main.v 19 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR_IN,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. output SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. input SNES_SYSCLK,
  36. input [7:0] SNES_PA,
  37. input SNES_PARD,
  38. input SNES_PAWR,
  39. /* SRAM signals */
  40. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  41. inout [15:0] ROM_DATA,
  42. output [22:0] ROM_ADDR,
  43. output ROM_CE,
  44. output ROM_OE,
  45. output ROM_WE,
  46. output ROM_BHE,
  47. output ROM_BLE,
  48. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  49. inout [7:0] RAM_DATA,
  50. output [18:0] RAM_ADDR,
  51. output RAM_CE,
  52. output RAM_OE,
  53. output RAM_WE,
  54. /* MCU signals */
  55. input SPI_MOSI,
  56. inout SPI_MISO,
  57. input SPI_SS,
  58. inout SPI_SCK,
  59. input MCU_OVR,
  60. output MCU_RDY,
  61. output DAC_MCLK,
  62. output DAC_LRCK,
  63. output DAC_SDOUT,
  64. /* SD signals */
  65. input [3:0] SD_DAT,
  66. inout SD_CMD,
  67. inout SD_CLK,
  68. /* debug */
  69. output p113_out
  70. );
  71. wire CLK2;
  72. reg [23:0] SNES_ADDR_r [2:0];
  73. always @(posedge CLK2) begin
  74. SNES_ADDR_r[2] <= SNES_ADDR_r[1];
  75. SNES_ADDR_r[1] <= SNES_ADDR_r[0];
  76. SNES_ADDR_r[0] <= SNES_ADDR_IN;
  77. end
  78. wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
  79. wire dspx_dp_enable;
  80. wire [7:0] spi_cmd_data;
  81. wire [7:0] spi_param_data;
  82. wire [7:0] spi_input_data;
  83. wire [31:0] spi_byte_cnt;
  84. wire [2:0] spi_bit_cnt;
  85. wire [23:0] MCU_ADDR;
  86. wire [2:0] MAPPER;
  87. wire [23:0] SAVERAM_MASK;
  88. wire [23:0] ROM_MASK;
  89. wire [7:0] SD_DMA_SRAM_DATA;
  90. wire [1:0] SD_DMA_TGT;
  91. wire [10:0] SD_DMA_PARTIAL_START;
  92. wire [10:0] SD_DMA_PARTIAL_END;
  93. wire [10:0] dac_addr;
  94. //wire [7:0] dac_volume;
  95. wire [7:0] msu_volumerq_out;
  96. wire [6:0] msu_status_out;
  97. wire [31:0] msu_addressrq_out;
  98. wire [15:0] msu_trackrq_out;
  99. wire [13:0] msu_write_addr;
  100. wire [13:0] msu_ptr_addr;
  101. wire [7:0] MSU_SNES_DATA_IN;
  102. wire [7:0] MSU_SNES_DATA_OUT;
  103. wire [5:0] msu_status_reset_bits;
  104. wire [5:0] msu_status_set_bits;
  105. wire [14:0] bsx_regs;
  106. wire [7:0] BSX_SNES_DATA_IN;
  107. wire [7:0] BSX_SNES_DATA_OUT;
  108. wire [7:0] bsx_regs_reset_bits;
  109. wire [7:0] bsx_regs_set_bits;
  110. wire [59:0] rtc_data;
  111. wire [55:0] rtc_data_in;
  112. wire [59:0] srtc_rtc_data_out;
  113. wire [3:0] SRTC_SNES_DATA_IN;
  114. wire [7:0] SRTC_SNES_DATA_OUT;
  115. wire [7:0] DSPX_SNES_DATA_IN;
  116. wire [7:0] DSPX_SNES_DATA_OUT;
  117. wire [23:0] dspx_pgm_data;
  118. wire [10:0] dspx_pgm_addr;
  119. wire dspx_pgm_we;
  120. wire [15:0] dspx_dat_data;
  121. wire [10:0] dspx_dat_addr;
  122. wire dspx_dat_we;
  123. wire [7:0] featurebits;
  124. wire [23:0] MAPPED_SNES_ADDR;
  125. wire ROM_ADDR0;
  126. wire [9:0] bs_page;
  127. wire [8:0] bs_page_offset;
  128. wire bs_page_enable;
  129. sd_dma snes_sd_dma(
  130. .CLK(CLK2),
  131. .SD_DAT(SD_DAT),
  132. .SD_CLK(SD_CLK),
  133. .SD_DMA_EN(SD_DMA_EN),
  134. .SD_DMA_STATUS(SD_DMA_STATUS),
  135. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  136. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  137. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  138. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  139. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  140. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  141. .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
  142. .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
  143. );
  144. wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
  145. dac snes_dac(
  146. .clkin(CLK2),
  147. .sysclk(SNES_SYSCLK),
  148. .mclk(DAC_MCLK),
  149. .lrck(DAC_LRCK),
  150. .sdout(DAC_SDOUT),
  151. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  152. .pgm_address(dac_addr),
  153. .pgm_data(SD_DMA_SRAM_DATA),
  154. .DAC_STATUS(DAC_STATUS),
  155. .volume(msu_volumerq_out),
  156. .vol_latch(msu_volume_latch_out),
  157. .play(dac_play),
  158. .reset(dac_reset)
  159. );
  160. srtc snes_srtc (
  161. .clkin(CLK2),
  162. .addr_in(SNES_ADDR[0]),
  163. .data_in(SRTC_SNES_DATA_IN),
  164. .data_out(SRTC_SNES_DATA_OUT),
  165. .rtc_data_in(rtc_data),
  166. .reg_we(SNES_WRITE),
  167. .reg_oe(SNES_READ),
  168. .enable(srtc_enable),
  169. .rtc_data_out(srtc_rtc_data_out),
  170. .rtc_we(srtc_rtc_we),
  171. .reset(srtc_reset)
  172. );
  173. rtc snes_rtc (
  174. .clkin(CLKIN),
  175. .rtc_data(rtc_data),
  176. .rtc_data_in(rtc_data_in),
  177. .pgm_we(rtc_pgm_we),
  178. .rtc_data_in1(srtc_rtc_data_out),
  179. .we1(srtc_rtc_we)
  180. );
  181. msu snes_msu (
  182. .clkin(CLK2),
  183. .enable(msu_enable),
  184. .pgm_address(msu_write_addr),
  185. .pgm_data(SD_DMA_SRAM_DATA),
  186. .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
  187. .reg_addr(SNES_ADDR[2:0]),
  188. .reg_data_in(MSU_SNES_DATA_IN),
  189. .reg_data_out(MSU_SNES_DATA_OUT),
  190. .reg_oe(SNES_READ),
  191. .reg_we(SNES_WRITE),
  192. .status_out(msu_status_out),
  193. .volume_out(msu_volumerq_out),
  194. .volume_latch_out(msu_volume_latch_out),
  195. .addr_out(msu_addressrq_out),
  196. .track_out(msu_trackrq_out),
  197. .status_reset_bits(msu_status_reset_bits),
  198. .status_set_bits(msu_status_set_bits),
  199. .status_reset_we(msu_status_reset_we),
  200. .msu_address_ext(msu_ptr_addr),
  201. .msu_address_ext_write(msu_addr_reset)
  202. );
  203. bsx snes_bsx(
  204. .clkin(CLK2),
  205. .use_bsx(use_bsx),
  206. .pgm_we(bsx_regs_reset_we),
  207. .snes_addr(SNES_ADDR),
  208. .reg_data_in(BSX_SNES_DATA_IN),
  209. .reg_data_out(BSX_SNES_DATA_OUT),
  210. .reg_oe(SNES_READ),
  211. .reg_we(SNES_WRITE),
  212. .regs_out(bsx_regs),
  213. .reg_reset_bits(bsx_regs_reset_bits),
  214. .reg_set_bits(bsx_regs_set_bits),
  215. .data_ovr(bsx_data_ovr),
  216. .flash_writable(IS_FLASHWR),
  217. .rtc_data(rtc_data[59:0]),
  218. .bs_page_out(bs_page), // support only page 0000-03ff
  219. .bs_page_enable(bs_page_enable),
  220. .bs_page_offset(bs_page_offset)
  221. );
  222. spi snes_spi(
  223. .clk(CLK2),
  224. .MOSI(SPI_MOSI),
  225. .MISO(SPI_MISO),
  226. .SSEL(SPI_SS),
  227. .SCK(SPI_SCK),
  228. .cmd_ready(spi_cmd_ready),
  229. .param_ready(spi_param_ready),
  230. .cmd_data(spi_cmd_data),
  231. .param_data(spi_param_data),
  232. .endmessage(spi_endmessage),
  233. .startmessage(spi_startmessage),
  234. .input_data(spi_input_data),
  235. .byte_cnt(spi_byte_cnt),
  236. .bit_cnt(spi_bit_cnt)
  237. );
  238. upd77c25 snes_dspx (
  239. .DI(DSPX_SNES_DATA_IN),
  240. .DO(DSPX_SNES_DATA_OUT),
  241. .A0(DSPX_A0),
  242. .nCS(~dspx_enable),
  243. .nRD(SNES_READ),
  244. .nWR(SNES_WRITE),
  245. .RST(~dspx_reset),
  246. .CLK(CLK2),
  247. .PGM_WR(dspx_pgm_we),
  248. .PGM_DI(dspx_pgm_data),
  249. .PGM_WR_ADDR(dspx_pgm_addr),
  250. .DAT_WR(dspx_dat_we),
  251. .DAT_DI(dspx_dat_data),
  252. .DAT_WR_ADDR(dspx_dat_addr),
  253. .DP_nCS(~dspx_dp_enable),
  254. .DP_ADDR(SNES_ADDR[10:0])
  255. );
  256. reg [7:0] MCU_DINr;
  257. wire [7:0] MCU_DOUT;
  258. mcu_cmd snes_mcu_cmd(
  259. .clk(CLK2),
  260. .snes_sysclk(SNES_SYSCLK),
  261. .cmd_ready(spi_cmd_ready),
  262. .param_ready(spi_param_ready),
  263. .cmd_data(spi_cmd_data),
  264. .param_data(spi_param_data),
  265. .mcu_mapper(MAPPER),
  266. .mcu_write(MCU_WRITE),
  267. .mcu_data_in(MCU_DINr),
  268. .mcu_data_out(MCU_DOUT),
  269. .spi_byte_cnt(spi_byte_cnt),
  270. .spi_bit_cnt(spi_bit_cnt),
  271. .spi_data_out(spi_input_data),
  272. .addr_out(MCU_ADDR),
  273. .saveram_mask_out(SAVERAM_MASK),
  274. .rom_mask_out(ROM_MASK),
  275. .SD_DMA_EN(SD_DMA_EN),
  276. .SD_DMA_STATUS(SD_DMA_STATUS),
  277. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  278. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  279. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  280. .SD_DMA_TGT(SD_DMA_TGT),
  281. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  282. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  283. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  284. .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
  285. .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
  286. .dac_addr_out(dac_addr),
  287. .DAC_STATUS(DAC_STATUS),
  288. // .dac_volume_out(dac_volume),
  289. // .dac_volume_latch_out(dac_vol_latch),
  290. .dac_play_out(dac_play),
  291. .dac_reset_out(dac_reset),
  292. .msu_addr_out(msu_write_addr),
  293. .MSU_STATUS(msu_status_out),
  294. .msu_status_reset_out(msu_status_reset_bits),
  295. .msu_status_set_out(msu_status_set_bits),
  296. .msu_status_reset_we(msu_status_reset_we),
  297. .msu_volumerq(msu_volumerq_out),
  298. .msu_addressrq(msu_addressrq_out),
  299. .msu_trackrq(msu_trackrq_out),
  300. .msu_ptr_out(msu_ptr_addr),
  301. .msu_reset_out(msu_addr_reset),
  302. .bsx_regs_set_out(bsx_regs_set_bits),
  303. .bsx_regs_reset_out(bsx_regs_reset_bits),
  304. .bsx_regs_reset_we(bsx_regs_reset_we),
  305. .rtc_data_out(rtc_data_in),
  306. .rtc_pgm_we(rtc_pgm_we),
  307. .srtc_reset(srtc_reset),
  308. .dspx_pgm_data_out(dspx_pgm_data),
  309. .dspx_pgm_addr_out(dspx_pgm_addr),
  310. .dspx_pgm_we_out(dspx_pgm_we),
  311. .dspx_dat_data_out(dspx_dat_data),
  312. .dspx_dat_addr_out(dspx_dat_addr),
  313. .dspx_dat_we_out(dspx_dat_we),
  314. .dspx_reset_out(dspx_reset),
  315. .featurebits_out(featurebits),
  316. .mcu_rrq(MCU_RRQ),
  317. .mcu_wrq(MCU_WRQ),
  318. .mcu_rq_rdy(MCU_RDY),
  319. .region_out(mcu_region)
  320. );
  321. wire [7:0] DCM_STATUS;
  322. // dcm1: dfs 4x
  323. my_dcm snes_dcm(
  324. .CLKIN(CLKIN),
  325. .CLKFX(CLK2),
  326. .LOCKED(DCM_LOCKED),
  327. .RST(DCM_RST),
  328. .STATUS(DCM_STATUS)
  329. );
  330. assign DCM_RST=0;
  331. reg [7:0] SNES_PARDr;
  332. reg [7:0] SNES_PAWRr;
  333. reg [7:0] SNES_READr;
  334. reg [7:0] SNES_WRITEr;
  335. reg [7:0] SNES_CPU_CLKr;
  336. wire SNES_FAKE_CLK = &SNES_CPU_CLKr[2:1];
  337. //wire SNES_FAKE_CLK = ~(SNES_READ & SNES_WRITE);
  338. reg SNES_DEADr;
  339. initial SNES_DEADr = 0;
  340. wire SNES_PARD_start = (SNES_PARDr[7:1] == 7'b1111110);
  341. wire SNES_PAWR_start = (SNES_PAWRr[7:1] == 7'b0000001);
  342. wire SNES_RD_start = (SNES_READr[7:1] == 7'b1111110);
  343. wire SNES_WR_start = (SNES_WRITEr[7:1] == 7'b1111110);
  344. wire SNES_WR_end = (SNES_WRITEr[7:1] == 7'b0000001);
  345. wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000001);
  346. wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b111110);
  347. always @(posedge CLK2) begin
  348. SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD};
  349. end
  350. always @(posedge CLK2) begin
  351. SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR};
  352. SNES_READr <= {SNES_READr[6:0], SNES_READ};
  353. SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE};
  354. SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK};
  355. end
  356. address snes_addr(
  357. .CLK(CLK2),
  358. .MAPPER(MAPPER),
  359. .featurebits(featurebits),
  360. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  361. .SNES_PA(SNES_PA),
  362. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  363. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  364. .IS_SAVERAM(IS_SAVERAM),
  365. .IS_ROM(IS_ROM),
  366. .IS_WRITABLE(IS_WRITABLE),
  367. .SAVERAM_MASK(SAVERAM_MASK),
  368. .ROM_MASK(ROM_MASK),
  369. //MSU-1
  370. .msu_enable(msu_enable),
  371. //BS-X
  372. .use_bsx(use_bsx),
  373. .bsx_regs(bsx_regs),
  374. .bs_page_offset(bs_page_offset),
  375. .bs_page(bs_page),
  376. .bs_page_enable(bs_page_enable),
  377. //SRTC
  378. .srtc_enable(srtc_enable),
  379. //uPD77C25
  380. .dspx_enable(dspx_enable),
  381. .dspx_dp_enable(dspx_dp_enable),
  382. .dspx_a0(DSPX_A0),
  383. .r213f_enable(r213f_enable),
  384. .snescmd_rd_enable(snescmd_rd_enable),
  385. .snescmd_wr_enable(snescmd_wr_enable)
  386. );
  387. parameter MODE_SNES = 1'b0;
  388. parameter MODE_MCU = 1'b1;
  389. parameter ST_IDLE = 18'b000000000000000001;
  390. parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
  391. parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
  392. parameter ST_SNES_RD_END = 18'b000000000000001000;
  393. parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
  394. parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
  395. parameter ST_SNES_WR_DATA = 18'b000000000001000000;
  396. parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
  397. parameter ST_SNES_WR_END = 18'b000000000100000000;
  398. parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
  399. parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
  400. parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
  401. parameter ST_MCU_RD_END = 18'b000001000000000000;
  402. parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
  403. parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
  404. parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
  405. parameter ST_MCU_WR_END = 18'b010000000000000000;
  406. parameter ROM_RD_WAIT = 4'h4;
  407. parameter ROM_RD_WAIT_MCU = 4'h6;
  408. parameter ROM_WR_WAIT1 = 4'h2;
  409. parameter ROM_WR_WAIT2 = 4'h3;
  410. parameter ROM_WR_WAIT_MCU = 4'h6;
  411. reg [17:0] STATE;
  412. initial STATE = ST_IDLE;
  413. reg [7:0] SNES_DINr;
  414. reg [7:0] ROM_DOUTr;
  415. assign DSPX_SNES_DATA_IN = SNES_DATA;
  416. assign SRTC_SNES_DATA_IN = SNES_DATA[3:0];
  417. assign MSU_SNES_DATA_IN = SNES_DATA;
  418. assign BSX_SNES_DATA_IN = bs_page_enable ? SNES_DINr : SNES_DATA;
  419. reg [7:0] r213fr;
  420. reg r213f_forceread;
  421. reg [2:0] r213f_delay;
  422. reg [1:0] r213f_state;
  423. initial r213fr = 8'h55;
  424. initial r213f_forceread = 0;
  425. initial r213f_state = 2'b01;
  426. initial r213f_delay = 3'b011;
  427. reg[7:0] snescmd_regs[15:0];
  428. assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
  429. :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
  430. :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
  431. ? (srtc_enable ? SRTC_SNES_DATA_OUT
  432. :dspx_enable ? DSPX_SNES_DATA_OUT
  433. :dspx_dp_enable ? DSPX_SNES_DATA_OUT
  434. :msu_enable ? MSU_SNES_DATA_OUT
  435. :bsx_data_ovr ? BSX_SNES_DATA_OUT
  436. :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
  437. reg [3:0] ST_MEM_DELAYr;
  438. reg MCU_RD_PENDr;
  439. reg MCU_WR_PENDr;
  440. reg [23:0] ROM_ADDRr;
  441. reg NEED_SNES_ADDRr;
  442. always @(posedge CLK2) begin
  443. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  444. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  445. end
  446. wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
  447. assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
  448. assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  449. reg ROM_WEr;
  450. initial ROM_WEr = 1'b1;
  451. reg RQ_MCU_RDYr;
  452. initial RQ_MCU_RDYr = 1'b1;
  453. assign MCU_RDY = RQ_MCU_RDYr;
  454. always @(posedge CLK2) begin
  455. if(MCU_RRQ) begin
  456. MCU_RD_PENDr <= 1'b1;
  457. RQ_MCU_RDYr <= 1'b0;
  458. end else if(MCU_WRQ) begin
  459. MCU_WR_PENDr <= 1'b1;
  460. RQ_MCU_RDYr <= 1'b0;
  461. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  462. MCU_RD_PENDr <= 1'b0;
  463. MCU_WR_PENDr <= 1'b0;
  464. RQ_MCU_RDYr <= 1'b1;
  465. end
  466. end
  467. reg snes_wr_cycle;
  468. always @(posedge CLK2) begin
  469. if(SNES_cycle_start & ~SNES_WR_start) begin
  470. STATE <= ST_SNES_RD_ADDR;
  471. end else if(SNES_WR_start) begin
  472. STATE <= ST_SNES_WR_ADDR;
  473. end else begin
  474. case(STATE)
  475. ST_IDLE: begin
  476. ROM_ADDRr <= MAPPED_SNES_ADDR;
  477. if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
  478. else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
  479. else STATE <= ST_IDLE;
  480. end
  481. ST_SNES_RD_ADDR: begin
  482. STATE <= ST_SNES_RD_WAIT;
  483. ST_MEM_DELAYr <= ROM_RD_WAIT;
  484. end
  485. ST_SNES_RD_WAIT: begin
  486. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  487. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
  488. else STATE <= ST_SNES_RD_WAIT;
  489. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
  490. else SNES_DINr <= ROM_DATA[15:8];
  491. end
  492. ST_SNES_RD_END: begin
  493. STATE <= ST_IDLE;
  494. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
  495. else SNES_DINr <= ROM_DATA[15:8];
  496. end
  497. ST_SNES_WR_ADDR: begin
  498. ROM_WEr <= (!IS_FLASHWR & !IS_WRITABLE);
  499. snes_wr_cycle <= 1'b1;
  500. STATE <= ST_SNES_WR_WAIT1;
  501. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  502. end
  503. ST_SNES_WR_WAIT1: begin
  504. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  505. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
  506. else STATE <= ST_SNES_WR_WAIT1;
  507. end
  508. ST_SNES_WR_DATA: begin
  509. ROM_DOUTr <= SNES_DATA;
  510. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  511. STATE <= ST_SNES_WR_WAIT2;
  512. end
  513. ST_SNES_WR_WAIT2: begin
  514. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  515. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
  516. else STATE <= ST_SNES_WR_WAIT2;
  517. end
  518. ST_SNES_WR_END: begin
  519. STATE <= ST_IDLE;
  520. ROM_WEr <= 1'b1;
  521. snes_wr_cycle <= 1'b0;
  522. end
  523. ST_MCU_RD_ADDR: begin
  524. ROM_ADDRr <= MCU_ADDR;
  525. STATE <= ST_MCU_RD_WAIT;
  526. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  527. end
  528. ST_MCU_RD_WAIT: begin
  529. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  530. if(ST_MEM_DELAYr == 4'h0) begin
  531. STATE <= ST_MCU_RD_WAIT2;
  532. ST_MEM_DELAYr <= 4'h2;
  533. end
  534. else STATE <= ST_MCU_RD_WAIT;
  535. if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
  536. else MCU_DINr <= ROM_DATA[15:8];
  537. end
  538. ST_MCU_RD_WAIT2: begin
  539. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  540. if(ST_MEM_DELAYr == 4'h0) begin
  541. STATE <= ST_MCU_RD_END;
  542. end else STATE <= ST_MCU_RD_WAIT2;
  543. end
  544. ST_MCU_RD_END: begin
  545. STATE <= ST_IDLE;
  546. end
  547. ST_MCU_WR_ADDR: begin
  548. ROM_ADDRr <= MCU_ADDR;
  549. STATE <= ST_MCU_WR_WAIT;
  550. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  551. ROM_DOUTr <= MCU_DOUT;
  552. ROM_WEr <= 1'b0;
  553. end
  554. ST_MCU_WR_WAIT: begin
  555. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  556. if(ST_MEM_DELAYr == 4'h0) begin
  557. ROM_WEr <= 1'b1;
  558. STATE <= ST_MCU_WR_WAIT2;
  559. ST_MEM_DELAYr <= 4'h2;
  560. end
  561. else STATE <= ST_MCU_WR_WAIT;
  562. end
  563. ST_MCU_WR_WAIT2: begin
  564. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  565. if(ST_MEM_DELAYr == 4'h0) begin
  566. STATE <= ST_MCU_WR_END;
  567. end else STATE <= ST_MCU_WR_WAIT2;
  568. end
  569. ST_MCU_WR_END: begin
  570. STATE <= ST_IDLE;
  571. end
  572. endcase
  573. end
  574. end
  575. always @(posedge SYSCLK2) begin
  576. if(SNES_PARD_start & r213f_enable) begin
  577. r213f_forceread <= 1'b1;
  578. r213f_delay <= 3'b001;
  579. r213f_state <= 2'b10;
  580. end else if(r213f_state == 2'b10) begin
  581. r213f_delay <= r213f_delay - 1;
  582. if(r213f_delay == 3'b000) begin
  583. r213f_forceread <= 1'b0;
  584. r213f_state <= 2'b01;
  585. r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
  586. end
  587. end
  588. end
  589. always @(posedge CLK2) begin
  590. if(SNES_WR_end & snescmd_wr_enable) begin
  591. snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
  592. end
  593. end
  594. reg ROM_WE_1;
  595. reg MCU_WRITE_1;
  596. always @(posedge CLK2) begin
  597. ROM_WE_1 <= ROM_WE;
  598. MCU_WRITE_1<= MCU_WRITE;
  599. end
  600. assign ROM_DATA[7:0] = ROM_ADDR0
  601. ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  602. /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
  603. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
  604. )
  605. :8'bZ;
  606. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  607. :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  608. /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
  609. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
  610. );
  611. assign ROM_WE = SD_DMA_TO_ROM
  612. ?MCU_WRITE
  613. :/*(SNES_FAKE_CLK & (IS_WRITABLE | IS_FLASHWR)) ? SNES_WRITE :*/ ROM_WEr;
  614. // OE always active. Overridden by WE when needed.
  615. assign ROM_OE = 1'b0;
  616. assign ROM_CE = 1'b0;
  617. assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
  618. assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
  619. assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
  620. msu_enable ? 1'b0 :
  621. bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
  622. srtc_enable ? (SNES_READ & SNES_WRITE) :
  623. bs_page_enable ? (SNES_READ) :
  624. r213f_enable & !SNES_PARD ? 1'b0 :
  625. ((IS_ROM & SNES_CS)
  626. |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
  627. |(SNES_READ & SNES_WRITE)
  628. );
  629. assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable))
  630. ? 1'b1 ^ r213f_forceread
  631. : 1'b0;
  632. assign IRQ_DIR = 1'b0;
  633. assign SNES_IRQ = 1'bZ;
  634. assign p113_out = 1'b0;
  635. endmodule