main.v 14 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. inout SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. output IRQ_DIR,
  36. /* SRAM signals */
  37. inout [15:0] SRAM_DATA,
  38. output [19:0] SRAM_ADDR,
  39. output [3:0] SRAM_CE2,
  40. output SRAM_OE,
  41. output SRAM_WE,
  42. output SRAM_BHE,
  43. output SRAM_BLE,
  44. /* AVR signals */
  45. input SPI_MOSI,
  46. inout SPI_MISO,
  47. input SPI_SS,
  48. inout SPI_SCK,
  49. input AVR_ENA,
  50. inout SPI_DMA_CTRL
  51. /* debug */
  52. //output DCM_IN_STOPPED,
  53. //output DCM_FX_STOPPED
  54. //input DCM_RST
  55. );
  56. wire [7:0] spi_cmd_data;
  57. wire [7:0] spi_param_data;
  58. wire [7:0] spi_input_data;
  59. wire [31:0] spi_byte_cnt;
  60. wire [2:0] spi_bit_cnt;
  61. wire [23:0] AVR_ADDR;
  62. wire [7:0] avr_data_in;
  63. wire [7:0] avr_data_out;
  64. wire [7:0] AVR_IN_DATA;
  65. wire [7:0] AVR_OUT_DATA;
  66. wire [3:0] MAPPER;
  67. wire [23:0] SAVERAM_MASK;
  68. wire [23:0] ROM_MASK;
  69. wire [23:0] spi_dma_addr;
  70. wire [7:0] spi_dma_sram_data;
  71. wire spi_dma_trig = SPI_DMA_CTRL;
  72. spi snes_spi(.clk(CLK2),
  73. .MOSI(SPI_MOSI),
  74. .MISO(SPI_MISO),
  75. .SSEL(SPI_SS),
  76. .SCK(SPI_SCK),
  77. .cmd_ready(spi_cmd_ready),
  78. .param_ready(spi_param_ready),
  79. .cmd_data(spi_cmd_data),
  80. .param_data(spi_param_data),
  81. .endmessage(spi_endmessage),
  82. .startmessage(spi_startmessage),
  83. .input_data(spi_input_data),
  84. .byte_cnt(spi_byte_cnt),
  85. .bit_cnt(spi_bit_cnt),
  86. .spi_dma_sck(spi_dma_sck),
  87. .spi_dma_ovr(spi_dma_ovr)
  88. );
  89. avr_cmd snes_avr_cmd(
  90. .clk(CLK2),
  91. .cmd_ready(spi_cmd_ready),
  92. .param_ready(spi_param_ready),
  93. .cmd_data(spi_cmd_data),
  94. .param_data(spi_param_data),
  95. .avr_mapper(MAPPER),
  96. .avr_sram_size(SRAM_SIZE),
  97. .avr_read(AVR_READ),
  98. .avr_write(AVR_WRITE),
  99. .avr_data_in(AVR_OUT_DATA),
  100. .avr_data_out(AVR_IN_DATA),
  101. .spi_byte_cnt(spi_byte_cnt),
  102. .spi_bit_cnt(spi_bit_cnt),
  103. .spi_data_out(spi_input_data),
  104. .addr_out(AVR_ADDR),
  105. .endmessage(spi_endmessage),
  106. .startmessage(spi_startmessage),
  107. .saveram_mask_out(SAVERAM_MASK),
  108. .rom_mask_out(ROM_MASK),
  109. .spi_dma_ovr(spi_dma_ovr),
  110. .spi_dma_nextaddr(spi_dma_nextaddr),
  111. .spi_dma_sram_data(spi_dma_sram_data),
  112. .spi_dma_sram_we(spi_dma_sram_we)
  113. );
  114. spi_dma snes_spi_dma(
  115. .clk(CLK2),
  116. .spi_dma_ovr(spi_dma_ovr), // to spi, avr_cmd
  117. .spi_dma_miso(SPI_MISO), // to spi
  118. .spi_dma_sck(spi_dma_sck), // to spi
  119. .spi_dma_trig(spi_dma_trig), // from avr
  120. .spi_dma_nextaddr(spi_dma_nextaddr), // to avr_cmd?
  121. .spi_dma_sram_data(spi_dma_sram_data), // to avr_cmd?
  122. .spi_dma_sram_we(spi_dma_sram_we), // to avr_cmd?
  123. .spi_dma_done(spi_dma_done) // to avr
  124. );
  125. assign SPI_DMA_CTRL = spi_dma_ovr ? 1'b0 : 1'bZ;
  126. // dcm1: dfs 4x
  127. my_dcm snes_dcm(.CLKIN(CLKIN),
  128. .CLKFX(CLK2),
  129. .LOCKED(DCM_LOCKED),
  130. .RST(DCM_RST),
  131. .STATUS(DCM_STATUS)
  132. );
  133. assign DCM_RST=0;
  134. /*
  135. dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
  136. .Q(DCM_RST)
  137. );
  138. */
  139. //wire DCM_FX_STOPPED = DCM_STATUS[2];
  140. //always @(posedge CLKIN) begin
  141. // if(DCM_FX_STOPPED)
  142. // DCM_RSTr <= 1'b1;
  143. // else
  144. // DCM_RSTr <= 1'b0;
  145. //end
  146. /*reg DO_DCM_RESET, DCM_RESETTING;
  147. reg DCM_RSTr;
  148. assign DCM_RST = DCM_RSTr;
  149. reg [2:0] DCM_RESET_CNT;
  150. initial DO_DCM_RESET = 1'b0;
  151. initial DCM_RESETTING = 1'b0;
  152. always @(posedge CLKIN) begin
  153. if(!DCM_LOCKED && !DCM_RESETTING) begin
  154. DCM_RSTr <= 1'b1;
  155. DO_DCM_RESET <= 1'b1;
  156. DCM_RESET_CNT <= 3'b0;
  157. end else if (DO_DCM_RESET) begin
  158. DCM_RSTr <= 1'b0;
  159. DCM_RESET_CNT <= DCM_RESET_CNT + 1;
  160. end
  161. end
  162. always @(posedge CLKIN) begin
  163. if (DO_DCM_RESET)
  164. DCM_RESETTING <= 1'b1;
  165. else if (DCM_RESET_CNT == 3'b110)
  166. DCM_RESETTING <= 1'b0;
  167. end
  168. */
  169. wire SNES_RW;
  170. reg [1:0] SNES_READr;
  171. reg [1:0] SNES_WRITEr;
  172. reg [1:0] SNES_CSr;
  173. reg [5:0] SNES_CPU_CLKr;
  174. reg [5:0] SNES_RWr;
  175. reg [23:0] SNES_ADDRr;
  176. reg [23:0] SNES_ADDR_PREVr;
  177. reg [3:0] SNES_ADDRCHGr;
  178. wire SNES_READs = (SNES_READr == 2'b11);
  179. wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
  180. wire SNES_CSs = (SNES_CSr == 2'b11);
  181. wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
  182. wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
  183. wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001);
  184. wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
  185. wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
  186. assign SNES_RW = (SNES_READ & SNES_WRITE);
  187. always @(posedge CLK2) begin
  188. SNES_READr <= {SNES_READr[0], SNES_READ};
  189. SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
  190. SNES_CSr <= {SNES_CSr[0], SNES_CS};
  191. SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
  192. SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
  193. end
  194. reg ADDR_WRITE;
  195. //reg [23:0] SNES_ADDRr;
  196. //wire [23:0] SNES_ADDRw = SNES_ADDR;
  197. address snes_addr(
  198. .CLK(CLK2),
  199. .MAPPER(MAPPER),
  200. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  201. .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
  202. .SRAM_ADDR(SRAM_ADDR), // Address to request from SRAM (active low)
  203. .ROM_SEL(SRAM_CE2), // which SRAM unit to access
  204. .AVR_ENA(AVR_ENA), // enable AVR mode (active low)
  205. .MODE(MODE), // AVR(1) or SNES(0) ("bus phase")
  206. .IS_SAVERAM(IS_SAVERAM),
  207. .IS_ROM(IS_ROM),
  208. .AVR_ADDR(AVR_ADDR),
  209. .SRAM_ADDR0(SRAM_ADDR0),
  210. .SAVERAM_MASK(SAVERAM_MASK),
  211. .ROM_MASK(ROM_MASK)
  212. );
  213. wire SNES_READ_CYCLEw;
  214. wire SNES_WRITE_CYCLEw;
  215. wire AVR_READ_CYCLEw;
  216. wire AVR_WRITE_CYCLEw;
  217. data snes_data(.CLK(CLK2),
  218. .SNES_READ(SNES_READ),
  219. .SNES_WRITE(SNES_WRITE),
  220. .AVR_READ(AVR_READ),
  221. .AVR_WRITE(AVR_WRITE),
  222. .SNES_DATA(SNES_DATA),
  223. .SRAM_DATA(SRAM_DATA),
  224. .MODE(MODE),
  225. .SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
  226. .AVR_DATA_TO_MEM(AVR_DATA_TO_MEM),
  227. .SRAM_DATA_TO_SNES_MEM(SRAM_DATA_TO_SNES_MEM),
  228. .SRAM_DATA_TO_AVR_MEM(SRAM_DATA_TO_AVR_MEM),
  229. .AVR_ENA(AVR_ENA),
  230. .AVR_IN_DATA(AVR_IN_DATA),
  231. .AVR_OUT_DATA(AVR_OUT_DATA),
  232. .SRAM_ADDR0(SRAM_ADDR0)
  233. );
  234. parameter MODE_SNES = 1'b0;
  235. parameter MODE_AVR = 1'b1;
  236. parameter STATE_0 = 13'b0000000000001;
  237. parameter STATE_1 = 13'b0000000000010;
  238. parameter STATE_2 = 13'b0000000000100;
  239. parameter STATE_3 = 13'b0000000001000;
  240. parameter STATE_4 = 13'b0000000010000;
  241. parameter STATE_5 = 13'b0000000100000;
  242. parameter STATE_6 = 13'b0000001000000;
  243. parameter STATE_7 = 13'b0000010000000;
  244. parameter STATE_8 = 13'b0000100000000;
  245. parameter STATE_9 = 13'b0001000000000;
  246. parameter STATE_10 = 13'b0010000000000;
  247. parameter STATE_11 = 13'b0100000000000;
  248. parameter STATE_IDLE = 13'b1000000000000;
  249. reg [12:0] STATE;
  250. reg [3:0] STATEIDX;
  251. reg [1:0] CYCLE_RESET;
  252. reg SRAM_WE_MASK;
  253. reg SRAM_OE_MASK;
  254. reg [12:0] SRAM_WE_ARRAY [3:0];
  255. reg [12:0] SRAM_OE_ARRAY [3:0];
  256. reg [12:0] SNES_DATA_TO_MEM_ARRAY[1:0];
  257. reg [12:0] AVR_DATA_TO_MEM_ARRAY[1:0];
  258. reg [12:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0];
  259. reg [12:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0];
  260. reg [12:0] MODE_ARRAY;
  261. reg SNES_READ_CYCLE;
  262. reg SNES_WRITE_CYCLE;
  263. reg AVR_READ_CYCLE;
  264. reg AVR_WRITE_CYCLE;
  265. reg AVR_SPI_WRITEONCE;
  266. reg AVR_SPI_READONCE;
  267. reg AVR_SPI_WRITE;
  268. reg AVR_SPI_READ;
  269. reg AVR_SPI_ADDR_INCREMENT;
  270. reg [7:0] AVR_DATA_IN;
  271. reg [3:0] MAPPER_BUF;
  272. reg SNES_DATABUS_OE_BUF;
  273. reg SNES_DATABUS_DIR_BUF;
  274. assign MODE = !AVR_ENA ? MODE_AVR : MODE_ARRAY[STATEIDX];
  275. initial begin
  276. CYCLE_RESET = 2'b0;
  277. STATE = STATE_IDLE;
  278. STATEIDX = 12;
  279. SRAM_WE_MASK = 1'b1;
  280. SRAM_OE_MASK = 1'b1;
  281. SNES_READ_CYCLE = 1'b1;
  282. SNES_WRITE_CYCLE = 1'b1;
  283. AVR_READ_CYCLE = 1'b1;
  284. AVR_WRITE_CYCLE = 1'b1;
  285. MODE_ARRAY = 13'b0_000000_111111;
  286. SRAM_WE_ARRAY[2'b00] = 13'b1_000000_000000;
  287. SRAM_WE_ARRAY[2'b01] = 13'b1_000000_111111;
  288. SRAM_WE_ARRAY[2'b10] = 13'b1_111111_000000;
  289. SRAM_WE_ARRAY[2'b11] = 13'b1_111111_111111;
  290. SRAM_OE_ARRAY[2'b00] = 13'b1_111111_111111;
  291. SRAM_OE_ARRAY[2'b01] = 13'b1_111111_000000;
  292. SRAM_OE_ARRAY[2'b10] = 13'b0_000000_111111;
  293. SRAM_OE_ARRAY[2'b11] = 13'b0_000000_000000;
  294. SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_001000_000000; // SNES write
  295. /* 13'b0001000000000 */
  296. SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // SNES read
  297. AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111; // AVR write
  298. // AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // AVR write
  299. AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // AVR read
  300. SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0_000000_000000; // SNES write
  301. SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0_000100_000000; // SNES read
  302. /* 13'b0000100000000; */
  303. SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0_000000_000000; // AVR write
  304. SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0_000000_000001; // AVR read
  305. // SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001; // AVR read
  306. end
  307. // falling edge of SNES /RD or /WR marks the beginning of a new cycle
  308. // SNES READ or WRITE always starts @posedge CLK !!
  309. // CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
  310. // the minimum of 6 SNES cycles to get everything done.
  311. // we have 24 internal cycles to work with. (CLKIN * 4)
  312. always @(posedge CLK2) begin
  313. CYCLE_RESET <= {CYCLE_RESET[0], SNES_RW_start};
  314. end
  315. always @(posedge CLK2) begin
  316. AVR_READ_CYCLE <= AVR_READ;
  317. AVR_WRITE_CYCLE <= AVR_WRITE;
  318. if (SNES_RW_start) begin
  319. SNES_READ_CYCLE <= SNES_READ;
  320. SNES_WRITE_CYCLE <= SNES_WRITE;
  321. STATE <= STATE_0;
  322. STATEIDX <= 11;
  323. end else begin
  324. case (STATE)
  325. STATE_0: begin
  326. STATE <= STATE_1; STATEIDX <= 10;
  327. end
  328. STATE_1: begin
  329. STATE <= STATE_2; STATEIDX <= 9;
  330. end
  331. STATE_2: begin
  332. STATE <= STATE_3; STATEIDX <= 8;
  333. end
  334. STATE_3: begin
  335. STATE <= STATE_4; STATEIDX <= 7;
  336. end
  337. STATE_4: begin
  338. STATE <= STATE_5; STATEIDX <= 6;
  339. end
  340. STATE_5: begin
  341. STATE <= STATE_6; STATEIDX <= 5;
  342. end
  343. STATE_6: begin
  344. STATE <= STATE_7; STATEIDX <= 4;
  345. end
  346. STATE_7: begin
  347. STATE <= STATE_8; STATEIDX <= 3;
  348. end
  349. STATE_8: begin
  350. STATE <= STATE_9; STATEIDX <= 2;
  351. end
  352. STATE_9: begin
  353. STATE <= STATE_10; STATEIDX <= 1;
  354. end
  355. STATE_10: begin
  356. STATE <= STATE_11; STATEIDX <= 0;
  357. end
  358. STATE_11: begin
  359. STATE <= STATE_IDLE; STATEIDX <= 12;
  360. end
  361. STATE_IDLE: begin
  362. STATE <= STATE_IDLE; STATEIDX <= 12;
  363. end
  364. default: begin
  365. STATE <= STATE_IDLE; STATEIDX <= 12;
  366. end
  367. endcase
  368. end
  369. end
  370. /*
  371. always @(posedge CLK2) begin
  372. case (STATE)
  373. STATE_9: begin
  374. STATEIDX <= 9;
  375. end
  376. STATE_0: begin
  377. STATEIDX <= 8;
  378. end
  379. STATE_1: begin
  380. STATEIDX <= 7;
  381. end
  382. STATE_2: begin
  383. STATEIDX <= 6;
  384. end
  385. STATE_3: begin
  386. STATEIDX <= 5;
  387. end
  388. STATE_4: begin
  389. STATEIDX <= 4;
  390. end
  391. STATE_5: begin
  392. STATEIDX <= 3;
  393. end
  394. STATE_6: begin
  395. STATEIDX <= 2;
  396. end
  397. STATE_7: begin
  398. STATEIDX <= 1;
  399. end
  400. STATE_8: begin
  401. STATEIDX <= 0;
  402. end
  403. default:
  404. STATEIDX <= 9;
  405. endcase
  406. end
  407. */
  408. // When in AVR mode, enable SRAM_WE according to AVR programming
  409. // else enable SRAM_WE according to state&cycle
  410. assign SRAM_WE = !AVR_ENA ? AVR_WRITE
  411. : ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]);
  412. // When in AVR mode, enable SRAM_OE whenever not writing
  413. // else enable SRAM_OE according to state&cycle
  414. assign SRAM_OE = !AVR_ENA ? AVR_READ
  415. : SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
  416. assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
  417. assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
  418. //assign SRAM_BHE = SRAM_ADDR0;
  419. //assign SRAM_BLE = ~SRAM_ADDR0;
  420. // dumb version
  421. //assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
  422. //assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
  423. //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
  424. assign SNES_DATABUS_OE = (IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM) | (SNES_READ & SNES_WRITE);
  425. assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
  426. assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
  427. assign AVR_DATA_TO_MEM = AVR_DATA_TO_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
  428. assign SRAM_DATA_TO_SNES_MEM = SRAM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
  429. assign SRAM_DATA_TO_AVR_MEM = SRAM_DATA_TO_AVR_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
  430. assign SNES_READ_CYCLEw = SNES_READ_CYCLE;
  431. assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
  432. assign IRQ_DIR = 1'b0;
  433. assign SNES_IRQ = 1'bZ;
  434. endmodule