tf_main.v 3.2 KB

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  1. `timescale 1ns / 1ps
  2. ////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 23:11:58 05/13/2009
  7. // Design Name: main
  8. // Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/tf_main.v
  9. // Project Name: sd2snes
  10. // Target Device:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Verilog Test Fixture created by ISE for module: main
  15. //
  16. // Dependencies:
  17. //
  18. // Revision:
  19. // Revision 0.01 - File Created
  20. // Additional Comments:
  21. //
  22. ////////////////////////////////////////////////////////////////////////////////
  23. module tf_main;
  24. // Inputs
  25. reg CLK;
  26. reg [2:0] MAPPER;
  27. reg [23:0] SNES_ADDR;
  28. reg SNES_READ;
  29. reg SNES_WRITE;
  30. reg SNES_CS;
  31. reg AVR_ENA;
  32. // Outputs
  33. wire [20:0] SRAM_ADDR;
  34. wire [3:0] ROM_SEL;
  35. wire SRAM_OE;
  36. wire SRAM_WE;
  37. wire SNES_DATABUS_OE;
  38. wire SNES_DATABUS_DIR;
  39. wire MODE;
  40. // Bidirs
  41. wire [7:0] SNES_DATA;
  42. wire [7:0] SRAM_DATA;
  43. wire [7:0] AVR_DATA;
  44. reg [7:0] SRAM_DATA_BUF;
  45. reg [7:0] SNES_DATA_BUF;
  46. SCK = 0;
  47. MOSI = 0;
  48. SSEL = 1;
  49. input_data = 0;
  50. // Wait 100 ns for global reset to finish
  51. #100;
  52. // Add stimulus here
  53. SSEL = 0;
  54. MOSI=1;
  55. #100 SCK=1;
  56. #100 SCK=0;
  57. MOSI=0;
  58. #100 SCK=1;
  59. #100 SCK=0;
  60. MOSI=0;
  61. #100 SCK=1;
  62. #100 SCK=0;
  63. MOSI=1;
  64. #100 SCK=1;
  65. #100 SCK=0;
  66. MOSI=0;
  67. #100 SCK=1;
  68. #100 SCK=0;
  69. #100 SCK=1;
  70. #100 SCK=0;
  71. #100 SCK=1;
  72. #100 SCK=0;
  73. #100 SCK=1;
  74. #100 SCK=0;
  75. #200;
  76. #100 SCK=1;
  77. #100 SCK=0;
  78. #100 SCK=1;
  79. #100 SCK=0;
  80. #100 SCK=1;
  81. #100 SCK=0;
  82. #100 SCK=1;
  83. #100 SCK=0;
  84. #100 SCK=1;
  85. #100 SCK=0;
  86. #100 SCK=1;
  87. #100 SCK=0;
  88. #100 SCK=1;
  89. #100 SCK=0;
  90. #100 SCK=1;
  91. #100 SCK=0;
  92. #200;
  93. #100 SCK=1;
  94. #100 SCK=0;
  95. #100 SCK=1;
  96. #100 SCK=0;
  97. #100 SCK=1;
  98. #100 SCK=0;
  99. #100 SCK=1;
  100. #100 SCK=0;
  101. #100 SCK=1;
  102. #100 SCK=0;
  103. #100 SCK=1;
  104. #100 SCK=0;
  105. #100 SCK=1;
  106. #100 SCK=0;
  107. #100 SCK=1;
  108. #100 SCK=0;
  109. #100 SSEL=1;
  110. end
  111. always begin
  112. #19 clk = ~clk;
  113. end
  114. // Instantiate the Unit Under Test (UUT)
  115. main uut (
  116. .CLKIN(CLK),
  117. .MAPPER(MAPPER),
  118. .SNES_ADDR(SNES_ADDR),
  119. .SNES_READ(SNES_READ),
  120. .SNES_WRITE(SNES_WRITE),
  121. .SNES_CS(SNES_CS),
  122. .SNES_DATA(SNES_DATA),
  123. .SRAM_DATA(SRAM_DATA),
  124. .SRAM_ADDR(SRAM_ADDR),
  125. .ROM_SEL(ROM_SEL),
  126. .SRAM_OE(SRAM_OE),
  127. .SRAM_WE(SRAM_WE),
  128. .AVR_ENA(AVR_ENA),
  129. .SNES_DATABUS_OE(SNES_DATABUS_OE),
  130. .SNES_DATABUS_DIR(SNES_DATABUS_DIR),
  131. .MODE(MODE)
  132. );
  133. assign SRAM_DATA = SRAM_DATA_BUF;
  134. initial begin
  135. // Initialize Inputs
  136. CLK = 1;
  137. MAPPER = 0;
  138. SNES_ADDR = 24'h223456;
  139. SNES_READ = 1;
  140. SNES_WRITE = 1;
  141. SNES_CS = 0;
  142. AVR_ENA = 1;
  143. SRAM_DATA_BUF = 8'hff;
  144. // Wait for global reset to finish
  145. #276;
  146. SNES_ADDR <= 24'h123456;
  147. SNES_READ <= 0;
  148. #176;
  149. SNES_READ <= 1;
  150. #100;
  151. SNES_WRITE <= 0;
  152. #176;
  153. SNES_WRITE <= 1;
  154. #100;
  155. SNES_READ <= 0;
  156. #276;
  157. // AVR_READ <= 1;
  158. // Add stimulus here
  159. end
  160. always
  161. #23 CLK <= ~CLK;
  162. // always begin
  163. // end
  164. endmodule