address.v 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: address
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Address logic w/ SaveRAM masking
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.02 - All new combinatorial glory. fucking slow.
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module address(
  22. input CLK,
  23. input [2:0] MAPPER, // AVR detected mapper
  24. input [23:0] SNES_ADDR, // requested address from SNES
  25. input SNES_CS, // "CART" pin from SNES (active low)
  26. output [19:0] SRAM_ADDR, // Address to request from SRAM
  27. output [3:0] ROM_SEL, // which SRAM unit to access (active low)
  28. input AVR_ENA, // enable AVR master mode (active low)
  29. input MODE, // AVR(1) or SNES(0) ("bus phase")
  30. output IS_SAVERAM, // address/CS mapped as SRAM?
  31. output IS_ROM, // address mapped as ROM?
  32. input [23:0] AVR_ADDR, // allow address to be set externally
  33. input ADDR_WRITE,
  34. output SRAM_BHE,
  35. output SRAM_BLE,
  36. output SRAM_ADDR0
  37. );
  38. reg [22:0] SRAM_ADDR_BUF;
  39. reg [3:0] ROM_SEL_BUF;
  40. reg [3:0] AVR_ROM_SEL_BUF;
  41. reg [3:0] CS_ARRAY[3:0];
  42. reg [1:0] AVR_BANK;
  43. wire [3:0] CURRENT_ROM_SEL;
  44. wire [22:0] SRAM_ADDR_FULL;
  45. initial begin
  46. CS_ARRAY[0] = 4'b0001;
  47. CS_ARRAY[1] = 4'b0010;
  48. CS_ARRAY[2] = 4'b0100;
  49. CS_ARRAY[3] = 4'b1000;
  50. AVR_BANK = 2'b0;
  51. end
  52. /* currently supported mappers:
  53. Index Mapper
  54. 000 HiROM
  55. 001 LoROM
  56. */
  57. /* HiROM: SRAM @ Bank 0x20-0x3f, 0xa0-0xbf
  58. Offset 6000-7fff */
  59. assign IS_SAVERAM = ((MAPPER == 3'b000) ? (!SNES_ADDR[22]
  60. & SNES_ADDR[21]
  61. & &SNES_ADDR[14:13]
  62. & !SNES_ADDR[15]
  63. )
  64. /* LoROM: SRAM @ Bank 0x70-0x7f, 0xf0-0xff
  65. Offset 0000-7fff */
  66. :(MAPPER == 3'b001) ? (&SNES_ADDR[22:20]
  67. & (SNES_ADDR[19:16] < 4'b1110)
  68. & !SNES_ADDR[15]
  69. & !SNES_CS)
  70. : 1'b0);
  71. assign IS_ROM = ( (MAPPER == 3'b000) ? ( (!SNES_ADDR[22]
  72. & SNES_ADDR[15])
  73. |(SNES_ADDR[22]))
  74. : (MAPPER == 3'b001) ? ( (SNES_ADDR[15] & !SNES_ADDR[22])
  75. |(SNES_ADDR[22]) )
  76. : 1'b0);
  77. assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR
  78. : ((MAPPER == 3'b000) ?
  79. (IS_SAVERAM ? SNES_ADDR[14:0] - 15'h6000
  80. : SNES_ADDR[22:0])
  81. :(MAPPER == 3'b001) ?
  82. (IS_SAVERAM ? SNES_ADDR[14:0]
  83. : {1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]})
  84. : 21'b0);
  85. assign SRAM_BANK = SRAM_ADDR_FULL[22:21];
  86. assign SRAM_ADDR = SRAM_ADDR_FULL[20:1];
  87. // XXX assign ROM_SEL = (MODE) ? CS_ARRAY[AVR_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
  88. assign ROM_SEL = 4'b0001;
  89. assign SRAM_BHE = !AVR_ENA ? SRAM_ADDR_FULL[0] : 1'b0;
  90. assign SRAM_BLE = !AVR_ENA ? !SRAM_ADDR_FULL[0] : 1'b0;
  91. assign SRAM_ADDR0 = SRAM_ADDR_FULL[0];
  92. endmodule