memory.c 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141
  1. // insert cool lenghty disclaimer here
  2. // memory.c: ROM+RAM operations
  3. #include <stdint.h>
  4. #include <avr/pgmspace.h>
  5. #include <util/delay.h>
  6. #include "config.h"
  7. #include "uart.h"
  8. #include "fpga.h"
  9. #include "crc16.h"
  10. #include "ff.h"
  11. #include "fileops.h"
  12. #include "spi.h"
  13. #include "fpga_spi.h"
  14. #include "avrcompat.h"
  15. #include "led.h"
  16. char* hex = "0123456789ABCDEF";
  17. uint32_t load_rom(char* filename) {
  18. // TODO Mapper, Mirroring, Bankselect
  19. // snes_rom_properties_t romprops;
  20. // set_avr_bank(0);
  21. UINT bytes_read;
  22. DWORD filesize;
  23. UINT count=0;
  24. file_open(filename, FA_READ);
  25. filesize = file_handle.fsize;
  26. if(file_res) {
  27. uart_putc('?');
  28. uart_putc(0x30+file_res);
  29. return 0;
  30. }
  31. // snes_rom_id(&romprops, &file_handle);
  32. for(;;) {
  33. FPGA_SS_HIGH();
  34. SPI_SS_LOW();
  35. bytes_read = file_read();
  36. SPI_SS_HIGH();
  37. if (file_res || !bytes_read) break;
  38. FPGA_SS_LOW();
  39. _delay_us(1);
  40. spiTransferByte(0x91); // write w/ increment
  41. if(!(count++ % 16)) {
  42. toggle_busy_led();
  43. }
  44. for(int j=0; j<bytes_read; j++) {
  45. spiTransferByte(file_buf[j]);
  46. // uart_putc((file_buf[j] > 0x20)
  47. // && (file_buf[j] < ('z'+1)) ? file_buf[j]:'.');
  48. // _delay_ms(2);
  49. }
  50. spiTransferByte(0x00); // dummy tx for increment+write pulse
  51. _delay_us(10);
  52. FPGA_SS_HIGH();
  53. }
  54. file_close();
  55. return (uint32_t)filesize;
  56. }
  57. uint32_t load_sram(char* filename) {
  58. set_avr_bank(3);
  59. AVR_ADDR_RESET();
  60. SET_AVR_READ();
  61. UINT bytes_read;
  62. DWORD filesize;
  63. file_open(filename, FA_READ);
  64. filesize = file_handle.fsize;
  65. if(file_res) return 0;
  66. for(;;) {
  67. bytes_read = file_read();
  68. if (file_res || !bytes_read) break;
  69. for(int j=0; j<bytes_read; j++) {
  70. SET_AVR_DATA(file_buf[j]);
  71. AVR_WRITE();
  72. AVR_NEXTADDR();
  73. }
  74. }
  75. file_close();
  76. return (uint32_t)filesize;
  77. }
  78. void save_sram(char* filename, uint32_t sram_size) {
  79. uint32_t count = 0;
  80. uint32_t num = 0;
  81. set_avr_bank(3);
  82. _delay_us(100);
  83. AVR_ADDR_RESET();
  84. CLR_AVR_READ();
  85. SET_AVR_WRITE();
  86. file_open(filename, FA_CREATE_ALWAYS | FA_WRITE);
  87. while(count<sram_size) {
  88. for(int j=0; j<sizeof(file_buf); j++) {
  89. _delay_us(5);
  90. file_buf[j] = AVR_DATA;
  91. CLR_AVR_ADDR_EN();
  92. SET_AVR_NEXTADDR();
  93. _delay_us(5);
  94. CLR_AVR_NEXTADDR();
  95. SET_AVR_ADDR_EN();
  96. count++;
  97. }
  98. num = file_write();
  99. }
  100. file_close();
  101. }
  102. uint32_t calc_sram_crc(uint32_t size) {
  103. uint8_t data;
  104. set_avr_bank(3);
  105. _delay_us(100);
  106. AVR_ADDR_RESET();
  107. SET_AVR_WRITE();
  108. CLR_AVR_READ();
  109. uint32_t count;
  110. uint16_t crc;
  111. crc=0;
  112. for(count=0; count<size; count++) {
  113. _delay_us(5);
  114. data = AVR_DATA;
  115. crc += crc16_update(crc, &data, 1);
  116. CLR_AVR_ADDR_EN();
  117. SET_AVR_NEXTADDR();
  118. _delay_us(5);
  119. CLR_AVR_NEXTADDR();
  120. SET_AVR_ADDR_EN();
  121. }
  122. /* uart_putc(hex[(crc>>28)&0xf]);
  123. uart_putc(hex[(crc>>24)&0xf]);
  124. uart_putc(hex[(crc>>20)&0xf]);
  125. uart_putc(hex[(crc>>16)&0xf]); */
  126. uart_putc(hex[(crc>>12)&0xf]);
  127. uart_putc(hex[(crc>>8)&0xf]);
  128. uart_putc(hex[(crc>>4)&0xf]);
  129. uart_putc(hex[(crc)&0xf]);
  130. uart_putcrlf();
  131. return crc;
  132. }