main.c 8.4 KB

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  1. /* sd2iec - SD/MMC to Commodore serial bus interface/controller
  2. Copyright (C) 2007-2009 Ingo Korb <ingo@akana.de>
  3. Inspiration and low-level SD/MMC access based on code from MMC2IEC
  4. by Lars Pontoppidan et al., see sdcard.c|h and config.h.
  5. FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; version 2 of the License only.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. main.c: Lots of init calls for the submodules
  17. */
  18. #include <stdio.h>
  19. #include <string.h>
  20. #include <avr/boot.h>
  21. #include <avr/interrupt.h>
  22. #include <avr/pgmspace.h>
  23. #include <avr/power.h>
  24. #include <avr/wdt.h>
  25. #include <util/delay.h>
  26. #include "config.h"
  27. #include "diskio.h"
  28. #include "ff.h"
  29. #include "led.h"
  30. #include "timer.h"
  31. #include "fpga.h"
  32. #include "uart.h"
  33. #include "ustring.h"
  34. #include "utils.h"
  35. #include "snes.h"
  36. #include "fileops.h"
  37. #include "memory.h"
  38. #include "fpga_spi.h"
  39. #include "spi.h"
  40. #include "avrcompat.h"
  41. #include "filetypes.h"
  42. /* Make sure the watchdog is disabled as soon as possible */
  43. /* Copy this code to your bootloader if you use one and your */
  44. /* MCU doesn't disable the WDT after reset! */
  45. void get_mcusr(void) \
  46. __attribute__((naked)) \
  47. __attribute__((section(".init3")));
  48. void get_mcusr(void)
  49. {
  50. MCUSR = 0;
  51. wdt_disable();
  52. }
  53. #ifdef CONFIG_MEMPOISON
  54. void poison_memory(void) \
  55. __attribute__((naked)) \
  56. __attribute__((section(".init1")));
  57. void poison_memory(void) {
  58. register uint16_t i;
  59. register uint8_t *ptr;
  60. asm("clr r1\n");
  61. /* There is no RAMSTARt variable =( */
  62. if (RAMEND > 2048 && RAMEND < 4096) {
  63. /* 2K memory */
  64. ptr = (void *)RAMEND-2047;
  65. for (i=0;i<2048;i++)
  66. ptr[i] = 0x55;
  67. } else if (RAMEND > 4096 && RAMEND < 8192) {
  68. /* 4K memory */
  69. ptr = (void *)RAMEND-4095;
  70. for (i=0;i<4096;i++)
  71. ptr[i] = 0x55;
  72. } else {
  73. /* Assume 8K memory */
  74. ptr = (void *)RAMEND-8191;
  75. for (i=0;i<8192;i++)
  76. ptr[i] = 0x55;
  77. }
  78. }
  79. #endif
  80. void avr_goto_addr(const uint32_t val) {
  81. AVR_ADDR_RESET();
  82. for(uint32_t i=0; i<val; i++) {
  83. AVR_NEXTADDR();
  84. }
  85. }
  86. #if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 1)
  87. int main(void) __attribute__((OS_main));
  88. #endif
  89. int main(void) {
  90. #if defined __AVR_ATmega644__ || defined __AVR_ATmega644P__ || defined __AVR_ATmega2561__
  91. asm volatile("in r24, %0\n"
  92. "ori r24, 0x80\n"
  93. "out %0, r24\n"
  94. "out %0, r24\n"
  95. :
  96. : "I" (_SFR_IO_ADDR(MCUCR))
  97. : "r24"
  98. );
  99. #elif defined __AVR_ATmega32__
  100. asm volatile ("in r24, %0\n"
  101. "ori r24, 0x80\n"
  102. "out %0, r24\n"
  103. "out %0, r24\n"
  104. :
  105. : "I" (_SFR_IO_ADDR(MCUCSR))
  106. : "r24"
  107. );
  108. #elif defined __AVR_ATmega128__ || defined __AVR_ATmega1281__
  109. /* Just assume that JTAG doesn't hurt us on the m128 */
  110. #else
  111. # error Unknown chip!
  112. #endif
  113. #ifdef CLOCK_PRESCALE
  114. clock_prescale_set(CLOCK_PRESCALE);
  115. #endif
  116. set_pwr_led(0);
  117. set_busy_led(1);
  118. spi_none();
  119. snes_reset(1);
  120. uart_init();
  121. sei(); // suspected to reset the AVR when inserting an SD card
  122. _delay_ms(100);
  123. disk_init();
  124. snes_init();
  125. timer_init();
  126. uart_puts_P(PSTR("\nsd2snes " VERSION));
  127. uart_putcrlf();
  128. file_init();
  129. FATFS fatfs;
  130. f_mount(0,&fatfs);
  131. uart_putc('W');
  132. fpga_init();
  133. fpga_pgm((uint8_t*)"/sd2snes/main.bit");
  134. _delay_ms(100);
  135. set_pwr_led(1);
  136. fpga_spi_init();
  137. uart_putc('!');
  138. _delay_ms(100);
  139. restart:
  140. set_avr_ena(0);
  141. snes_reset(1);
  142. *fs_path=0;
  143. uint16_t saved_dir_id;
  144. get_db_id(&saved_dir_id);
  145. uint16_t mem_dir_id = sram_readshort(SRAM_DIRID);
  146. uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD);
  147. if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id)) {
  148. uint16_t curr_dir_id = scan_dir(fs_path, 0, 0); // generate files footprint
  149. dprintf("curr dir id = %x\n", curr_dir_id);
  150. if((get_db_id(&saved_dir_id) != FR_OK) // no database?
  151. || saved_dir_id != curr_dir_id) { // files changed? // XXX
  152. dprintf("saved dir id = %x\n", saved_dir_id);
  153. _delay_ms(50);
  154. dprintf("rebuilding database...");
  155. _delay_ms(50);
  156. curr_dir_id = scan_dir(fs_path, 1, 0); // then rebuild database
  157. sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 2);
  158. uint32_t endaddr, direndaddr;
  159. sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4);
  160. sram_readblock(&direndaddr, SRAM_DB_ADDR+8, 4);
  161. dprintf("%lx %lx\n", endaddr, direndaddr);
  162. save_sram((uint8_t*)"/sd2snes/sd2snes.db", endaddr-SRAM_DB_ADDR, SRAM_DB_ADDR);
  163. save_sram((uint8_t*)"/sd2snes/sd2snes.dir", direndaddr-(SRAM_DIR_ADDR), SRAM_DIR_ADDR);
  164. dprintf("done\n");
  165. sram_hexdump(SRAM_DB_ADDR, 0x400);
  166. } else {
  167. dprintf("different card, consistent db, loading db...\n");
  168. load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
  169. load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
  170. }
  171. // save_sram((uint8_t*)"/debug.smc", 0x400000, 0);
  172. // uart_putc('[');
  173. // load_sram((uint8_t*)"/test.srm", SRAM_SAVE_ADDR);
  174. // uart_putc(']');
  175. sram_writeshort(curr_dir_id, SRAM_DIRID);
  176. sram_writelong(0x12345678, SRAM_SCRATCHPAD);
  177. } else {
  178. dprintf("same card, loading db...\n");
  179. load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
  180. load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
  181. }
  182. led_pwm();
  183. uart_putc('(');
  184. load_rom((uint8_t*)"/sd2snes/menu.bin");
  185. set_rom_mask(0x3fffff); // force mirroring off
  186. uart_putc(')');
  187. sram_writebyte(0, SRAM_CMD_ADDR);
  188. set_busy_led(0);
  189. set_avr_ena(1);
  190. _delay_ms(100);
  191. uart_puts_P(PSTR("SNES GO!\r\n"));
  192. snes_reset(0);
  193. uint8_t cmd = 0;
  194. while(!sram_reliable());
  195. while(!cmd) {
  196. cmd=menu_main_loop();
  197. switch(cmd) {
  198. case 0x01: // SNES_CMD_LOADROM:
  199. get_selected_name(file_lfn);
  200. _delay_ms(100);
  201. // snes_reset(1);
  202. set_avr_ena(0);
  203. dprintf("Selected name: %s\n", file_lfn);
  204. load_rom(file_lfn);
  205. if(romprops.ramsize_bytes) {
  206. strcpy(strrchr((char*)file_lfn, (int)'.'), ".srm");
  207. dprintf("SRM file: %s\n", file_lfn);
  208. load_sram(file_lfn, SRAM_SAVE_ADDR);
  209. } else {
  210. dprintf("No SRAM\n");
  211. }
  212. set_avr_ena(1);
  213. snes_reset(1);
  214. _delay_ms(100);
  215. snes_reset(0);
  216. break;
  217. default:
  218. dprintf("unknown cmd: %d\n", cmd);
  219. cmd=0; // unknown cmd: stay in loop
  220. break;
  221. }
  222. }
  223. dprintf("cmd was %x, going to snes main loop\n", cmd);
  224. led_std();
  225. cmd=0;
  226. uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
  227. uint16_t reset_count=0;
  228. while(fpga_test() == 0xa5) {
  229. snes_reset_now=get_snes_reset();
  230. if(snes_reset_now) {
  231. if(!snes_reset_prev) {
  232. dprintf("RESET BUTTON DOWN\n");
  233. snes_reset_state=1;
  234. // reset reset counter
  235. reset_count=0;
  236. }
  237. } else {
  238. if(snes_reset_prev) {
  239. dprintf("RESET BUTTON UP\n");
  240. snes_reset_state=0;
  241. }
  242. }
  243. if(snes_reset_state) {
  244. _delay_ms(10);
  245. reset_count++;
  246. } else {
  247. sram_reliable();
  248. snes_main_loop();
  249. }
  250. if(reset_count>100) {
  251. reset_count=0;
  252. led_std();
  253. set_avr_ena(0);
  254. snes_reset(1);
  255. _delay_ms(100);
  256. if(romprops.ramsize_bytes && fpga_test() == 0xa5) {
  257. set_busy_led(1);
  258. save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
  259. set_busy_led(0);
  260. }
  261. _delay_ms(1000);
  262. set_busy_led(1);
  263. goto restart;
  264. }
  265. snes_reset_prev = snes_reset_now;
  266. }
  267. // FPGA TEST FAIL. PANIC.
  268. led_std();
  269. while(1) {
  270. set_pwr_led(1);
  271. set_busy_led(1);
  272. _delay_ms(150);
  273. set_pwr_led(0);
  274. set_busy_led(0);
  275. _delay_ms(150);
  276. }
  277. /* HERE BE LIONS */
  278. while(1) {
  279. set_avr_addr(0x600000);
  280. spi_fpga();
  281. spiTransferByte(0x81); // read w/ increment... hopefully
  282. spiTransferByte(0x00); // 1 dummy read
  283. uart_putcrlf();
  284. uint8_t buff[21];
  285. for(uint8_t cnt=0; cnt<21; cnt++) {
  286. uint8_t data=spiTransferByte(0x00);
  287. buff[cnt]=data;
  288. }
  289. for(uint8_t cnt=0; cnt<21; cnt++) {
  290. uint8_t data = buff[cnt];
  291. _delay_ms(2);
  292. if(data>=0x20 && data <= 0x7a) {
  293. uart_putc(data);
  294. } else {
  295. // uart_putc('.');
  296. uart_putc("0123456789ABCDEF"[data>>4]);
  297. uart_putc("0123456789ABCDEF"[data&15]);
  298. uart_putc(' ');
  299. }
  300. // set_avr_bank(3);
  301. }
  302. spi_none();
  303. }
  304. while(1);
  305. }