main.v 18 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. inout SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. output IRQ_DIR,
  36. input SNES_SYSCLK,
  37. /* SRAM signals */
  38. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  39. inout [15:0] ROM_DATA,
  40. output [22:0] ROM_ADDR,
  41. output ROM_CE,
  42. output ROM_OE,
  43. output ROM_WE,
  44. output ROM_BHE,
  45. output ROM_BLE,
  46. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  47. inout [7:0] RAM_DATA,
  48. output [18:0] RAM_ADDR,
  49. output RAM_CE,
  50. output RAM_OE,
  51. output RAM_WE,
  52. /* MCU signals */
  53. input SPI_MOSI,
  54. inout SPI_MISO,
  55. input SPI_SS,
  56. inout SPI_SCK,
  57. input MCU_OVR,
  58. output DAC_MCLK,
  59. output DAC_LRCK,
  60. output DAC_SDOUT,
  61. /* SD signals */
  62. input [3:0] SD_DAT,
  63. inout SD_CMD,
  64. inout SD_CLK
  65. /* debug */
  66. //output DCM_IN_STOPPED,
  67. //output DCM_FX_STOPPED
  68. //input DCM_RST
  69. );
  70. wire [7:0] spi_cmd_data;
  71. wire [7:0] spi_param_data;
  72. wire [7:0] spi_input_data;
  73. wire [31:0] spi_byte_cnt;
  74. wire [2:0] spi_bit_cnt;
  75. wire [23:0] MCU_ADDR;
  76. wire [7:0] mcu_data_in;
  77. wire [7:0] mcu_data_out;
  78. wire [7:0] MCU_IN_DATA;
  79. wire [7:0] MCU_OUT_DATA;
  80. wire [3:0] MAPPER;
  81. wire [23:0] SAVERAM_MASK;
  82. wire [23:0] ROM_MASK;
  83. wire [7:0] SD_DMA_SRAM_DATA;
  84. wire [1:0] SD_DMA_TGT;
  85. wire [10:0] SD_DMA_PARTIAL_START;
  86. wire [10:0] SD_DMA_PARTIAL_END;
  87. wire [10:0] dac_addr;
  88. //wire [7:0] dac_volume;
  89. wire [7:0] msu_volumerq_out;
  90. wire [6:0] msu_status_out;
  91. wire [31:0] msu_addressrq_out;
  92. wire [15:0] msu_trackrq_out;
  93. wire [13:0] msu_write_addr;
  94. wire [13:0] msu_ptr_addr;
  95. wire [7:0] MSU_SNES_DATA_IN;
  96. wire [7:0] MSU_SNES_DATA_OUT;
  97. wire [5:0] msu_status_reset_bits;
  98. wire [5:0] msu_status_set_bits;
  99. wire [14:0] bsx_regs;
  100. wire [14:0] bsx_regs_in;
  101. wire [7:0] BSX_SNES_DATA_IN;
  102. wire [7:0] BSX_SNES_DATA_OUT;
  103. wire [7:0] bsx_regs_reset_bits;
  104. wire [7:0] bsx_regs_set_bits;
  105. //wire SD_DMA_EN; //SPI_DMA_CTRL;
  106. sd_dma snes_sd_dma(.CLK(CLK2),
  107. .SD_DAT(SD_DAT),
  108. .SD_CLK(SD_CLK),
  109. .SD_DMA_EN(SD_DMA_EN),
  110. .SD_DMA_STATUS(SD_DMA_STATUS),
  111. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  112. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  113. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  114. .SD_DMA_TGT(SD_DMA_TGT),
  115. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  116. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  117. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
  118. );
  119. dac_test snes_dac_test(.clkin(CLK2),
  120. .sysclk(SNES_SYSCLK),
  121. .mclk(DAC_MCLK),
  122. .lrck(DAC_LRCK),
  123. .sdout(DAC_SDOUT),
  124. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  125. .pgm_address(dac_addr),
  126. .pgm_data(SD_DMA_SRAM_DATA),
  127. .DAC_STATUS(DAC_STATUS),
  128. .volume(msu_volumerq_out),
  129. .vol_latch(msu_volume_latch_out),
  130. .play(dac_play),
  131. .reset(dac_reset)
  132. );
  133. msu snes_msu (
  134. .clkin(CLK2),
  135. .enable(msu_enable),
  136. .pgm_address(msu_write_addr),
  137. .pgm_data(SD_DMA_SRAM_DATA),
  138. .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
  139. .reg_addr(SNES_ADDR),
  140. .reg_data_in(MSU_SNES_DATA_IN),
  141. .reg_data_out(MSU_SNES_DATA_OUT),
  142. .reg_oe(SNES_READ),
  143. .reg_we(SNES_WRITE),
  144. .status_out(msu_status_out),
  145. .volume_out(msu_volumerq_out),
  146. .volume_latch_out(msu_volume_latch_out),
  147. .addr_out(msu_addressrq_out),
  148. .track_out(msu_trackrq_out),
  149. .status_reset_bits(msu_status_reset_bits),
  150. .status_set_bits(msu_status_set_bits),
  151. .status_reset_we(msu_status_reset_we),
  152. .msu_address_ext(msu_ptr_addr),
  153. .msu_address_ext_write(msu_addr_reset)
  154. );
  155. bsx snes_bsx(.clkin(CLK2),
  156. .use_bsx(use_bsx),
  157. .pgm_we(bsx_regs_reset_we),
  158. .snes_addr(SNES_ADDR),
  159. .reg_data_in(BSX_SNES_DATA_IN),
  160. .reg_data_out(BSX_SNES_DATA_OUT),
  161. .reg_oe(SNES_READ),
  162. .reg_we(SNES_WRITE),
  163. .regs_out(bsx_regs),
  164. .reg_reset_bits(bsx_regs_reset_bits),
  165. .reg_set_bits(bsx_regs_set_bits),
  166. .data_ovr(bsx_data_ovr),
  167. .flash_writable(IS_FLASHWR)
  168. );
  169. spi snes_spi(.clk(CLK2),
  170. .MOSI(SPI_MOSI),
  171. .MISO(SPI_MISO),
  172. .SSEL(SPI_SS),
  173. .SCK(SPI_SCK),
  174. .cmd_ready(spi_cmd_ready),
  175. .param_ready(spi_param_ready),
  176. .cmd_data(spi_cmd_data),
  177. .param_data(spi_param_data),
  178. .endmessage(spi_endmessage),
  179. .startmessage(spi_startmessage),
  180. .input_data(spi_input_data),
  181. .byte_cnt(spi_byte_cnt),
  182. .bit_cnt(spi_bit_cnt)
  183. );
  184. mcu_cmd snes_mcu_cmd(
  185. .clk(CLK2),
  186. .snes_sysclk(SNES_SYSCLK),
  187. .cmd_ready(spi_cmd_ready),
  188. .param_ready(spi_param_ready),
  189. .cmd_data(spi_cmd_data),
  190. .param_data(spi_param_data),
  191. .mcu_mapper(MAPPER),
  192. .mcu_sram_size(SRAM_SIZE),
  193. .mcu_read(MCU_READ),
  194. .mcu_write(MCU_WRITE),
  195. .mcu_data_in(MCU_OUT_DATA),
  196. .mcu_data_out(MCU_IN_DATA),
  197. .spi_byte_cnt(spi_byte_cnt),
  198. .spi_bit_cnt(spi_bit_cnt),
  199. .spi_data_out(spi_input_data),
  200. .addr_out(MCU_ADDR),
  201. .endmessage(spi_endmessage),
  202. .startmessage(spi_startmessage),
  203. .saveram_mask_out(SAVERAM_MASK),
  204. .rom_mask_out(ROM_MASK),
  205. .SD_DMA_EN(SD_DMA_EN),
  206. .SD_DMA_STATUS(SD_DMA_STATUS),
  207. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  208. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  209. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  210. .SD_DMA_TGT(SD_DMA_TGT),
  211. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  212. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  213. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  214. .dac_addr_out(dac_addr),
  215. .DAC_STATUS(DAC_STATUS),
  216. // .dac_volume_out(dac_volume),
  217. // .dac_volume_latch_out(dac_vol_latch),
  218. .dac_play_out(dac_play),
  219. .dac_reset_out(dac_reset),
  220. .msu_addr_out(msu_write_addr),
  221. .MSU_STATUS(msu_status_out),
  222. .msu_status_reset_out(msu_status_reset_bits),
  223. .msu_status_set_out(msu_status_set_bits),
  224. .msu_status_reset_we(msu_status_reset_we),
  225. .msu_volumerq(msu_volumerq_out),
  226. .msu_addressrq(msu_addressrq_out),
  227. .msu_trackrq(msu_trackrq_out),
  228. .msu_ptr_out(msu_ptr_addr),
  229. .msu_reset_out(msu_addr_reset),
  230. .bsx_regs_set_out(bsx_regs_set_bits),
  231. .bsx_regs_reset_out(bsx_regs_reset_bits),
  232. .bsx_regs_reset_we(bsx_regs_reset_we)
  233. );
  234. // dcm1: dfs 4x
  235. my_dcm snes_dcm(.CLKIN(CLKIN),
  236. .CLKFX(CLK2),
  237. .LOCKED(DCM_LOCKED),
  238. .RST(DCM_RST),
  239. .STATUS(DCM_STATUS)
  240. );
  241. assign DCM_RST=0;
  242. /*
  243. dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
  244. .Q(DCM_RST)
  245. );
  246. */
  247. //wire DCM_FX_STOPPED = DCM_STATUS[2];
  248. //always @(posedge CLKIN) begin
  249. // if(DCM_FX_STOPPED)
  250. // DCM_RSTr <= 1'b1;
  251. // else
  252. // DCM_RSTr <= 1'b0;
  253. //end
  254. /*reg DO_DCM_RESET, DCM_RESETTING;
  255. reg DCM_RSTr;
  256. assign DCM_RST = DCM_RSTr;
  257. reg [2:0] DCM_RESET_CNT;
  258. initial DO_DCM_RESET = 1'b0;
  259. initial DCM_RESETTING = 1'b0;
  260. always @(posedge CLKIN) begin
  261. if(!DCM_LOCKED && !DCM_RESETTING) begin
  262. DCM_RSTr <= 1'b1;
  263. DO_DCM_RESET <= 1'b1;
  264. DCM_RESET_CNT <= 3'b0;
  265. end else if (DO_DCM_RESET) begin
  266. DCM_RSTr <= 1'b0;
  267. DCM_RESET_CNT <= DCM_RESET_CNT + 1;
  268. end
  269. end
  270. always @(posedge CLKIN) begin
  271. if (DO_DCM_RESET)
  272. DCM_RESETTING <= 1'b1;
  273. else if (DCM_RESET_CNT == 3'b110)
  274. DCM_RESETTING <= 1'b0;
  275. end
  276. */
  277. wire SNES_RW;
  278. reg [1:0] SNES_READr;
  279. reg [1:0] SNES_WRITEr;
  280. reg [1:0] SNES_CSr;
  281. reg [5:0] SNES_CPU_CLKr;
  282. reg [5:0] SNES_RWr;
  283. reg [23:0] SNES_ADDRr;
  284. reg [23:0] SNES_ADDR_PREVr;
  285. reg [3:0] SNES_ADDRCHGr;
  286. wire SNES_READs = (SNES_READr == 2'b11);
  287. wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
  288. wire SNES_CSs = (SNES_CSr == 2'b11);
  289. wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
  290. wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
  291. wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001);
  292. wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
  293. wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
  294. assign SNES_RW = (SNES_READ & SNES_WRITE);
  295. always @(posedge CLK2) begin
  296. SNES_READr <= {SNES_READr[0], SNES_READ};
  297. SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
  298. SNES_CSr <= {SNES_CSr[0], SNES_CS};
  299. SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
  300. SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
  301. end
  302. reg ADDR_WRITE;
  303. //reg [23:0] SNES_ADDRr;
  304. //wire [23:0] SNES_ADDRw = SNES_ADDR;
  305. wire ROM_SEL;
  306. address snes_addr(
  307. .CLK(CLK2),
  308. .MAPPER(MAPPER),
  309. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  310. .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
  311. .ROM_ADDR(ROM_ADDR), // Address to request from SRAM (active low)
  312. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  313. .MCU_OVR(MCU_OVR), // enable MCU mode (active low)
  314. .MODE(MODE), // MCU(1) or SNES(0) ("bus phase")
  315. .IS_SAVERAM(IS_SAVERAM),
  316. .IS_ROM(IS_ROM),
  317. .IS_WRITABLE(IS_WRITABLE),
  318. .MCU_ADDR(MCU_ADDR),
  319. .ROM_ADDR0(ROM_ADDR0),
  320. .SAVERAM_MASK(SAVERAM_MASK),
  321. .ROM_MASK(ROM_MASK),
  322. //MSU-1
  323. .use_msu(use_msu),
  324. .msu_enable(msu_enable),
  325. //BS-X
  326. .use_bsx(use_bsx),
  327. .bsx_regs(bsx_regs)
  328. );
  329. wire SNES_READ_CYCLEw;
  330. wire SNES_WRITE_CYCLEw;
  331. wire MCU_READ_CYCLEw;
  332. wire MCU_WRITE_CYCLEw;
  333. data snes_data(.CLK(CLK2),
  334. .SNES_READ(SNES_READ),
  335. .SNES_WRITE(SNES_WRITE),
  336. .MCU_READ(MCU_READ),
  337. .MCU_WRITE(MCU_WRITE),
  338. .SNES_DATA(SNES_DATA),
  339. .ROM_DATA(ROM_DATA),
  340. .MODE(MODE),
  341. .SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
  342. .MCU_DATA_TO_MEM(MCU_DATA_TO_MEM),
  343. .ROM_DATA_TO_SNES_MEM(ROM_DATA_TO_SNES_MEM),
  344. .ROM_DATA_TO_MCU_MEM(ROM_DATA_TO_MCU_MEM),
  345. .MCU_OVR(MCU_OVR),
  346. .MCU_IN_DATA(MCU_IN_DATA),
  347. .MCU_OUT_DATA(MCU_OUT_DATA),
  348. .ROM_ADDR0(ROM_ADDR0),
  349. .MSU_DATA_IN(MSU_SNES_DATA_IN),
  350. .MSU_DATA_OUT(MSU_SNES_DATA_OUT),
  351. .BSX_DATA_IN(BSX_SNES_DATA_IN),
  352. .BSX_DATA_OUT(BSX_SNES_DATA_OUT),
  353. .msu_enable(msu_enable),
  354. .bsx_data_ovr(bsx_data_ovr)
  355. );
  356. parameter MODE_SNES = 1'b0;
  357. parameter MODE_MCU = 1'b1;
  358. parameter STATE_0 = 14'b00000000000001;
  359. parameter STATE_1 = 14'b00000000000010;
  360. parameter STATE_2 = 14'b00000000000100;
  361. parameter STATE_3 = 14'b00000000001000;
  362. parameter STATE_4 = 14'b00000000010000;
  363. parameter STATE_5 = 14'b00000000100000;
  364. parameter STATE_6 = 14'b00000001000000;
  365. parameter STATE_7 = 14'b00000010000000;
  366. parameter STATE_8 = 14'b00000100000000;
  367. parameter STATE_9 = 14'b00001000000000;
  368. parameter STATE_10 = 14'b00010000000000;
  369. parameter STATE_11 = 14'b00100000000000;
  370. parameter STATE_12 = 14'b01000000000000;
  371. parameter STATE_IDLE = 14'b10000000000000;
  372. reg [13:0] STATE;
  373. reg [3:0] STATEIDX;
  374. reg [1:0] CYCLE_RESET;
  375. reg ROM_WE_MASK;
  376. reg ROM_OE_MASK;
  377. reg [13:0] ROM_WE_ARRAY [3:0];
  378. reg [13:0] ROM_OE_ARRAY [3:0];
  379. reg [13:0] SNES_DATA_TO_MEM_ARRAY[1:0];
  380. reg [13:0] MCU_DATA_TO_MEM_ARRAY[1:0];
  381. reg [13:0] ROM_DATA_TO_SNES_MEM_ARRAY[1:0];
  382. reg [13:0] ROM_DATA_TO_MCU_MEM_ARRAY[1:0];
  383. reg [13:0] MODE_ARRAY;
  384. reg SNES_READ_CYCLE;
  385. reg SNES_WRITE_CYCLE;
  386. reg MCU_READ_CYCLE;
  387. reg MCU_WRITE_CYCLE;
  388. reg MCU_SPI_WRITEONCE;
  389. reg MCU_SPI_READONCE;
  390. reg MCU_SPI_WRITE;
  391. reg MCU_SPI_READ;
  392. reg MCU_SPI_ADDR_INCREMENT;
  393. reg [7:0] MCU_DATA_IN;
  394. reg [3:0] MAPPER_BUF;
  395. reg SNES_DATABUS_OE_BUF;
  396. reg SNES_DATABUS_DIR_BUF;
  397. assign MODE = !MCU_OVR ? MODE_MCU : MODE_ARRAY[STATEIDX];
  398. initial begin
  399. CYCLE_RESET = 2'b0;
  400. STATE = STATE_IDLE;
  401. STATEIDX = 13;
  402. ROM_WE_MASK = 1'b1;
  403. ROM_OE_MASK = 1'b1;
  404. SNES_READ_CYCLE = 1'b1;
  405. SNES_WRITE_CYCLE = 1'b1;
  406. MCU_READ_CYCLE = 1'b1;
  407. MCU_WRITE_CYCLE = 1'b1;
  408. MODE_ARRAY = 14'b0_000000_1111111;
  409. ROM_WE_ARRAY[2'b00] = 14'b1_000000_0000000;
  410. ROM_WE_ARRAY[2'b01] = 14'b1_000000_1111111;
  411. ROM_WE_ARRAY[2'b10] = 14'b1_111111_0000000;
  412. ROM_WE_ARRAY[2'b11] = 14'b1_111111_1111111;
  413. ROM_OE_ARRAY[2'b00] = 14'b1_111111_1111111;
  414. ROM_OE_ARRAY[2'b01] = 14'b1_111111_0000000;
  415. ROM_OE_ARRAY[2'b10] = 14'b0_000000_1111111;
  416. ROM_OE_ARRAY[2'b11] = 14'b0_000000_0000000;
  417. SNES_DATA_TO_MEM_ARRAY[1'b0] = 14'b0_000100_0000000; // SNES write
  418. /* 13'b0001000000000 */
  419. SNES_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // SNES read
  420. MCU_DATA_TO_MEM_ARRAY[1'b0] = 14'b1_111111_1111111; // MCU write
  421. // MCU_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // MCU write
  422. MCU_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // MCU read
  423. ROM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // SNES write
  424. ROM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 14'b0_000010_0000000; // SNES read
  425. /* 13'b0000100000000; */
  426. ROM_DATA_TO_MCU_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // MCU write
  427. ROM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 14'b0_000000_0000001; // MCU read
  428. // SRAM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 13'b0000000000001; // MCU read
  429. end
  430. // falling edge of SNES /RD or /WR marks the beginning of a new cycle
  431. // SNES READ or WRITE always starts @posedge CLK !!
  432. // CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
  433. // the minimum of 6 SNES cycles to get everything done.
  434. // we have 24 internal cycles to work with. (CLKIN * 4)
  435. always @(posedge CLK2) begin
  436. CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start};
  437. end
  438. always @(posedge CLK2) begin
  439. MCU_READ_CYCLE <= MCU_READ;
  440. MCU_WRITE_CYCLE <= MCU_WRITE;
  441. if (SNES_cycle_start) begin
  442. SNES_READ_CYCLE <= SNES_READ;
  443. SNES_WRITE_CYCLE <= SNES_WRITE;
  444. STATE <= STATE_0;
  445. STATEIDX <= 12;
  446. end else begin
  447. case (STATE)
  448. STATE_0: begin
  449. STATE <= STATE_1; STATEIDX <= 11;
  450. end
  451. STATE_1: begin
  452. STATE <= STATE_2; STATEIDX <= 10;
  453. end
  454. STATE_2: begin
  455. STATE <= STATE_3; STATEIDX <= 9;
  456. end
  457. STATE_3: begin
  458. STATE <= STATE_4; STATEIDX <= 8;
  459. end
  460. STATE_4: begin
  461. STATE <= STATE_5; STATEIDX <= 7;
  462. end
  463. STATE_5: begin
  464. STATE <= STATE_6; STATEIDX <= 6;
  465. end
  466. STATE_6: begin
  467. STATE <= STATE_7; STATEIDX <= 5;
  468. end
  469. STATE_7: begin
  470. STATE <= STATE_8; STATEIDX <= 4;
  471. end
  472. STATE_8: begin
  473. STATE <= STATE_9; STATEIDX <= 3;
  474. end
  475. STATE_9: begin
  476. STATE <= STATE_10; STATEIDX <= 2;
  477. end
  478. STATE_10: begin
  479. STATE <= STATE_11; STATEIDX <= 1;
  480. end
  481. STATE_11: begin
  482. STATE <= STATE_12; STATEIDX <= 0;
  483. end
  484. STATE_12: begin
  485. STATE <= STATE_IDLE; STATEIDX <= 13;
  486. end
  487. STATE_IDLE: begin
  488. STATE <= STATE_IDLE; STATEIDX <= 13;
  489. end
  490. default: begin
  491. STATE <= STATE_IDLE; STATEIDX <= 13;
  492. end
  493. endcase
  494. end
  495. end
  496. /*
  497. always @(posedge CLK2) begin
  498. case (STATE)
  499. STATE_9: begin
  500. STATEIDX <= 9;
  501. end
  502. STATE_0: begin
  503. STATEIDX <= 8;
  504. end
  505. STATE_1: begin
  506. STATEIDX <= 7;
  507. end
  508. STATE_2: begin
  509. STATEIDX <= 6;
  510. end
  511. STATE_3: begin
  512. STATEIDX <= 5;
  513. end
  514. STATE_4: begin
  515. STATEIDX <= 4;
  516. end
  517. STATE_5: begin
  518. STATEIDX <= 3;
  519. end
  520. STATE_6: begin
  521. STATEIDX <= 2;
  522. end
  523. STATE_7: begin
  524. STATEIDX <= 1;
  525. end
  526. STATE_8: begin
  527. STATEIDX <= 0;
  528. end
  529. default:
  530. STATEIDX <= 9;
  531. endcase
  532. end
  533. */
  534. // When in MCU mode, enable SRAM_WE according to MCU programming
  535. // else enable SRAM_WE according to state&cycle
  536. assign ROM_WE = !MCU_OVR ? MCU_WRITE
  537. : ((!IS_FLASHWR & !IS_WRITABLE & !MODE) | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]);
  538. // When in MCU mode, enable SRAM_OE whenever not writing
  539. // else enable SRAM_OE according to state&cycle
  540. assign ROM_OE = !MCU_OVR ? MCU_READ
  541. : ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
  542. assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL;
  543. assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
  544. assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
  545. //assign SRAM_BHE = SRAM_ADDR0;
  546. //assign SRAM_BLE = ~SRAM_ADDR0;
  547. // dumb version
  548. //assign SRAM_OE = !MCU_ENA ? MCU_READ : SNES_READs;
  549. //assign SRAM_WE = !MCU_ENA ? MCU_WRITE : 1'b1;
  550. //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
  551. assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
  552. bsx_data_ovr ? 1'b0 : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) | (SNES_READ & SNES_WRITE));
  553. assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
  554. assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
  555. assign MCU_DATA_TO_MEM = MCU_DATA_TO_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX];
  556. assign ROM_DATA_TO_SNES_MEM = ROM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
  557. assign ROM_DATA_TO_MCU_MEM = ROM_DATA_TO_MCU_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX];
  558. assign SNES_READ_CYCLEw = SNES_READ_CYCLE;
  559. assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
  560. assign IRQ_DIR = 1'b0;
  561. assign SNES_IRQ = 1'bZ;
  562. endmodule