dac_buf.v 4.7 KB

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  29. // The synthesis directives "translate_off/translate_on" specified below are
  30. // supported by Xilinx, Mentor Graphics and Synplicity synthesis
  31. // tools. Ensure they are correct for your synthesis tool(s).
  32. // You must compile the wrapper file dac_buf.v when simulating
  33. // the core, dac_buf. When compiling the wrapper file, be sure to
  34. // reference the XilinxCoreLib Verilog simulation library. For detailed
  35. // instructions, please refer to the "CORE Generator Help".
  36. `timescale 1ns/1ps
  37. module dac_buf(
  38. clka,
  39. wea,
  40. addra,
  41. dina,
  42. clkb,
  43. addrb,
  44. doutb);
  45. input clka;
  46. input [0 : 0] wea;
  47. input [10 : 0] addra;
  48. input [7 : 0] dina;
  49. input clkb;
  50. input [8 : 0] addrb;
  51. output [31 : 0] doutb;
  52. // synthesis translate_off
  53. BLK_MEM_GEN_V4_3 #(
  54. .C_ADDRA_WIDTH(11),
  55. .C_ADDRB_WIDTH(9),
  56. .C_ALGORITHM(1),
  57. .C_BYTE_SIZE(9),
  58. .C_COMMON_CLK(1),
  59. .C_DEFAULT_DATA("0"),
  60. .C_DISABLE_WARN_BHV_COLL(0),
  61. .C_DISABLE_WARN_BHV_RANGE(0),
  62. .C_FAMILY("spartan3"),
  63. .C_HAS_ENA(0),
  64. .C_HAS_ENB(0),
  65. .C_HAS_INJECTERR(0),
  66. .C_HAS_MEM_OUTPUT_REGS_A(0),
  67. .C_HAS_MEM_OUTPUT_REGS_B(0),
  68. .C_HAS_MUX_OUTPUT_REGS_A(0),
  69. .C_HAS_MUX_OUTPUT_REGS_B(0),
  70. .C_HAS_REGCEA(0),
  71. .C_HAS_REGCEB(0),
  72. .C_HAS_RSTA(0),
  73. .C_HAS_RSTB(0),
  74. .C_HAS_SOFTECC_INPUT_REGS_A(0),
  75. .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
  76. .C_INITA_VAL("0"),
  77. .C_INITB_VAL("0"),
  78. .C_INIT_FILE_NAME("no_coe_file_loaded"),
  79. .C_LOAD_INIT_FILE(0),
  80. .C_MEM_TYPE(1),
  81. .C_MUX_PIPELINE_STAGES(0),
  82. .C_PRIM_TYPE(1),
  83. .C_READ_DEPTH_A(2048),
  84. .C_READ_DEPTH_B(512),
  85. .C_READ_WIDTH_A(8),
  86. .C_READ_WIDTH_B(32),
  87. .C_RSTRAM_A(0),
  88. .C_RSTRAM_B(0),
  89. .C_RST_PRIORITY_A("CE"),
  90. .C_RST_PRIORITY_B("CE"),
  91. .C_RST_TYPE("SYNC"),
  92. .C_SIM_COLLISION_CHECK("ALL"),
  93. .C_USE_BYTE_WEA(0),
  94. .C_USE_BYTE_WEB(0),
  95. .C_USE_DEFAULT_DATA(0),
  96. .C_USE_ECC(0),
  97. .C_USE_SOFTECC(0),
  98. .C_WEA_WIDTH(1),
  99. .C_WEB_WIDTH(1),
  100. .C_WRITE_DEPTH_A(2048),
  101. .C_WRITE_DEPTH_B(512),
  102. .C_WRITE_MODE_A("WRITE_FIRST"),
  103. .C_WRITE_MODE_B("WRITE_FIRST"),
  104. .C_WRITE_WIDTH_A(8),
  105. .C_WRITE_WIDTH_B(32),
  106. .C_XDEVICEFAMILY("spartan3"))
  107. inst (
  108. .CLKA(clka),
  109. .WEA(wea),
  110. .ADDRA(addra),
  111. .DINA(dina),
  112. .CLKB(clkb),
  113. .ADDRB(addrb),
  114. .DOUTB(doutb),
  115. .RSTA(),
  116. .ENA(),
  117. .REGCEA(),
  118. .DOUTA(),
  119. .RSTB(),
  120. .ENB(),
  121. .REGCEB(),
  122. .WEB(),
  123. .DINB(),
  124. .INJECTSBITERR(),
  125. .INJECTDBITERR(),
  126. .SBITERR(),
  127. .DBITERR(),
  128. .RDADDRECC());
  129. // synthesis translate_on
  130. // XST black box declaration
  131. // box_type "black_box"
  132. // synthesis attribute box_type of dac_buf is "black_box"
  133. endmodule