dac_test.v 3.9 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 19:26:11 07/23/2010
  7. // Design Name:
  8. // Module Name: dac_test
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module dac_test(
  22. input clkin,
  23. input sysclk,
  24. input we,
  25. input[10:0] pgm_address,
  26. input[7:0] pgm_data,
  27. input[7:0] volume,
  28. input vol_latch,
  29. input play,
  30. input reset,
  31. output sdout,
  32. output lrck,
  33. output mclk,
  34. output DAC_STATUS
  35. );
  36. reg[8:0] dac_address_r;
  37. wire[8:0] dac_address = dac_address_r;
  38. reg dac_nextaddr_r;
  39. wire[31:0] dac_data;
  40. assign DAC_STATUS = dac_address_r[8];
  41. reg[7:0] vol_reg;
  42. reg[7:0] vol_target_reg;
  43. reg[1:0] vol_latch_reg;
  44. reg vol_valid;
  45. reg[2:0] sysclk_sreg;
  46. wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
  47. reg [25:0] interpol_count;
  48. reg interpol_overflow;
  49. always @(posedge clkin) begin
  50. sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
  51. end
  52. dac_buf snes_dac_buf (
  53. .clka(clkin),
  54. .wea(~we), // Bus [0 : 0]
  55. .addra(pgm_address), // Bus [10 : 0]
  56. .dina(pgm_data), // Bus [7 : 0]
  57. .clkb(clkin),
  58. .addrb(dac_address), // Bus [8 : 0]
  59. .doutb(dac_data)); // Bus [31 : 0]
  60. reg [15:0] cnt;
  61. reg [15:0] smpcnt;
  62. reg [15:0] samples;
  63. wire [15:0] sample = {smpcnt[10] ? ~smpcnt[9:0] : smpcnt[9:0], 6'b0};
  64. wire [15:0] sample2 = {smpcnt[9] ? ~smpcnt[8:0] : smpcnt[8:0], 7'b0};
  65. reg [15:0] smpshift;
  66. reg [15:0] smpdata;
  67. assign mclk = cnt[2]; // mclk = clk/8
  68. //assign lrck = cnt[10]; // lrck = mclk/512
  69. //wire sclk = cnt[5]; // sclk = lrck*32
  70. assign lrck = cnt[8]; // lrck = mclk/128
  71. wire sclk = cnt[3]; // sclk = lrck*32
  72. reg [2:0] lrck_sreg;
  73. reg [2:0] sclk_sreg;
  74. wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01);
  75. wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10);
  76. wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01);
  77. wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
  78. reg sdout_reg;
  79. assign sdout = sdout_reg;
  80. reg [1:0] reset_sreg;
  81. wire reset_rising = (reset_sreg[1:0] == 2'b01);
  82. reg play_r;
  83. initial begin
  84. cnt = 16'hff00;
  85. smpcnt = 16'b0;
  86. lrck_sreg = 2'b11;
  87. sclk_sreg = 1'b0;
  88. dac_address_r = 10'b0;
  89. vol_valid = 1'b0;
  90. vol_latch_reg = 1'b0;
  91. vol_reg = 8'h0;
  92. vol_target_reg = 8'hff;
  93. samples <= 16'h0;
  94. end
  95. always @(posedge clkin) begin
  96. if(reset_rising) begin
  97. dac_address_r <= 0;
  98. interpol_overflow <= 0;
  99. interpol_count <= 0;
  100. end else if(sysclk_rising) begin
  101. if(interpol_count > 59378938) begin
  102. interpol_count <= interpol_count + 122500 - 59501439;
  103. dac_address_r <= dac_address_r + play_r;
  104. interpol_overflow <= 1;
  105. end else begin
  106. interpol_count <= interpol_count + 122500;
  107. interpol_overflow <= 0;
  108. end
  109. end
  110. end
  111. always @(posedge clkin) begin
  112. cnt <= cnt + 1;
  113. lrck_sreg <= {lrck_sreg[1:0], lrck};
  114. sclk_sreg <= {sclk_sreg[1:0], sclk};
  115. vol_latch_reg <= {vol_latch_reg[0], vol_latch};
  116. play_r <= play;
  117. reset_sreg <= {reset_sreg[0], reset};
  118. end
  119. always @(posedge clkin) begin
  120. if (vol_latch_rising) begin
  121. vol_valid <= 1'b1;
  122. end
  123. else if(vol_valid) begin
  124. vol_target_reg <= volume;
  125. vol_valid <= 1'b0;
  126. end
  127. end
  128. // ramp volume only every 4 samples
  129. always @(posedge clkin) begin
  130. if (lrck_rising && &samples[1:0]) begin
  131. if(vol_reg > vol_target_reg)
  132. vol_reg <= vol_reg - 1;
  133. else if(vol_reg < vol_target_reg)
  134. vol_reg <= vol_reg + 1;
  135. end
  136. end
  137. always @(posedge clkin) begin
  138. if (lrck_rising) begin // right channel
  139. smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
  140. samples <= samples + 1;
  141. end else if (lrck_falling) begin // left channel
  142. smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
  143. end else begin
  144. if (sclk_rising) begin
  145. smpcnt <= smpcnt + 1;
  146. sdout_reg <= smpshift[15];
  147. smpshift <= {smpshift[14:0], 1'b0};
  148. end
  149. end
  150. end
  151. endmodule