avr_cmd.v 11 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 21:57:50 08/25/2009
  7. // Design Name:
  8. // Module Name: mcu_cmd
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module mcu_cmd(
  22. input clk,
  23. input cmd_ready,
  24. input param_ready,
  25. input [7:0] cmd_data,
  26. input [7:0] param_data,
  27. output [3:0] mcu_mapper,
  28. output [3:0] mcu_sram_size,
  29. output mcu_read,
  30. output mcu_write,
  31. output [7:0] mcu_data_out,
  32. input [7:0] mcu_data_in,
  33. output [7:0] spi_data_out,
  34. input [31:0] spi_byte_cnt,
  35. input [2:0] spi_bit_cnt,
  36. output [23:0] addr_out,
  37. output [3:0] mapper,
  38. input endmessage,
  39. input startmessage,
  40. output [23:0] saveram_mask_out,
  41. output [23:0] rom_mask_out,
  42. // SD "DMA" extension
  43. output SD_DMA_EN,
  44. input SD_DMA_STATUS,
  45. input SD_DMA_NEXTADDR,
  46. input [7:0] SD_DMA_SRAM_DATA,
  47. input SD_DMA_SRAM_WE,
  48. output [1:0] SD_DMA_TGT,
  49. output SD_DMA_PARTIAL,
  50. output [11:0] SD_DMA_PARTIAL_START,
  51. output [11:0] SD_DMA_PARTIAL_END,
  52. // DAC
  53. output [10:0] dac_addr_out,
  54. // output [7:0] dac_volume_out,
  55. // output dac_volume_latch_out,
  56. input DAC_STATUS,
  57. output dac_play_out,
  58. output dac_reset_out,
  59. // MSU data
  60. output [13:0] msu_addr_out,
  61. input [6:0] MSU_STATUS,
  62. output [5:0] msu_status_reset_out,
  63. output [5:0] msu_status_set_out,
  64. output msu_status_reset_we,
  65. input [31:0] msu_addressrq,
  66. input [15:0] msu_trackrq,
  67. input [7:0] msu_volumerq,
  68. output [13:0] msu_ptr_out,
  69. output msu_reset_out,
  70. // BS-X
  71. output [7:0] bsx_regs_reset_out,
  72. output [7:0] bsx_regs_set_out,
  73. output bsx_regs_reset_we,
  74. // SNES sync/clk
  75. input snes_sysclk
  76. );
  77. wire [31:0] snes_sysclk_freq;
  78. clk_test snes_clk_test (
  79. .clk(clk),
  80. .sysclk(snes_sysclk),
  81. .snes_sysclk_freq(snes_sysclk_freq)
  82. );
  83. reg [3:0] MAPPER_BUF;
  84. reg [3:0] SRAM_SIZE_BUF;
  85. reg MCU_READ_BUF;
  86. reg MCU_WRITE_BUF;
  87. reg [23:0] ADDR_OUT_BUF;
  88. reg [10:0] DAC_ADDR_OUT_BUF;
  89. reg [7:0] DAC_VOL_OUT_BUF;
  90. reg DAC_VOL_LATCH_BUF;
  91. reg DAC_PLAY_OUT_BUF;
  92. reg DAC_RESET_OUT_BUF;
  93. reg [13:0] MSU_ADDR_OUT_BUF;
  94. reg [13:0] MSU_PTR_OUT_BUF;
  95. reg [5:0] msu_status_set_out_buf;
  96. reg [5:0] msu_status_reset_out_buf;
  97. reg msu_status_reset_we_buf;
  98. reg MSU_RESET_OUT_BUF;
  99. reg [7:0] bsx_regs_set_out_buf;
  100. reg [7:0] bsx_regs_reset_out_buf;
  101. reg bsx_regs_reset_we_buf;
  102. reg [31:0] SNES_SYSCLK_FREQ_BUF;
  103. reg [7:0] MCU_DATA_OUT_BUF;
  104. reg [7:0] MCU_DATA_IN_BUF;
  105. reg [1:0] mcu_nextaddr_buf;
  106. reg SD_DMA_NEXTADDRr;
  107. always @(posedge clk) SD_DMA_NEXTADDRr <= SD_DMA_NEXTADDR;
  108. wire mcu_nextaddr;
  109. reg DAC_STATUSr;
  110. reg SD_DMA_STATUSr;
  111. reg [6:0] MSU_STATUSr;
  112. always @(posedge clk) begin
  113. DAC_STATUSr <= DAC_STATUS;
  114. SD_DMA_STATUSr <= SD_DMA_STATUS;
  115. MSU_STATUSr <= MSU_STATUS;
  116. end
  117. reg SD_DMA_PARTIALr;
  118. assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
  119. reg SD_DMA_ENr;
  120. assign SD_DMA_EN = SD_DMA_ENr;
  121. reg [1:0] SD_DMA_TGTr;
  122. assign SD_DMA_TGT = SD_DMA_TGTr;
  123. reg [11:0] SD_DMA_PARTIAL_STARTr;
  124. reg [11:0] SD_DMA_PARTIAL_ENDr;
  125. assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
  126. assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
  127. reg [2:0] spi_dma_nextaddr_r;
  128. reg [1:0] SRAM_MASK_IDX;
  129. reg [23:0] SAVERAM_MASK;
  130. reg [23:0] ROM_MASK;
  131. assign spi_data_out = MCU_DATA_IN_BUF;
  132. initial begin
  133. ADDR_OUT_BUF = 0;
  134. DAC_ADDR_OUT_BUF = 0;
  135. MSU_ADDR_OUT_BUF = 0;
  136. DAC_VOL_OUT_BUF = 0;
  137. DAC_VOL_LATCH_BUF = 0;
  138. spi_dma_nextaddr_r = 0;
  139. SD_DMA_ENr = 0;
  140. end
  141. // command interpretation
  142. always @(posedge clk) begin
  143. if (cmd_ready) begin
  144. case (cmd_data[7:4])
  145. 4'h3: // select mapper
  146. MAPPER_BUF <= cmd_data[3:0];
  147. 4'h4: begin// SD DMA
  148. SD_DMA_ENr <= 1;
  149. SD_DMA_TGTr <= cmd_data[1:0];
  150. SD_DMA_PARTIALr <= cmd_data[2];
  151. end
  152. 4'h8: SD_DMA_TGTr <= 2'b00;
  153. 4'h9: SD_DMA_TGTr <= cmd_data[1:0];
  154. // 4'hE:
  155. // select memory unit
  156. endcase
  157. end else if (param_ready) begin
  158. casex (cmd_data[7:0])
  159. 8'h0x:
  160. case (cmd_data[1:0])
  161. 2'b01: begin
  162. case (spi_byte_cnt)
  163. 32'h2: begin
  164. DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
  165. DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
  166. end
  167. 32'h3:
  168. DAC_ADDR_OUT_BUF[7:0] <= param_data;
  169. endcase
  170. end
  171. 2'b10: begin
  172. case (spi_byte_cnt)
  173. 32'h2: begin
  174. MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
  175. MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
  176. end
  177. 32'h3:
  178. MSU_ADDR_OUT_BUF[7:0] <= param_data;
  179. endcase
  180. end
  181. default:
  182. case (spi_byte_cnt)
  183. 32'h2: begin
  184. ADDR_OUT_BUF[23:16] <= param_data;
  185. ADDR_OUT_BUF[15:0] <= 16'b0;
  186. end
  187. 32'h3:
  188. ADDR_OUT_BUF[15:8] <= param_data;
  189. 32'h4:
  190. ADDR_OUT_BUF[7:0] <= param_data;
  191. endcase
  192. endcase
  193. 8'h1x:
  194. case (spi_byte_cnt)
  195. 32'h2:
  196. ROM_MASK[23:16] <= param_data;
  197. 32'h3:
  198. ROM_MASK[15:8] <= param_data;
  199. 32'h4:
  200. ROM_MASK[7:0] <= param_data;
  201. endcase
  202. 8'h2x:
  203. case (spi_byte_cnt)
  204. 32'h2:
  205. SAVERAM_MASK[23:16] <= param_data;
  206. 32'h3:
  207. SAVERAM_MASK[15:8] <= param_data;
  208. 32'h4:
  209. SAVERAM_MASK[7:0] <= param_data;
  210. endcase
  211. 8'h4x:
  212. SD_DMA_ENr <= 1'b0;
  213. // 8'h5x:
  214. // case (spi_byte_cnt)
  215. // 32'h2:
  216. // DAC_VOL_OUT_BUF <= param_data;
  217. // 32'h3:
  218. // DAC_VOL_LATCH_BUF <= 1'b1;
  219. // 32'h4:
  220. // DAC_VOL_LATCH_BUF <= 1'b0;
  221. // endcase
  222. 8'h6x:
  223. case (spi_byte_cnt)
  224. 32'h2:
  225. SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
  226. 32'h3:
  227. SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
  228. 32'h4:
  229. SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
  230. 32'h5:
  231. SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
  232. endcase
  233. 8'h9x:
  234. MCU_DATA_OUT_BUF <= param_data;
  235. 8'he0:
  236. case (spi_byte_cnt)
  237. 32'h2: begin
  238. msu_status_set_out_buf <= param_data[5:0];
  239. end
  240. 32'h3: begin
  241. msu_status_reset_out_buf <= param_data[5:0];
  242. msu_status_reset_we_buf <= 1'b1;
  243. end
  244. 32'h4:
  245. msu_status_reset_we_buf <= 1'b0;
  246. endcase
  247. 8'he1: // pause DAC
  248. DAC_PLAY_OUT_BUF <= 1'b0;
  249. 8'he2: // resume DAC
  250. DAC_PLAY_OUT_BUF <= 1'b1;
  251. 8'he3: // reset DAC (set DAC playback address = 0)
  252. case (spi_byte_cnt)
  253. 32'h2:
  254. DAC_RESET_OUT_BUF <= 1'b1;
  255. 32'h3:
  256. DAC_RESET_OUT_BUF <= 1'b0;
  257. endcase
  258. 8'he4: // reset MSU read buffer pointer
  259. case (spi_byte_cnt)
  260. 32'h2: begin
  261. MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
  262. MSU_PTR_OUT_BUF[7:0] <= 8'h0;
  263. end
  264. 32'h3: begin
  265. MSU_PTR_OUT_BUF[7:0] <= param_data;
  266. MSU_RESET_OUT_BUF <= 1'b1;
  267. end
  268. 32'h4:
  269. MSU_RESET_OUT_BUF <= 1'b0;
  270. endcase
  271. 8'he6:
  272. case (spi_byte_cnt)
  273. 32'h2: begin
  274. bsx_regs_set_out_buf <= param_data[7:0];
  275. end
  276. 32'h3: begin
  277. bsx_regs_reset_out_buf <= param_data[7:0];
  278. bsx_regs_reset_we_buf <= 1'b1;
  279. end
  280. 32'h4:
  281. bsx_regs_reset_we_buf <= 1'b0;
  282. endcase
  283. endcase
  284. end
  285. if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[3]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) begin
  286. case (SD_DMA_TGTr)
  287. 2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
  288. 2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
  289. 2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
  290. endcase
  291. end
  292. end
  293. // value fetch during last SPI bit
  294. always @(posedge clk) begin
  295. if (spi_bit_cnt == 3'h7)
  296. if (cmd_data[7:0] == 8'hF0)
  297. MCU_DATA_IN_BUF <= 8'hA5;
  298. else if (cmd_data[7:0] == 8'hF1)
  299. case (spi_byte_cnt[0])
  300. 1'b1: // buffer status (1st byte)
  301. MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[6], 5'b0};
  302. 1'b0: // control status (2nd byte)
  303. MCU_DATA_IN_BUF <= {2'b0, MSU_STATUSr[5:0]};
  304. endcase
  305. else if (cmd_data[7:0] == 8'hF2)
  306. case (spi_byte_cnt)
  307. 32'h1:
  308. MCU_DATA_IN_BUF <= msu_addressrq[31:24];
  309. 32'h2:
  310. MCU_DATA_IN_BUF <= msu_addressrq[23:16];
  311. 32'h3:
  312. MCU_DATA_IN_BUF <= msu_addressrq[15:8];
  313. 32'h4:
  314. MCU_DATA_IN_BUF <= msu_addressrq[7:0];
  315. endcase
  316. else if (cmd_data[7:0] == 8'hF3)
  317. case (spi_byte_cnt)
  318. 32'h1:
  319. MCU_DATA_IN_BUF <= msu_trackrq[15:8];
  320. 32'h2:
  321. MCU_DATA_IN_BUF <= msu_trackrq[7:0];
  322. endcase
  323. else if (cmd_data[7:0] == 8'hF4)
  324. MCU_DATA_IN_BUF <= msu_volumerq;
  325. else if (cmd_data[7:0] == 8'hFE)
  326. case (spi_byte_cnt)
  327. 32'h1:
  328. SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
  329. 32'h2:
  330. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  331. 32'h3:
  332. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  333. 32'h4:
  334. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  335. 32'h5:
  336. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  337. endcase
  338. else if (cmd_data[7:0] == 8'hFF)
  339. MCU_DATA_IN_BUF <= param_data;
  340. else if (cmd_data[7:4] == 4'h8)
  341. MCU_DATA_IN_BUF <= mcu_data_in;
  342. else
  343. MCU_DATA_IN_BUF <= cmd_data;
  344. end
  345. // nextaddr pulse generation
  346. always @(posedge clk) begin
  347. if (spi_bit_cnt == 3'h0)
  348. mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b1};
  349. else
  350. mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b0};
  351. end
  352. // r/w pulse
  353. always @(posedge clk) begin
  354. if ((spi_bit_cnt == 3'h1 || spi_bit_cnt == 3'h2 || spi_bit_cnt == 3'h3) & (cmd_data[7:4] == 4'h9) & (spi_byte_cnt > 32'h1))
  355. MCU_WRITE_BUF <= 1'b0;
  356. else
  357. MCU_WRITE_BUF <= 1'b1;
  358. // Read pulse is two spi cycles to ensure that the value
  359. // is ready in the 2nd cycle in MCU master mode
  360. if ((spi_bit_cnt == 3'h5 || spi_bit_cnt == 3'h6 || spi_bit_cnt == 3'h7) & (cmd_data[7:4] == 4'h8) & (spi_byte_cnt > 32'h0))
  361. MCU_READ_BUF <= 1'b0;
  362. else
  363. MCU_READ_BUF <= 1'b1;
  364. end
  365. // trigger for nextaddr
  366. assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
  367. assign mcu_read = MCU_READ_BUF;
  368. assign mcu_write = SD_DMA_STATUS ? (SD_DMA_TGTr == 2'b00 ? SD_DMA_SRAM_WE : 1'b1) : MCU_WRITE_BUF;
  369. assign addr_out = ADDR_OUT_BUF;
  370. assign dac_addr_out = DAC_ADDR_OUT_BUF;
  371. assign msu_addr_out = MSU_ADDR_OUT_BUF;
  372. assign dac_volume_out = DAC_VOL_OUT_BUF;
  373. assign dac_volume_latch_out = DAC_VOL_LATCH_BUF;
  374. assign dac_play_out = DAC_PLAY_OUT_BUF;
  375. assign dac_reset_out = DAC_RESET_OUT_BUF;
  376. assign msu_status_reset_we = msu_status_reset_we_buf;
  377. assign msu_status_reset_out = msu_status_reset_out_buf;
  378. assign msu_status_set_out = msu_status_set_out_buf;
  379. assign msu_reset_out = MSU_RESET_OUT_BUF;
  380. assign msu_ptr_out = MSU_PTR_OUT_BUF;
  381. assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
  382. assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
  383. assign bsx_regs_set_out = bsx_regs_set_out_buf;
  384. assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
  385. assign mcu_mapper = MAPPER_BUF;
  386. assign mcu_sram_size = SRAM_SIZE_BUF;
  387. assign rom_mask_out = ROM_MASK;
  388. assign saveram_mask_out = SAVERAM_MASK;
  389. endmodule