spi.c 5.5 KB

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  1. /* Sd2iec - SD/MMC to Commodore serial bus interface/controller
  2. Copyright (C) 2007-2010 Ingo Korb <ingo@akana.de>
  3. Inspiration and low-level SD/MMC access based on code from MMC2IEC
  4. by Lars Pontoppidan et al., see sdcard.c|h and config.h.
  5. FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; version 2 of the License only.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. spi.c: Low-level SPI routines
  17. */
  18. #include <arm/NXP/LPC17xx/LPC17xx.h>
  19. #include <arm/bits.h>
  20. #include "config.h"
  21. #include "spi.h"
  22. #define SSP_TFE 0 // Transmit FIFO empty
  23. #define SSP_TNF 1 // Transmit FIFO not full
  24. #define SSP_RNE 2 // Receive FIFO not empty
  25. #define SSP_RFF 3 // Receive FIFO full
  26. #define SSP_BSY 4 // Busy
  27. // FIXME: Move to config.h!
  28. #define SSP_CLK_DIVISOR_FAST 4
  29. #define SSP_CLK_DIVISOR_SLOW 250
  30. #define SSP_REGS LPC_SSP1
  31. #define SSP_PCLKREG PCLKSEL0
  32. /* SSP0: PCLKSEL1
  33. SSP1: PCLKSEL0 */
  34. #define SSP_PCLKBIT 20
  35. /* SSP0: 10
  36. SSP1: 20 */
  37. #define SSP_DMAID_TX 2
  38. /* SSP0: 0
  39. SSP1: 2 */
  40. #define SSP_DMAID_RX 3
  41. /* SSP0: 1
  42. SSP1: 3 */
  43. void spi_init(spi_speed_t speed) {
  44. /* Set clock prescaler to 1:1 */
  45. BITBAND(LPC_SC->SSP_PCLKREG, SSP_PCLKBIT) = 1;
  46. /* configure data format - 8 bits, SPI, CPOL=0, CPHA=0, 1 clock per bit */
  47. SSP_REGS->CR0 = (8-1);
  48. /* set clock prescaler */
  49. if (speed == SPI_SPEED_FAST) {
  50. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
  51. } else {
  52. SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
  53. }
  54. /* Enable SSP */
  55. SSP_REGS->CR1 = BV(1);
  56. /* Enable DMA controller, little-endian mode */
  57. BITBAND(LPC_SC->PCONP, 29) = 1;
  58. LPC_GPDMA->DMACConfig = 1;
  59. }
  60. void spi_tx_byte(uint8_t data) {
  61. /* Wait until TX fifo can accept data */
  62. while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ;
  63. /* Send byte */
  64. SSP_REGS->DR = data;
  65. }
  66. uint8_t spi_rx_byte(void) {
  67. /* Wait until SSP is not busy */
  68. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  69. /* Clear RX fifo */
  70. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  71. (void) SSP_REGS->DR;
  72. /* Transmit a single dummy byte */
  73. SSP_REGS->DR = 0xff;
  74. /* Wait until answer has been received */
  75. while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  76. return SSP_REGS->DR;
  77. }
  78. void spi_tx_block(const void *ptr, unsigned int length) {
  79. const uint8_t *data = (const uint8_t *)ptr;
  80. while (length--) {
  81. /* Wait until TX fifo can accept data */
  82. while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ;
  83. SSP_REGS->DR = *data++;
  84. }
  85. }
  86. void spi_rx_block(void *ptr, unsigned int length) {
  87. uint8_t *data = (uint8_t *)ptr;
  88. unsigned int txlen = length;
  89. /* Wait until SSP is not busy */
  90. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  91. /* Clear RX fifo */
  92. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  93. (void) SSP_REGS->DR;
  94. if ((length & 3) != 0 || ((uint32_t)ptr & 3) != 0) {
  95. /* Odd length or unaligned buffer */
  96. while (length > 0) {
  97. /* Wait until TX or RX FIFO are ready */
  98. while (txlen > 0 && !BITBAND(SSP_REGS->SR, SSP_TNF) &&
  99. !BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  100. /* Try to receive data */
  101. while (length > 0 && BITBAND(SSP_REGS->SR, SSP_RNE)) {
  102. *data++ = SSP_REGS->DR;
  103. length--;
  104. }
  105. /* Send dummy data until TX full or RX ready */
  106. while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF) && !BITBAND(SSP_REGS->SR, SSP_RNE)) {
  107. txlen--;
  108. SSP_REGS->DR = 0xff;
  109. }
  110. }
  111. } else {
  112. /* Clear interrupt flags of DMA channels 0 */
  113. LPC_GPDMA->DMACIntTCClear = BV(0);
  114. LPC_GPDMA->DMACIntErrClr = BV(0);
  115. /* Set up RX DMA channel */
  116. LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&SSP_REGS->DR;
  117. LPC_GPDMACH0->DMACCDestAddr = (uint32_t)ptr;
  118. LPC_GPDMACH0->DMACCLLI = 0; // no linked list
  119. LPC_GPDMACH0->DMACCControl = length
  120. | (0 << 12) // source burst size 1 (FIXME: Check if larger possible/useful)
  121. | (0 << 15) // destination burst size 1
  122. | (0 << 18) // source transfer width 1 byte
  123. | (2 << 21) // destination transfer width 4 bytes
  124. | (0 << 26) // source address not incremented
  125. | (1 << 27) // destination address incremented
  126. ;
  127. LPC_GPDMACH0->DMACCConfig = 1 // enable channel
  128. | (SSP_DMAID_RX << 1) // data source SSP RX
  129. | (2 << 11) // transfer from peripheral to memory
  130. ;
  131. /* Enable RX FIFO DMA */
  132. SSP_REGS->DMACR = 1;
  133. /* Write <length> bytes into TX FIFO */
  134. // FIXME: Any value in doing this using DMA too?
  135. while (txlen > 0) {
  136. while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF)) {
  137. txlen--;
  138. SSP_REGS->DR = 0xff;
  139. }
  140. }
  141. /* Wait until DMA channel disables itself */
  142. while (LPC_GPDMACH0->DMACCConfig & 1) ;
  143. /* Disable RX FIFO DMA */
  144. SSP_REGS->DMACR = 0;
  145. }
  146. }
  147. void spi_set_speed(spi_speed_t speed) {
  148. /* Wait until TX fifo is empty */
  149. while (!BITBAND(SSP_REGS->SR, 0)) ;
  150. /* Disable SSP (FIXME: Is this required?) */
  151. SSP_REGS->CR1 = 0;
  152. /* Change clock divisor */
  153. if (speed == SPI_SPEED_FAST) {
  154. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
  155. } else {
  156. SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
  157. }
  158. /* Enable SSP */
  159. SSP_REGS->CR1 = BV(1);
  160. }