mcu_cmd.v 3.8 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 21:57:50 08/25/2009
  7. // Design Name:
  8. // Module Name: mcu_cmd
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module mcu_cmd(
  22. input clk,
  23. input cmd_ready,
  24. input param_ready,
  25. input [7:0] cmd_data,
  26. input [7:0] param_data,
  27. output mcu_rrq,
  28. output mcu_wrq,
  29. input mcu_rq_rdy,
  30. output [7:0] mcu_data_out,
  31. input [7:0] mcu_data_in,
  32. output [7:0] spi_data_out,
  33. input [31:0] spi_byte_cnt,
  34. input [2:0] spi_bit_cnt,
  35. output [23:0] addr_out,
  36. output [23:0] saveram_mask_out,
  37. output [23:0] rom_mask_out
  38. );
  39. reg [7:0] MCU_DATA_OUT_BUF;
  40. reg [7:0] MCU_DATA_IN_BUF;
  41. reg [2:0] mcu_nextaddr_buf;
  42. wire mcu_nextaddr;
  43. reg [23:0] SAVERAM_MASK;
  44. reg [23:0] ROM_MASK;
  45. reg [23:0] ADDR_OUT_BUF;
  46. assign spi_data_out = MCU_DATA_IN_BUF;
  47. initial begin
  48. ADDR_OUT_BUF = 0;
  49. end
  50. // command interpretation
  51. always @(posedge clk) begin
  52. if (param_ready) begin
  53. casex (cmd_data[7:0])
  54. 8'h1x:
  55. case (spi_byte_cnt)
  56. 32'h2:
  57. ROM_MASK[23:16] <= param_data;
  58. 32'h3:
  59. ROM_MASK[15:8] <= param_data;
  60. 32'h4:
  61. ROM_MASK[7:0] <= param_data;
  62. endcase
  63. 8'h2x:
  64. case (spi_byte_cnt)
  65. 32'h2:
  66. SAVERAM_MASK[23:16] <= param_data;
  67. 32'h3:
  68. SAVERAM_MASK[15:8] <= param_data;
  69. 32'h4:
  70. SAVERAM_MASK[7:0] <= param_data;
  71. endcase
  72. 8'h9x:
  73. MCU_DATA_OUT_BUF <= param_data;
  74. endcase
  75. end
  76. end
  77. always @(posedge clk) begin
  78. if(param_ready && cmd_data[7:4] == 4'h0) begin
  79. case (spi_byte_cnt)
  80. 32'h2: begin
  81. ADDR_OUT_BUF[23:16] <= param_data;
  82. ADDR_OUT_BUF[15:0] <= 16'b0;
  83. end
  84. 32'h3:
  85. ADDR_OUT_BUF[15:8] <= param_data;
  86. 32'h4:
  87. ADDR_OUT_BUF[7:0] <= param_data;
  88. endcase
  89. end else if ((mcu_nextaddr & (cmd_data[7:5] == 3'h4)
  90. && (cmd_data[3])
  91. && (spi_byte_cnt >= (32'h1+cmd_data[4])))
  92. )
  93. begin
  94. ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
  95. end
  96. end
  97. // value fetch during last SPI bit
  98. always @(posedge clk) begin
  99. if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
  100. MCU_DATA_IN_BUF <= mcu_data_in;
  101. else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
  102. if (cmd_data[7:0] == 8'hF0)
  103. MCU_DATA_IN_BUF <= 8'hA5;
  104. else if (cmd_data[7:0] == 8'hFF)
  105. MCU_DATA_IN_BUF <= param_data;
  106. end
  107. end
  108. // nextaddr pulse generation
  109. always @(posedge clk) begin
  110. mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
  111. end
  112. parameter ST_RQ = 2'b01;
  113. parameter ST_IDLE = 2'b10;
  114. reg [1:0] rrq_state;
  115. initial rrq_state = ST_IDLE;
  116. reg mcu_rrq_r;
  117. reg [1:0] wrq_state;
  118. initial wrq_state = ST_IDLE;
  119. reg mcu_wrq_r;
  120. always @(posedge clk) begin
  121. case(rrq_state)
  122. ST_IDLE: begin
  123. if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
  124. mcu_rrq_r <= 1'b1;
  125. rrq_state <= ST_RQ;
  126. end else
  127. rrq_state <= ST_IDLE;
  128. end
  129. ST_RQ: begin
  130. mcu_rrq_r <= 1'b0;
  131. rrq_state <= ST_IDLE;
  132. end
  133. endcase
  134. end
  135. always @(posedge clk) begin
  136. case(wrq_state)
  137. ST_IDLE: begin
  138. if(param_ready && cmd_data[7:4] == 4'h9) begin
  139. mcu_wrq_r <= 1'b1;
  140. wrq_state <= ST_RQ;
  141. end else
  142. wrq_state <= ST_IDLE;
  143. end
  144. ST_RQ: begin
  145. mcu_wrq_r <= 1'b0;
  146. wrq_state <= ST_IDLE;
  147. end
  148. endcase
  149. end
  150. // trigger for nextaddr
  151. assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
  152. assign mcu_rrq = mcu_rrq_r;
  153. assign mcu_wrq = mcu_wrq_r;
  154. assign addr_out = ADDR_OUT_BUF;
  155. assign mcu_data_out = MCU_DATA_OUT_BUF;
  156. assign rom_mask_out = ROM_MASK;
  157. assign saveram_mask_out = SAVERAM_MASK;
  158. assign DBG_mcu_nextaddr = mcu_nextaddr;
  159. endmodule