address.v 10 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: address
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Address logic w/ SaveRAM masking
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Additional Comments:
  18. //
  19. //////////////////////////////////////////////////////////////////////////////////
  20. module address(
  21. input CLK,
  22. input [7:0] featurebits, // peripheral enable/disable
  23. input [2:0] MAPPER, // MCU detected mapper
  24. input [23:0] SNES_ADDR, // requested address from SNES
  25. input [7:0] SNES_PA, // peripheral address from SNES
  26. output [23:0] ROM_ADDR, // Address to request from SRAM0
  27. output ROM_SEL, // enable SRAM0 (active low)
  28. output IS_SAVERAM, // address/CS mapped as SRAM?
  29. output IS_ROM, // address mapped as ROM?
  30. output IS_WRITABLE, // address somehow mapped as writable area?
  31. input [23:0] SAVERAM_MASK,
  32. input [23:0] ROM_MASK,
  33. output msu_enable,
  34. output srtc_enable,
  35. output use_bsx,
  36. output bsx_tristate,
  37. input [14:0] bsx_regs,
  38. output dspx_enable,
  39. output dspx_dp_enable,
  40. output dspx_a0,
  41. output r213f_enable,
  42. output snescmd_rd_enable,
  43. output snescmd_wr_enable,
  44. input [8:0] bs_page_offset,
  45. input [9:0] bs_page,
  46. input bs_page_enable
  47. );
  48. parameter [2:0]
  49. FEAT_DSPX = 0,
  50. FEAT_ST0010 = 1,
  51. FEAT_SRTC = 2,
  52. FEAT_MSU1 = 3,
  53. FEAT_213F = 4
  54. ;
  55. wire [23:0] SRAM_SNES_ADDR;
  56. /* currently supported mappers:
  57. Index Mapper
  58. 000 HiROM
  59. 001 LoROM
  60. 010 ExHiROM (48-64Mbit)
  61. 011 BS-X
  62. 110 brainfuck interleaved 96MBit Star Ocean =)
  63. 111 menu (ROM in upper SRAM)
  64. */
  65. /* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
  66. Offset 6000-7fff */
  67. assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
  68. |(SNES_ADDR[22]));
  69. assign IS_SAVERAM = SAVERAM_MASK[0]
  70. &(featurebits[FEAT_ST0010]
  71. ?((SNES_ADDR[22:19] == 4'b1101)
  72. & &(~SNES_ADDR[15:12])
  73. & SNES_ADDR[11])
  74. :((MAPPER == 3'b000
  75. || MAPPER == 3'b010
  76. || MAPPER == 3'b110
  77. || MAPPER == 3'b111)
  78. ? (!SNES_ADDR[22]
  79. & SNES_ADDR[21]
  80. & &SNES_ADDR[14:13]
  81. & !SNES_ADDR[15]
  82. )
  83. /* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd
  84. * Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff */
  85. :(MAPPER == 3'b001)
  86. ? (&SNES_ADDR[22:20]
  87. & (SNES_ADDR[19:16] < 4'b1110)
  88. & (~SNES_ADDR[15] | ~ROM_MASK[21])
  89. )
  90. /* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
  91. :(MAPPER == 3'b011)
  92. ? ((SNES_ADDR[23:19] == 5'b00010)
  93. & (SNES_ADDR[15:12] == 4'b0101)
  94. )
  95. : 1'b0));
  96. /* BS-X has 4 MBits of extra RAM that can be mapped to various places */
  97. wire [2:0] BSX_PSRAM_BANK = {bsx_regs[2], bsx_regs[6], bsx_regs[5]};
  98. wire [23:0] BSX_CHKADDR = bsx_regs[2] ? SNES_ADDR : {SNES_ADDR[23], 1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]};
  99. wire BSX_PSRAM_LOHI = (bsx_regs[3] & ~SNES_ADDR[23]) | (bsx_regs[4] & SNES_ADDR[23]);
  100. wire BSX_IS_PSRAM = BSX_PSRAM_LOHI
  101. & (( (BSX_CHKADDR[22:20] == BSX_PSRAM_BANK)
  102. &(SNES_ADDR[15] | bsx_regs[2])
  103. &(~(SNES_ADDR[19] & bsx_regs[2])))
  104. | (bsx_regs[2]
  105. ? (SNES_ADDR[22:21] == 2'b01 & SNES_ADDR[15:13] == 3'b011)
  106. : (&SNES_ADDR[22:20] & ~SNES_ADDR[15]))
  107. );
  108. wire BSX_IS_CARTROM = ((bsx_regs[7] & (SNES_ADDR[23:22] == 2'b00))
  109. |(bsx_regs[8] & (SNES_ADDR[23:22] == 2'b10)))
  110. & SNES_ADDR[15];
  111. wire BSX_HOLE_LOHI = (bsx_regs[9] & ~SNES_ADDR[23]) | (bsx_regs[10] & SNES_ADDR[23]);
  112. wire BSX_IS_HOLE = BSX_HOLE_LOHI
  113. & (bsx_regs[2] ? (SNES_ADDR[21:20] == {bsx_regs[11], 1'b0})
  114. : (SNES_ADDR[22:21] == {bsx_regs[11], 1'b0}));
  115. assign bsx_tristate = (MAPPER == 3'b011) & ~BSX_IS_CARTROM & ~BSX_IS_PSRAM & BSX_IS_HOLE;
  116. assign IS_WRITABLE = IS_SAVERAM
  117. |((MAPPER == 3'b011)
  118. ? BSX_IS_PSRAM
  119. : 1'b0);
  120. wire [23:0] BSX_ADDR = bsx_regs[2] ? {1'b0, SNES_ADDR[22:0]}
  121. : {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]};
  122. /* BSX regs:
  123. Index Function
  124. 1 0=map flash to ROM area; 1=map PRAM to ROM area
  125. 2 1=HiROM; 0=LoROM
  126. 3 1=Mirror PRAM @60-6f:0000-ffff
  127. 5 1=DO NOT mirror PRAM @40-4f:0000-ffff
  128. 6 1=DO NOT mirror PRAM @50-5f:0000-ffff
  129. 7 1=map BSX cartridge ROM @00-1f:8000-ffff
  130. 8 1=map BSX cartridge ROM @80-9f:8000-ffff
  131. */
  132. assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
  133. ?(IS_SAVERAM
  134. ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
  135. & SAVERAM_MASK)
  136. : ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
  137. :(MAPPER == 3'b001)
  138. ?(IS_SAVERAM
  139. ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]}
  140. & SAVERAM_MASK)
  141. : ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
  142. & ROM_MASK))
  143. :(MAPPER == 3'b010)
  144. ?(IS_SAVERAM
  145. ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
  146. & SAVERAM_MASK)
  147. : ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
  148. & ROM_MASK))
  149. :(MAPPER == 3'b011)
  150. ?( IS_SAVERAM
  151. ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
  152. : BSX_IS_CARTROM
  153. ? (24'h800000 + ({SNES_ADDR[22:16], SNES_ADDR[14:0]} & 24'h0fffff))
  154. : BSX_IS_PSRAM
  155. ? (24'h400000 + (BSX_ADDR & 24'h07FFFF))
  156. : bs_page_enable
  157. ? (24'h900000 + {bs_page,bs_page_offset})
  158. : (BSX_ADDR & 24'h0fffff)
  159. )
  160. :(MAPPER == 3'b110)
  161. ?(IS_SAVERAM
  162. ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
  163. & SAVERAM_MASK)
  164. :(SNES_ADDR[15]
  165. ?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
  166. :({2'b10,
  167. SNES_ADDR[23],
  168. SNES_ADDR[21:16],
  169. SNES_ADDR[14:0]}
  170. )
  171. )
  172. )
  173. :(MAPPER == 3'b111)
  174. ?(IS_SAVERAM
  175. ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
  176. & SAVERAM_MASK)
  177. : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
  178. + 24'hC00000)
  179. )
  180. : 24'b0);
  181. assign ROM_ADDR = SRAM_SNES_ADDR;
  182. assign ROM_SEL = 1'b0;
  183. assign msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
  184. //reg [5:0] msu_enable_r;
  185. //initial msu_enable_r = 6'b000000;
  186. //always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w};
  187. assign msu_enable = msu_enable_w /*&msu_enable_r[5:2]*/;
  188. assign use_bsx = (MAPPER == 3'b011);
  189. assign srtc_enable_w = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
  190. //reg [5:0] srtc_enable_r;
  191. //initial srtc_enable_r = 6'b000000;
  192. //always @(posedge CLK) srtc_enable_r <= {srtc_enable_r[4:0], srtc_enable_w};
  193. assign srtc_enable = srtc_enable_w /*&srtc_enable_r[3:0]*/ & featurebits[FEAT_SRTC];
  194. // DSP1 LoROM: DR=30-3f:8000-bfff; SR=30-3f:c000-ffff
  195. // or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
  196. // DSP1 HiROM: DR=00-0f:6000-6fff; SR=00-0f:7000-7fff
  197. wire dspx_enable_w =
  198. featurebits[FEAT_DSPX]
  199. ?((MAPPER == 3'b001)
  200. ?(ROM_MASK[20]
  201. ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
  202. :(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
  203. )
  204. :(MAPPER == 3'b000)
  205. ?(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15]
  206. & &SNES_ADDR[14:13])
  207. :1'b0)
  208. :featurebits[FEAT_ST0010]
  209. ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & &(~SNES_ADDR[19:16]) & ~SNES_ADDR[15])
  210. :1'b0;
  211. wire dspx_dp_enable_w = featurebits[FEAT_ST0010]
  212. &(SNES_ADDR[22:19] == 4'b1101
  213. && SNES_ADDR[15:11] == 5'b00000);
  214. assign dspx_a0 = featurebits[FEAT_DSPX]
  215. ?((MAPPER == 3'b001) ? SNES_ADDR[14]
  216. :(MAPPER == 3'b000) ? SNES_ADDR[12]
  217. :1'b1)
  218. :featurebits[FEAT_ST0010]
  219. ?SNES_ADDR[0]
  220. :1'b1;
  221. assign dspx_dp_enable = dspx_dp_enable_w;
  222. //reg [5:0] dspx_enable_r;
  223. //initial dspx_enable_r = 6'b000000;
  224. //always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[4:0], dspx_enable_w};
  225. assign dspx_enable = dspx_enable_w /*&dspx_enable_r[5:1]*/;
  226. wire r213f_enable_w = (SNES_PA == 8'h3f);
  227. //reg [5:0] r213f_enable_r;
  228. //initial r213f_enable_r = 6'b000000;
  229. //always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
  230. assign r213f_enable = r213f_enable_w /*&r213f_enable_r[5:2]*/ & featurebits[FEAT_213F];
  231. wire snescmd_rd_enable_w = (SNES_PA[7:4] == 4'b1111);
  232. //reg [5:0] snescmd_rd_enable_r;
  233. //initial snescmd_rd_enable_r = 6'b000000;
  234. //always @(posedge CLK) snescmd_rd_enable_r <= {snescmd_rd_enable_r[4:0], snescmd_rd_enable_w};
  235. assign snescmd_rd_enable = snescmd_rd_enable_w /*&snescmd_rd_enable_r[5:1]*/;
  236. assign snescmd_wr_enable_w = (SNES_ADDR[23:4] == 20'hccccc);
  237. //reg [5:0] snescmd_wr_enable_r;
  238. //initial snescmd_wr_enable_r = 6'b000000;
  239. //always @(posedge CLK) snescmd_wr_enable_r <= {snescmd_wr_enable_r[4:0], snescmd_wr_enable_w};
  240. assign snescmd_wr_enable = snescmd_wr_enable_w /*&snescmd_wr_enable_r[5:1]*/;
  241. endmodule