main.v 12 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR_IN,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. output SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. input SNES_SYSCLK,
  36. input [7:0] SNES_PA,
  37. input SNES_PARD,
  38. input SNES_PAWR,
  39. /* SRAM signals */
  40. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  41. inout [15:0] ROM_DATA,
  42. output [22:0] ROM_ADDR,
  43. output ROM_CE,
  44. output ROM_OE,
  45. output ROM_WE,
  46. output ROM_BHE,
  47. output ROM_BLE,
  48. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  49. inout [7:0] RAM_DATA,
  50. output [18:0] RAM_ADDR,
  51. output RAM_CE,
  52. output RAM_OE,
  53. output RAM_WE,
  54. /* MCU signals */
  55. input SPI_MOSI,
  56. inout SPI_MISO,
  57. input SPI_SS,
  58. inout SPI_SCK,
  59. input MCU_OVR,
  60. output MCU_RDY,
  61. output DAC_MCLK,
  62. output DAC_LRCK,
  63. output DAC_SDOUT,
  64. /* SD signals */
  65. input [3:0] SD_DAT,
  66. inout SD_CMD,
  67. inout SD_CLK,
  68. /* debug */
  69. output p113_out
  70. );
  71. assign DAC_MCLK = 0;
  72. assign DAC_LRCK = 0;
  73. assign DAC_SDOUT = 0;
  74. wire CLK2;
  75. reg [23:0] SNES_ADDR_r [2:0];
  76. always @(posedge CLK2) begin
  77. SNES_ADDR_r[2] <= SNES_ADDR_r[1];
  78. SNES_ADDR_r[1] <= SNES_ADDR_r[0];
  79. SNES_ADDR_r[0] <= SNES_ADDR_IN;
  80. end
  81. wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
  82. wire [7:0] spi_cmd_data;
  83. wire [7:0] spi_param_data;
  84. wire [7:0] spi_input_data;
  85. wire [31:0] spi_byte_cnt;
  86. wire [2:0] spi_bit_cnt;
  87. wire [23:0] MCU_ADDR;
  88. wire [23:0] SAVERAM_MASK;
  89. wire [23:0] ROM_MASK;
  90. wire [23:0] MAPPED_SNES_ADDR;
  91. spi snes_spi(
  92. .clk(CLK2),
  93. .MOSI(SPI_MOSI),
  94. .MISO(SPI_MISO),
  95. .SSEL(SPI_SS),
  96. .SCK(SPI_SCK),
  97. .cmd_ready(spi_cmd_ready),
  98. .param_ready(spi_param_ready),
  99. .cmd_data(spi_cmd_data),
  100. .param_data(spi_param_data),
  101. .input_data(spi_input_data),
  102. .byte_cnt(spi_byte_cnt),
  103. .bit_cnt(spi_bit_cnt)
  104. );
  105. reg [7:0] MCU_DINr;
  106. wire [7:0] MCU_DOUT;
  107. mcu_cmd snes_mcu_cmd(
  108. .clk(CLK2),
  109. .cmd_ready(spi_cmd_ready),
  110. .param_ready(spi_param_ready),
  111. .cmd_data(spi_cmd_data),
  112. .param_data(spi_param_data),
  113. .mcu_data_in(MCU_DINr),
  114. .mcu_data_out(MCU_DOUT),
  115. .spi_byte_cnt(spi_byte_cnt),
  116. .spi_bit_cnt(spi_bit_cnt),
  117. .spi_data_out(spi_input_data),
  118. .addr_out(MCU_ADDR),
  119. .saveram_mask_out(SAVERAM_MASK),
  120. .rom_mask_out(ROM_MASK),
  121. .mcu_rrq(MCU_RRQ),
  122. .mcu_wrq(MCU_WRQ),
  123. .mcu_rq_rdy(MCU_RDY)
  124. );
  125. wire [7:0] DCM_STATUS;
  126. // dcm1: dfs 4x
  127. my_dcm snes_dcm(
  128. .CLKIN(CLKIN),
  129. .CLKFX(CLK2),
  130. .LOCKED(DCM_LOCKED),
  131. .RST(DCM_RST),
  132. .STATUS(DCM_STATUS)
  133. );
  134. assign DCM_RST=0;
  135. reg [7:0] SNES_PARDr;
  136. reg [7:0] SNES_PAWRr;
  137. reg [7:0] SNES_READr;
  138. reg [7:0] SNES_WRITEr;
  139. reg [7:0] SNES_CPU_CLKr;
  140. wire SNES_FAKE_CLK = &SNES_CPU_CLKr[2:1];
  141. //wire SNES_FAKE_CLK = ~(SNES_READ & SNES_WRITE);
  142. reg SNES_DEADr;
  143. initial SNES_DEADr = 0;
  144. wire SNES_PARD_start = (SNES_PARDr[7:1] == 7'b1111110);
  145. wire SNES_PAWR_start = (SNES_PAWRr[7:1] == 7'b0000001);
  146. wire SNES_RD_start = (SNES_READr[7:1] == 7'b1111110);
  147. wire SNES_WR_start = (SNES_WRITEr[7:1] == 7'b1111110);
  148. wire SNES_WR_end = (SNES_WRITEr[7:1] == 7'b0000001);
  149. wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000001);
  150. wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b111110);
  151. always @(posedge CLK2) begin
  152. SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD};
  153. end
  154. always @(posedge CLK2) begin
  155. SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR};
  156. SNES_READr <= {SNES_READr[6:0], SNES_READ};
  157. SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE};
  158. SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK};
  159. end
  160. address snes_addr(
  161. .CLK(CLK2),
  162. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  163. .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
  164. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  165. .IS_SAVERAM(IS_SAVERAM),
  166. .IS_ROM(IS_ROM),
  167. .SAVERAM_MASK(SAVERAM_MASK),
  168. .ROM_MASK(ROM_MASK)
  169. );
  170. parameter MODE_SNES = 1'b0;
  171. parameter MODE_MCU = 1'b1;
  172. parameter ST_IDLE = 18'b000000000000000001;
  173. parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
  174. parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
  175. parameter ST_SNES_RD_END = 18'b000000000000001000;
  176. parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
  177. parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
  178. parameter ST_SNES_WR_DATA = 18'b000000000001000000;
  179. parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
  180. parameter ST_SNES_WR_END = 18'b000000000100000000;
  181. parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
  182. parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
  183. parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
  184. parameter ST_MCU_RD_END = 18'b000001000000000000;
  185. parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
  186. parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
  187. parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
  188. parameter ST_MCU_WR_END = 18'b010000000000000000;
  189. parameter ROM_RD_WAIT = 4'h0;
  190. parameter ROM_RD_WAIT_MCU = 4'h6;
  191. parameter ROM_WR_WAIT = 4'h4;
  192. parameter ROM_WR_WAIT1 = 4'h2;
  193. parameter ROM_WR_WAIT2 = 4'h1;
  194. parameter ROM_WR_WAIT_MCU = 4'h5;
  195. parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
  196. reg [17:0] STATE;
  197. initial STATE = ST_IDLE;
  198. reg [7:0] SNES_DINr;
  199. reg [7:0] SNES_DOUTr;
  200. reg [7:0] ROM_DOUTr;
  201. assign SNES_DATA = ~SNES_READ ? SNES_DOUTr
  202. : 8'bZ;
  203. reg [3:0] ST_MEM_DELAYr;
  204. reg MCU_RD_PENDr;
  205. reg MCU_WR_PENDr;
  206. reg [23:0] ROM_ADDRr;
  207. reg NEED_SNES_ADDRr;
  208. always @(posedge CLK2) begin
  209. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  210. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  211. end
  212. reg RQ_MCU_RDYr;
  213. initial RQ_MCU_RDYr = 1'b1;
  214. assign MCU_RDY = RQ_MCU_RDYr;
  215. reg ROM_SAr;
  216. initial ROM_SAr = 1'b1;
  217. //wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
  218. wire ROM_SA = ROM_SAr;
  219. assign ROM_ADDR = (ROM_SA) ? MAPPED_SNES_ADDR[22:0] : ROM_ADDRr[22:0];
  220. reg ROM_WEr;
  221. initial ROM_WEr = 1'b1;
  222. reg ROM_DOUT_ENr;
  223. initial ROM_DOUT_ENr = 1'b0;
  224. reg[17:0] SNES_DEAD_CNTr;
  225. initial SNES_DEAD_CNTr = 0;
  226. always @(posedge CLK2) begin
  227. if(MCU_RRQ) begin
  228. MCU_RD_PENDr <= 1'b1;
  229. RQ_MCU_RDYr <= 1'b0;
  230. ROM_ADDRr <= MCU_ADDR;
  231. end else if(MCU_WRQ) begin
  232. MCU_WR_PENDr <= 1'b1;
  233. RQ_MCU_RDYr <= 1'b0;
  234. ROM_ADDRr <= MCU_ADDR;
  235. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  236. MCU_RD_PENDr <= 1'b0;
  237. MCU_WR_PENDr <= 1'b0;
  238. RQ_MCU_RDYr <= 1'b1;
  239. end
  240. end
  241. always @(posedge CLK2) begin
  242. if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
  243. else SNES_DEAD_CNTr <= 17'h0;
  244. end
  245. always @(posedge CLK2) begin
  246. if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
  247. else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
  248. end
  249. reg snes_wr_cycle;
  250. always @(posedge CLK2) begin
  251. if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
  252. else
  253. case(STATE)
  254. ST_IDLE: begin
  255. ROM_SAr <= 1'b1;
  256. ROM_DOUT_ENr <= 1'b0;
  257. if(SNES_cycle_start & ~SNES_WRITE) begin
  258. STATE <= ST_SNES_WR_ADDR;
  259. if(IS_SAVERAM) begin
  260. ROM_WEr <= 1'b0;
  261. ROM_DOUT_ENr <= 1'b1;
  262. end
  263. end else if(SNES_cycle_start) begin
  264. // STATE <= ST_SNES_RD_ADDR;
  265. STATE <= ST_SNES_RD_END;
  266. SNES_DOUTr <= ROM_DATA[7:0] | ROM_DATA[15:8];
  267. //(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
  268. end else if(SNES_DEADr & MCU_RD_PENDr) begin
  269. STATE <= ST_MCU_RD_ADDR;
  270. end else if(SNES_DEADr & MCU_WR_PENDr) begin
  271. STATE <= ST_MCU_WR_ADDR;
  272. end
  273. end
  274. ST_SNES_RD_ADDR: begin
  275. ST_MEM_DELAYr <= ROM_RD_WAIT;
  276. STATE <= ST_SNES_RD_WAIT;
  277. end
  278. ST_SNES_RD_WAIT: begin
  279. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  280. // if(ST_MEM_DELAYr == 0) begin
  281. // end
  282. // else STATE <= ST_SNES_RD_WAIT;
  283. end
  284. ST_SNES_WR_ADDR: begin
  285. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  286. STATE <= ST_SNES_WR_WAIT1;
  287. end
  288. ST_SNES_WR_WAIT1: begin
  289. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  290. if(ST_MEM_DELAYr == 0) begin
  291. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  292. STATE <= ST_SNES_WR_WAIT2;
  293. ROM_DOUTr <= SNES_DATA;
  294. end
  295. else STATE <= ST_SNES_WR_WAIT1;
  296. end
  297. ST_SNES_WR_WAIT2: begin
  298. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  299. if(ST_MEM_DELAYr == 0) begin
  300. STATE <= ST_SNES_WR_END;
  301. ROM_WEr <= 1'b1;
  302. end
  303. else STATE <= ST_SNES_WR_WAIT2;
  304. end
  305. ST_SNES_RD_END, ST_SNES_WR_END: begin
  306. ROM_DOUT_ENr <= 1'b0;
  307. if(MCU_RD_PENDr) begin
  308. STATE <= ST_MCU_RD_ADDR;
  309. end else if(MCU_WR_PENDr) begin
  310. STATE <= ST_MCU_WR_ADDR;
  311. end else STATE <= ST_IDLE;
  312. end
  313. ST_MCU_RD_ADDR: begin
  314. ROM_SAr <= 1'b0;
  315. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  316. STATE <= ST_MCU_RD_WAIT;
  317. end
  318. ST_MCU_RD_WAIT: begin
  319. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  320. if(ST_MEM_DELAYr == 0) begin
  321. STATE <= ST_MCU_RD_END;
  322. end
  323. else STATE <= ST_MCU_RD_WAIT;
  324. end
  325. ST_MCU_RD_END: begin
  326. MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
  327. //ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
  328. STATE <= ST_IDLE;
  329. end
  330. ST_MCU_WR_ADDR: begin
  331. ROM_DOUTr <= MCU_DOUT;
  332. ROM_SAr <= 1'b0;
  333. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  334. STATE <= ST_MCU_WR_WAIT;
  335. ROM_DOUT_ENr <= 1'b1;
  336. ROM_WEr <= 1'b0;
  337. end
  338. ST_MCU_WR_WAIT: begin
  339. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  340. if(ST_MEM_DELAYr == 0) begin
  341. ROM_WEr <= 1'b1;
  342. STATE <= ST_MCU_WR_END;
  343. end
  344. else STATE <= ST_MCU_WR_WAIT;
  345. end
  346. ST_MCU_WR_END: begin
  347. ROM_DOUT_ENr <= 1'b0;
  348. STATE <= ST_IDLE;
  349. end
  350. endcase
  351. end
  352. reg ROM_WE_1;
  353. always @(posedge CLK2) begin
  354. ROM_WE_1 <= ROM_WE;
  355. end
  356. assign ROM_DATA[7:0] = (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
  357. assign ROM_DATA[15:8] = (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
  358. assign ROM_WE = ROM_WEr;
  359. // OE always active. Overridden by WE when needed.
  360. assign ROM_OE = 1'b0;
  361. assign ROM_CE = 1'b0;
  362. assign ROM_BHE = 1'b0;// /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
  363. assign ROM_BLE = 1'b0;// /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
  364. assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
  365. |(!IS_ROM & !IS_SAVERAM)
  366. |(SNES_READr[0] & SNES_WRITEr[0])
  367. );
  368. assign SNES_DATABUS_DIR = (!SNES_READr[0])
  369. ? 1'b1
  370. : 1'b0;
  371. assign SNES_IRQ = 1'b0;
  372. assign p113_out = 1'b0;
  373. /*
  374. wire [35:0] CONTROL0;
  375. icon icon (
  376. .CONTROL0(CONTROL0) // INOUT BUS [35:0]
  377. );
  378. ila_srtc ila (
  379. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  380. .CLK(CLK2), // IN
  381. .TRIG0(SNES_ADDR), // IN BUS [23:0]
  382. .TRIG1(SNES_DATA), // IN BUS [7:0]
  383. .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
  384. .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
  385. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  386. .TRIG5(ROM_DATA), // IN BUS [15:0]
  387. .TRIG6(MCU_DINr), // IN BUS [7:0]
  388. .TRIG7(spi_byte_cnt[3:0])
  389. );
  390. */
  391. /*
  392. ila_srtc ila (
  393. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  394. .CLK(CLK2), // IN
  395. .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
  396. .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
  397. .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
  398. .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
  399. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  400. .TRIG5(ROM_DATA), // IN BUS [15:0]
  401. .TRIG6(MCU_DINr), // IN BUS [7:0]
  402. .TRIG7(ST_MEM_DELAYr)
  403. );
  404. */
  405. endmodule