sd_dma.v 3.3 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 19:19:08 12/01/2010
  7. // Design Name:
  8. // Module Name: sd_dma
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module sd_dma(
  22. input [3:0] SD_DAT,
  23. inout SD_CLK,
  24. input CLK,
  25. input SD_DMA_EN,
  26. output SD_DMA_STATUS,
  27. output SD_DMA_SRAM_WE,
  28. output SD_DMA_NEXTADDR,
  29. output [7:0] SD_DMA_SRAM_DATA,
  30. input SD_DMA_PARTIAL,
  31. input [10:0] SD_DMA_PARTIAL_START,
  32. input [10:0] SD_DMA_PARTIAL_END
  33. );
  34. reg [10:0] SD_DMA_STARTr;
  35. reg [10:0] SD_DMA_ENDr;
  36. reg SD_DMA_PARTIALr;
  37. always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
  38. reg SD_DMA_DONEr;
  39. reg[1:0] SD_DMA_DONEr2;
  40. initial begin
  41. SD_DMA_DONEr2 = 2'b00;
  42. SD_DMA_DONEr = 1'b0;
  43. end
  44. always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
  45. wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
  46. reg [1:0] SD_DMA_ENr;
  47. initial SD_DMA_ENr = 2'b00;
  48. always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
  49. wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
  50. reg SD_DMA_STATUSr;
  51. assign SD_DMA_STATUS = SD_DMA_STATUSr;
  52. // we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
  53. reg [10:0] cyclecnt;
  54. initial cyclecnt = 11'd0;
  55. reg SD_DMA_SRAM_WEr;
  56. initial SD_DMA_SRAM_WEr = 1'b1;
  57. assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
  58. reg SD_DMA_NEXTADDRr;
  59. assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
  60. reg[7:0] SD_DMA_SRAM_DATAr;
  61. assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
  62. // we have 4 internal cycles per SD clock, 8 per RAM byte write
  63. reg [2:0] clkcnt;
  64. initial clkcnt = 3'b000;
  65. reg [1:0] SD_CLKr;
  66. always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
  67. assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
  68. always @(posedge CLK) begin
  69. if(SD_DMA_EN_rising) begin
  70. SD_DMA_STATUSr <= 1'b1;
  71. SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
  72. SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
  73. end
  74. else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
  75. end
  76. always @(posedge CLK) begin
  77. if(cyclecnt == 1042) SD_DMA_DONEr <= 1;
  78. else SD_DMA_DONEr <= 0;
  79. end
  80. always @(posedge CLK) begin
  81. if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
  82. clkcnt <= 0;
  83. end else begin
  84. if(SD_DMA_STATUSr) begin
  85. clkcnt <= clkcnt + 1;
  86. end
  87. end
  88. end
  89. always @(posedge CLK) begin
  90. if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0;
  91. else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1;
  92. end
  93. // we have 8 clk cycles to complete one RAM write
  94. // (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
  95. always @(posedge CLK) begin
  96. if(SD_DMA_STATUSr) begin
  97. case(clkcnt[2:0])
  98. 3'h0: begin
  99. SD_DMA_SRAM_WEr <= 1'b1;
  100. SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
  101. if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
  102. end
  103. 3'h1:
  104. SD_DMA_NEXTADDRr <= 1'b0;
  105. // 3'h2:
  106. 3'h3:
  107. if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
  108. 3'h4:
  109. SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
  110. // 3'h5:
  111. // 3'h6:
  112. // 3'h7:
  113. endcase
  114. end
  115. end
  116. endmodule