main.v 16 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. output SNES_IRQ,
  32. output SNES_DATABUS_OE,
  33. output SNES_DATABUS_DIR,
  34. input SNES_SYSCLK,
  35. input SNES_REFRESH,
  36. input [7:0] SNES_PA,
  37. input SNES_PARD,
  38. input SNES_PAWR,
  39. /* SRAM signals */
  40. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  41. inout [15:0] ROM_DATA,
  42. output [22:0] ROM_ADDR,
  43. output ROM_CE,
  44. output ROM_OE,
  45. output ROM_WE,
  46. output ROM_BHE,
  47. output ROM_BLE,
  48. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  49. inout [7:0] RAM_DATA,
  50. output [18:0] RAM_ADDR,
  51. output RAM_OE,
  52. output RAM_WE,
  53. /* MCU signals */
  54. input SPI_MOSI,
  55. inout SPI_MISO,
  56. input SPI_SS,
  57. inout SPI_SCK,
  58. input MCU_OVR,
  59. output MCU_RDY,
  60. output DAC_MCLK,
  61. output DAC_LRCK,
  62. output DAC_SDOUT,
  63. /* SD signals */
  64. input [3:0] SD_DAT,
  65. inout SD_CMD,
  66. inout SD_CLK,
  67. /* debug */
  68. output p113_out
  69. );
  70. wire [31:0] snes_sysclk_freq;
  71. wire [31:0] snes_read_freq;
  72. wire [31:0] snes_write_freq;
  73. wire [31:0] snes_pard_freq;
  74. wire [31:0] snes_pawr_freq;
  75. wire [31:0] snes_refresh_freq;
  76. wire [31:0] snes_cpuclk_freq;
  77. wire [31:0] snes_romsel_freq;
  78. clk_test snes_clk_test (
  79. .clk(CLK2),
  80. .sysclk(SNES_SYSCLK),
  81. .read(SNES_READ),
  82. .write(SNES_WRITE),
  83. .pard(SNES_PARD),
  84. .pawr(SNES_PAWR),
  85. .refresh(SNES_REFRESH),
  86. .cpuclk(SNES_CPU_CLK),
  87. .romsel(SNES_CS),
  88. .snes_sysclk_freq(snes_sysclk_freq),
  89. .snes_read_freq(snes_read_freq),
  90. .snes_write_freq(snes_write_freq),
  91. .snes_pard_freq(snes_pard_freq),
  92. .snes_pawr_freq(snes_pawr_freq),
  93. .snes_refresh_freq(snes_refresh_freq),
  94. .snes_cpuclk_freq(snes_cpuclk_freq),
  95. .snes_romsel_freq(snes_romsel_freq)
  96. );
  97. wire [7:0] spi_cmd_data;
  98. wire [7:0] spi_param_data;
  99. wire [7:0] spi_input_data;
  100. wire [31:0] spi_byte_cnt;
  101. wire [2:0] spi_bit_cnt;
  102. wire [23:0] MCU_ADDR;
  103. wire [2:0] MAPPER;
  104. wire [23:0] SAVERAM_MASK;
  105. wire [23:0] ROM_MASK;
  106. wire [7:0] SD_DMA_SRAM_DATA;
  107. wire [1:0] SD_DMA_TGT;
  108. wire [10:0] SD_DMA_PARTIAL_START;
  109. wire [10:0] SD_DMA_PARTIAL_END;
  110. wire [10:0] dac_addr;
  111. wire [23:0] ram0_addr;
  112. wire [18:0] ram1_addr;
  113. wire [7:0] PA_addr;
  114. wire [12:0] bram_addr;
  115. wire ROM_ADDR0;
  116. sd_dma snes_sd_dma(
  117. .CLK(CLK2),
  118. .SD_DAT(SD_DAT),
  119. .SD_CLK(SD_CLK),
  120. .SD_DMA_EN(SD_DMA_EN),
  121. .SD_DMA_STATUS(SD_DMA_STATUS),
  122. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  123. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  124. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  125. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  126. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  127. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
  128. );
  129. wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
  130. dac snes_dac(
  131. .clkin(CLK2),
  132. .sysclk(SNES_SYSCLK),
  133. .mclk(DAC_MCLK),
  134. .lrck(DAC_LRCK),
  135. .sdout(DAC_SDOUT),
  136. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  137. .pgm_address(dac_addr),
  138. .pgm_data(SD_DMA_SRAM_DATA),
  139. .DAC_STATUS(DAC_STATUS),
  140. .play(dac_play),
  141. .reset(dac_reset)
  142. );
  143. spi snes_spi(
  144. .clk(CLK2),
  145. .MOSI(SPI_MOSI),
  146. .MISO(SPI_MISO),
  147. .SSEL(SPI_SS),
  148. .SCK(SPI_SCK),
  149. .cmd_ready(spi_cmd_ready),
  150. .param_ready(spi_param_ready),
  151. .cmd_data(spi_cmd_data),
  152. .param_data(spi_param_data),
  153. .endmessage(spi_endmessage),
  154. .startmessage(spi_startmessage),
  155. .input_data(spi_input_data),
  156. .byte_cnt(spi_byte_cnt),
  157. .bit_cnt(spi_bit_cnt)
  158. );
  159. reg [7:0] MCU_DINr;
  160. wire [7:0] MCU_DOUT;
  161. wire [7:0] mcu_bram_data_in;
  162. wire [7:0] mcu_bram_data_out;
  163. wire [12:0] mcu_bram_addr;
  164. mcu_cmd snes_mcu_cmd(
  165. .clk(CLK2),
  166. .cmd_ready(spi_cmd_ready),
  167. .param_ready(spi_param_ready),
  168. .cmd_data(spi_cmd_data),
  169. .param_data(spi_param_data),
  170. .mcu_mapper(MAPPER),
  171. .mcu_write(MCU_WRITE),
  172. .mcu_data_in(MCU_DINr),
  173. .mcu_data_out(MCU_DOUT),
  174. .spi_byte_cnt(spi_byte_cnt),
  175. .spi_bit_cnt(spi_bit_cnt),
  176. .spi_data_out(spi_input_data),
  177. .addr_out(MCU_ADDR),
  178. .saveram_mask_out(SAVERAM_MASK),
  179. .rom_mask_out(ROM_MASK),
  180. .SD_DMA_EN(SD_DMA_EN),
  181. .SD_DMA_STATUS(SD_DMA_STATUS),
  182. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  183. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  184. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  185. .SD_DMA_TGT(SD_DMA_TGT),
  186. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  187. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  188. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  189. .dac_addr_out(dac_addr),
  190. .DAC_STATUS(DAC_STATUS),
  191. // .dac_volume_out(dac_volume),
  192. // .dac_volume_latch_out(dac_vol_latch),
  193. .dac_play_out(dac_play),
  194. .dac_reset_out(dac_reset),
  195. .featurebits_out(featurebits),
  196. .mcu_rrq(MCU_RRQ),
  197. .mcu_wrq(MCU_WRQ),
  198. .mcu_rq_rdy(MCU_RDY),
  199. .ramsel_out(MCU_RAMSEL),
  200. .snes_sysclk_freq(snes_sysclk_freq),
  201. .snes_read_freq(snes_read_freq),
  202. .snes_write_freq(snes_write_freq),
  203. .snes_pard_freq(snes_pard_freq),
  204. .snes_pawr_freq(snes_pawr_freq),
  205. .snes_refresh_freq(snes_refresh_freq),
  206. .snes_cpuclk_freq(snes_cpuclk_freq),
  207. .snes_romsel_freq(snes_romsel_freq),
  208. .mcu_bram_addr(mcu_bram_addr),
  209. .mcu_bram_data_in(mcu_bram_data_in),
  210. .mcu_bram_data_out(mcu_bram_data_out),
  211. .mcu_bram_we(mcu_bram_we)
  212. );
  213. wire [7:0] DCM_STATUS;
  214. // dcm1: dfs 4x
  215. my_dcm snes_dcm(
  216. .CLKIN(CLKIN),
  217. .CLKFX(CLK2),
  218. .LOCKED(DCM_LOCKED),
  219. .RST(DCM_RST),
  220. .STATUS(DCM_STATUS)
  221. );
  222. assign DCM_RST=0;
  223. reg [5:0] SNES_READr;
  224. reg [5:0] SNES_WRITEr;
  225. reg [5:0] SNES_CPU_CLKr;
  226. wire SNES_RD_start = (SNES_READr == 6'b111110);
  227. wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
  228. wire SNES_WR_rising = (SNES_WRITEr == 6'b000001);
  229. wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
  230. wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
  231. always @(posedge CLK2) begin
  232. SNES_READr <= {SNES_READr[4:0], SNES_READ};
  233. SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
  234. SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
  235. end
  236. reg [7:0] ram0_bank;
  237. initial ram0_bank = 8'h00;
  238. reg ram0_linear;
  239. initial ram0_linear = 1'b0;
  240. address snes_addr(
  241. .CLK(CLK2),
  242. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  243. .ram0_addr(ram0_addr), // Address to request from SRAM (active low)
  244. .ram1_addr(ram1_addr),
  245. .PA_addr(PA_addr),
  246. .bram_addr(bram_addr),
  247. .ram0_enable(ram0_enable),
  248. .ram1_enable(ram1_enable),
  249. .PA_enable(PA_enable),
  250. .bram_enable(bram_enable),
  251. .ram0_bank(ram0_bank),
  252. .ram0_linear(ram0_linear),
  253. .irq_enable(irq_enable),
  254. .bank_enable(bank_enable),
  255. .linear_enable(linear_enable)
  256. );
  257. always @(posedge CLK2) begin
  258. if(SNES_WR_rising && bank_enable) ram0_bank <= SNES_DATA;
  259. end
  260. always @(posedge CLK2) begin
  261. if(SNES_WR_rising && linear_enable) ram0_linear <= SNES_DATA[0];
  262. end
  263. reg [7:0] irq_count_r;
  264. initial irq_count_r = 8'b0;
  265. reg SNES_IRQr;
  266. initial SNES_IRQr = 0;
  267. always @(posedge CLK2) begin
  268. if(SNES_WR_rising & irq_enable) SNES_IRQr <= 1'b1;
  269. else if(irq_count_r == 8'h00) SNES_IRQr <= 1'b0;
  270. end
  271. always @(posedge CLK2) begin
  272. if(SNES_WR_rising & irq_enable) irq_count_r <= 8'h01;
  273. else irq_count_r <= irq_count_r + 1;
  274. end
  275. wire [7:0] bram_data_out;
  276. bram test_bram (
  277. .clka(CLK2), // input clka
  278. .wea(~SNES_WRITE & bram_enable), // input [0 : 0] wea
  279. .addra(bram_addr), // input [12 : 0] addra
  280. .dina(SNES_DATA), // input [7 : 0] dina
  281. .douta(bram_data_out), // output [7 : 0] douta
  282. .clkb(CLK2), // input clkb
  283. .web(mcu_bram_we), // input [0 : 0] web
  284. .addrb(mcu_bram_addr), // input [12 : 0] addrb
  285. .dinb(mcu_bram_data_out), // input [7 : 0] dinb
  286. .doutb(mcu_bram_data_in) // output [7 : 0] doutb
  287. );
  288. reg [1:0] SNES_PAWR_start_r;
  289. always @(posedge CLK2) SNES_PAWR_start_r <= {SNES_PAWR_start_r[0], SNES_PAWR};
  290. wire SNES_PAWR_start = (SNES_PAWR_start_r == 2'b01);
  291. wire [7:0] PA_data_out;
  292. PA test_PA (
  293. .clka(CLK2), // input clka
  294. .wea(SNES_PAWR_start), // input [0 : 0] wea
  295. .addra(SNES_PA), // input [7 : 0] addra
  296. .dina(SNES_DATA), // input [7 : 0] dina
  297. .clkb(CLK2), // input clkb
  298. .addrb(PA_addr), // input [7 : 0] addrb
  299. .doutb(PA_data_out) // output [7 : 0] doutb
  300. );
  301. parameter MODE_SNES = 1'b0;
  302. parameter MODE_MCU = 1'b1;
  303. parameter ST_IDLE = 18'b000000000000000001;
  304. parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
  305. parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
  306. parameter ST_SNES_RD_END = 18'b000000000000001000;
  307. parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
  308. parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
  309. parameter ST_SNES_WR_DATA = 18'b000000000001000000;
  310. parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
  311. parameter ST_SNES_WR_END = 18'b000000000100000000;
  312. parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
  313. parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
  314. parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
  315. parameter ST_MCU_RD_END = 18'b000001000000000000;
  316. parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
  317. parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
  318. parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
  319. parameter ST_MCU_WR_END = 18'b010000000000000000;
  320. parameter ROM_RD_WAIT = 4'h4;
  321. parameter ROM_RD_WAIT_MCU = 4'h6;
  322. parameter ROM_WR_WAIT1 = 4'h2;
  323. parameter ROM_WR_WAIT2 = 4'h3;
  324. parameter ROM_WR_WAIT_MCU = 4'h6;
  325. reg [17:0] STATE;
  326. initial STATE = ST_IDLE;
  327. reg [7:0] SNES_DINr;
  328. reg [7:0] ROM_DOUTr;
  329. reg [7:0] RAM_DOUTr;
  330. assign SNES_DATA = (!SNES_READ) ? (ram0_enable ? SNES_DINr
  331. :ram1_enable ? SNES_DINr
  332. :bram_enable ? bram_data_out
  333. :PA_enable ? PA_data_out
  334. :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
  335. reg [3:0] ST_MEM_DELAYr;
  336. reg MCU_RD_PENDr;
  337. reg MCU_WR_PENDr;
  338. reg [23:0] ROM_ADDRr;
  339. reg [18:0] RAM_ADDRr;
  340. reg NEED_SNES_ADDRr;
  341. always @(posedge CLK2) begin
  342. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  343. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  344. end
  345. wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
  346. assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[22:0] : (ASSERT_SNES_ADDR) ? ram0_addr[22:0] : ROM_ADDRr[22:0];
  347. assign ROM_ADDR0 = 1'b0; //(SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0];
  348. assign RAM_ADDR = ASSERT_SNES_ADDR ? ram1_addr : RAM_ADDRr;
  349. reg ROM_WEr;
  350. initial ROM_WEr = 1'b1;
  351. reg RAM_WEr;
  352. initial RAM_WEr = 1'b1;
  353. reg RQ_MCU_RDYr;
  354. initial RQ_MCU_RDYr = 1'b1;
  355. assign MCU_RDY = RQ_MCU_RDYr;
  356. always @(posedge CLK2) begin
  357. if(MCU_RRQ) begin
  358. MCU_RD_PENDr <= 1'b1;
  359. RQ_MCU_RDYr <= 1'b0;
  360. end else if(MCU_WRQ) begin
  361. MCU_WR_PENDr <= 1'b1;
  362. RQ_MCU_RDYr <= 1'b0;
  363. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  364. MCU_RD_PENDr <= 1'b0;
  365. MCU_WR_PENDr <= 1'b0;
  366. RQ_MCU_RDYr <= 1'b1;
  367. end
  368. end
  369. reg snes_wr_cycle;
  370. wire ram_enable = ram0_enable | ram1_enable;
  371. always @(posedge CLK2) begin
  372. if(ram_enable & SNES_cycle_start & ~SNES_WR_start) begin
  373. STATE <= ST_SNES_RD_ADDR;
  374. end else if(ram_enable & SNES_WR_start) begin
  375. snes_wr_cycle <= 1'b1;
  376. STATE <= ST_SNES_WR_ADDR;
  377. end else begin
  378. case(STATE)
  379. ST_IDLE: begin
  380. if(ram0_enable) ROM_ADDRr <= ram0_addr;
  381. if(ram1_enable) RAM_ADDRr <= ram1_addr;
  382. if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
  383. else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
  384. else STATE <= ST_IDLE;
  385. end
  386. ST_SNES_RD_ADDR: begin
  387. STATE <= ST_SNES_RD_WAIT;
  388. ST_MEM_DELAYr <= ROM_RD_WAIT;
  389. end
  390. ST_SNES_RD_WAIT: begin
  391. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  392. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
  393. else STATE <= ST_SNES_RD_WAIT;
  394. if(ram0_enable) begin
  395. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
  396. else SNES_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
  397. end else if(ram1_enable) begin
  398. SNES_DINr <= RAM_DATA[7:0];
  399. end
  400. end
  401. ST_SNES_RD_END: begin
  402. STATE <= ST_IDLE;
  403. if(ram0_enable) begin
  404. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
  405. else SNES_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
  406. end else if(ram1_enable) begin
  407. SNES_DINr <= RAM_DATA[7:0];
  408. end
  409. end
  410. ST_SNES_WR_ADDR: begin
  411. if(ram0_enable) ROM_WEr <= 1'b0;
  412. if(ram1_enable) RAM_WEr <= 1'b0;
  413. STATE <= ST_SNES_WR_WAIT1;
  414. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  415. end
  416. ST_SNES_WR_WAIT1: begin
  417. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  418. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
  419. else STATE <= ST_SNES_WR_WAIT1;
  420. end
  421. ST_SNES_WR_DATA: begin
  422. if(ram0_enable) ROM_DOUTr <= SNES_DATA;
  423. if(ram1_enable) RAM_DOUTr <= SNES_DATA;
  424. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  425. STATE <= ST_SNES_WR_WAIT2;
  426. end
  427. ST_SNES_WR_WAIT2: begin
  428. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  429. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
  430. else STATE <= ST_SNES_WR_WAIT2;
  431. end
  432. ST_SNES_WR_END: begin
  433. STATE <= ST_IDLE;
  434. ROM_WEr <= 1'b1;
  435. RAM_WEr <= 1'b1;
  436. snes_wr_cycle <= 1'b0;
  437. end
  438. ST_MCU_RD_ADDR: begin
  439. if(MCU_RAMSEL == 1'b0) ROM_ADDRr <= MCU_ADDR;
  440. else RAM_ADDRr <= MCU_ADDR;
  441. STATE <= ST_MCU_RD_WAIT;
  442. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  443. end
  444. ST_MCU_RD_WAIT: begin
  445. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  446. if(ST_MEM_DELAYr == 4'h0) begin
  447. STATE <= ST_MCU_RD_WAIT2;
  448. ST_MEM_DELAYr <= 4'h2;
  449. end
  450. else STATE <= ST_MCU_RD_WAIT;
  451. if(MCU_RAMSEL == 1'b0) begin
  452. if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
  453. else MCU_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
  454. end else MCU_DINr <= RAM_DATA;
  455. end
  456. ST_MCU_RD_WAIT2: begin
  457. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  458. if(ST_MEM_DELAYr == 4'h0) begin
  459. STATE <= ST_MCU_RD_END;
  460. end else STATE <= ST_MCU_RD_WAIT2;
  461. end
  462. ST_MCU_RD_END: begin
  463. STATE <= ST_IDLE;
  464. end
  465. ST_MCU_WR_ADDR: begin
  466. if(MCU_RAMSEL == 1'b0) ROM_ADDRr <= MCU_ADDR;
  467. else RAM_ADDRr <= MCU_ADDR;
  468. STATE <= ST_MCU_WR_WAIT;
  469. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  470. if(MCU_RAMSEL == 1'b0) ROM_DOUTr <= MCU_DOUT;
  471. else RAM_DOUTr <= MCU_DOUT;
  472. if(MCU_RAMSEL == 1'b0)
  473. ROM_WEr <= 1'b0;
  474. else if(MCU_RAMSEL == 1'b1)
  475. RAM_WEr <= 1'b0;
  476. end
  477. ST_MCU_WR_WAIT: begin
  478. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  479. if(ST_MEM_DELAYr == 4'h0) begin
  480. ROM_WEr <= 1'b1;
  481. RAM_WEr <= 1'b1;
  482. STATE <= ST_MCU_WR_WAIT2;
  483. ST_MEM_DELAYr <= 4'h2;
  484. end
  485. else begin
  486. STATE <= ST_MCU_WR_WAIT;
  487. end
  488. end
  489. ST_MCU_WR_WAIT2: begin
  490. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  491. if(ST_MEM_DELAYr == 4'h0) begin
  492. STATE <= ST_MCU_WR_END;
  493. end else STATE <= ST_MCU_WR_WAIT2;
  494. end
  495. ST_MCU_WR_END: begin
  496. STATE <= ST_IDLE;
  497. end
  498. endcase
  499. end
  500. end
  501. assign ROM_DATA[7:0] = (SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
  502. : (!ROM_WE ? ROM_DOUTr : 8'bZ)
  503. );
  504. assign ROM_DATA[15:8] = (SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
  505. : (!ROM_WE ? ROM_DOUTr : 8'bZ)
  506. );
  507. assign RAM_DATA = !RAM_WE ? RAM_DOUTr : 8'bZ;
  508. assign ROM_WE = SD_DMA_TO_ROM
  509. ?MCU_WRITE
  510. :ROM_WEr | (ASSERT_SNES_ADDR & ~(snes_wr_cycle & ram0_enable));
  511. assign RAM_WE = RAM_WEr | (ASSERT_SNES_ADDR & ~(snes_wr_cycle & ram1_enable));
  512. assign RAM_OE = 1'b0;
  513. // OE always active. Overridden by WE when needed.
  514. assign ROM_OE = 1'b0;
  515. assign ROM_CE = 1'b0;
  516. assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
  517. assign ROM_BLE = !ROM_WE ? ROM_ADDR0 : 1'b0;
  518. assign SNES_DATABUS_OE = PA_enable ? 1'b0
  519. : bram_enable ? 1'b0
  520. : (~SNES_PAWR & SNES_READ) ? 1'b0
  521. : SNES_CS ? SNES_WRITE
  522. :((SNES_CS)
  523. |(!ram0_enable & !ram1_enable)
  524. |(SNES_READ & SNES_WRITE)
  525. );
  526. assign SNES_DATABUS_DIR = ~SNES_READ ? 1'b1 : 1'b0;
  527. assign IRQ_DIR = 1'b0;
  528. assign SNES_IRQ = SNES_IRQr;
  529. assign p113_out = 1'b0;
  530. endmodule