PA.xco 3.0 KB

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  1. ##############################################################
  2. #
  3. # Xilinx Core Generator version 13.4
  4. # Date: Fri Aug 17 17:03:15 2012
  5. #
  6. ##############################################################
  7. #
  8. # This file contains the customisation parameters for a
  9. # Xilinx CORE Generator IP GUI. It is strongly recommended
  10. # that you do not manually alter this file as it may cause
  11. # unexpected and unsupported behavior.
  12. #
  13. ##############################################################
  14. #
  15. # Generated from component: xilinx.com:ip:blk_mem_gen:6.2
  16. #
  17. ##############################################################
  18. #
  19. # BEGIN Project Options
  20. SET addpads = false
  21. SET asysymbol = true
  22. SET busformat = BusFormatAngleBracketNotRipped
  23. SET createndf = false
  24. SET designentry = Verilog
  25. SET device = xa3s400
  26. SET devicefamily = aspartan3
  27. SET flowvendor = Other
  28. SET formalverification = false
  29. SET foundationsym = false
  30. SET implementationfiletype = Ngc
  31. SET package = pqg208
  32. SET removerpms = false
  33. SET simulationfiles = Behavioral
  34. SET speedgrade = -4q
  35. SET verilogsim = true
  36. SET vhdlsim = false
  37. # END Project Options
  38. # BEGIN Select
  39. SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
  40. # END Select
  41. # BEGIN Parameters
  42. CSET additional_inputs_for_power_estimation=false
  43. CSET algorithm=Minimum_Area
  44. CSET assume_synchronous_clk=true
  45. CSET axi_id_width=4
  46. CSET axi_slave_type=Memory_Slave
  47. CSET axi_type=AXI4_Full
  48. CSET byte_size=9
  49. CSET coe_file=no_coe_file_loaded
  50. CSET collision_warnings=ALL
  51. CSET component_name=PA
  52. CSET disable_collision_warnings=false
  53. CSET disable_out_of_range_warnings=false
  54. CSET ecc=false
  55. CSET ecctype=No_ECC
  56. CSET enable_a=Always_Enabled
  57. CSET enable_b=Always_Enabled
  58. CSET error_injection_type=Single_Bit_Error_Injection
  59. CSET fill_remaining_memory_locations=false
  60. CSET interface_type=Native
  61. CSET load_init_file=false
  62. CSET memory_type=Simple_Dual_Port_RAM
  63. CSET operating_mode_a=WRITE_FIRST
  64. CSET operating_mode_b=WRITE_FIRST
  65. CSET output_reset_value_a=0
  66. CSET output_reset_value_b=0
  67. CSET pipeline_stages=0
  68. CSET port_a_clock=100
  69. CSET port_a_enable_rate=100
  70. CSET port_a_write_rate=50
  71. CSET port_b_clock=100
  72. CSET port_b_enable_rate=100
  73. CSET port_b_write_rate=0
  74. CSET primitive=8kx2
  75. CSET read_width_a=8
  76. CSET read_width_b=8
  77. CSET register_porta_input_of_softecc=false
  78. CSET register_porta_output_of_memory_core=false
  79. CSET register_porta_output_of_memory_primitives=false
  80. CSET register_portb_output_of_memory_core=false
  81. CSET register_portb_output_of_memory_primitives=false
  82. CSET register_portb_output_of_softecc=false
  83. CSET remaining_memory_locations=0
  84. CSET reset_memory_latch_a=false
  85. CSET reset_memory_latch_b=false
  86. CSET reset_priority_a=CE
  87. CSET reset_priority_b=CE
  88. CSET reset_type=SYNC
  89. CSET softecc=false
  90. CSET use_axi_id=false
  91. CSET use_byte_write_enable=false
  92. CSET use_error_injection_pins=false
  93. CSET use_regcea_pin=false
  94. CSET use_regceb_pin=false
  95. CSET use_rsta_pin=false
  96. CSET use_rstb_pin=false
  97. CSET write_depth_a=256
  98. CSET write_width_a=8
  99. CSET write_width_b=8
  100. # END Parameters
  101. # BEGIN Extra information
  102. MISC pkg_timestamp=2011-03-11T08:24:14Z
  103. # END Extra information
  104. GENERATE
  105. # CRC: 370f2518