main.v 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742
  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR_IN,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. output SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. input SNES_SYSCLK,
  36. input [7:0] SNES_PA,
  37. input SNES_PARD,
  38. input SNES_PAWR,
  39. /* SRAM signals */
  40. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  41. inout [15:0] ROM_DATA,
  42. output [22:0] ROM_ADDR,
  43. output ROM_CE,
  44. output ROM_OE,
  45. output ROM_WE,
  46. output ROM_BHE,
  47. output ROM_BLE,
  48. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  49. inout [7:0] RAM_DATA,
  50. output [18:0] RAM_ADDR,
  51. output RAM_CE,
  52. output RAM_OE,
  53. output RAM_WE,
  54. /* MCU signals */
  55. input SPI_MOSI,
  56. inout SPI_MISO,
  57. input SPI_SS,
  58. inout SPI_SCK,
  59. input MCU_OVR,
  60. output MCU_RDY,
  61. output DAC_MCLK,
  62. output DAC_LRCK,
  63. output DAC_SDOUT,
  64. /* SD signals */
  65. input [3:0] SD_DAT,
  66. inout SD_CMD,
  67. inout SD_CLK,
  68. /* debug */
  69. output p113_out
  70. );
  71. wire CLK2;
  72. reg [23:0] SNES_ADDR_r [2:0];
  73. always @(posedge CLK2) begin
  74. SNES_ADDR_r[2] <= SNES_ADDR_r[1];
  75. SNES_ADDR_r[1] <= SNES_ADDR_r[0];
  76. SNES_ADDR_r[0] <= SNES_ADDR_IN;
  77. end
  78. wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
  79. wire [7:0] CX4_SNES_DATA_IN;
  80. wire [7:0] CX4_SNES_DATA_OUT;
  81. wire [7:0] spi_cmd_data;
  82. wire [7:0] spi_param_data;
  83. wire [7:0] spi_input_data;
  84. wire [31:0] spi_byte_cnt;
  85. wire [2:0] spi_bit_cnt;
  86. wire [23:0] MCU_ADDR;
  87. wire [2:0] MAPPER;
  88. wire [23:0] SAVERAM_MASK;
  89. wire [23:0] ROM_MASK;
  90. wire [7:0] SD_DMA_SRAM_DATA;
  91. wire [1:0] SD_DMA_TGT;
  92. wire [10:0] SD_DMA_PARTIAL_START;
  93. wire [10:0] SD_DMA_PARTIAL_END;
  94. wire [10:0] dac_addr;
  95. wire [7:0] msu_volumerq_out;
  96. wire [6:0] msu_status_out;
  97. wire [31:0] msu_addressrq_out;
  98. wire [15:0] msu_trackrq_out;
  99. wire [13:0] msu_write_addr;
  100. wire [13:0] msu_ptr_addr;
  101. wire [7:0] MSU_SNES_DATA_IN;
  102. wire [7:0] MSU_SNES_DATA_OUT;
  103. wire [5:0] msu_status_reset_bits;
  104. wire [5:0] msu_status_set_bits;
  105. wire [23:0] MAPPED_SNES_ADDR;
  106. wire ROM_ADDR0;
  107. wire [23:0] cx4_datrom_data;
  108. wire [9:0] cx4_datrom_addr;
  109. wire cx4_datrom_we;
  110. sd_dma snes_sd_dma(
  111. .CLK(CLK2),
  112. .SD_DAT(SD_DAT),
  113. .SD_CLK(SD_CLK),
  114. .SD_DMA_EN(SD_DMA_EN),
  115. .SD_DMA_STATUS(SD_DMA_STATUS),
  116. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  117. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  118. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  119. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  120. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  121. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  122. .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
  123. .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
  124. );
  125. wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
  126. dac snes_dac(
  127. .clkin(CLK2),
  128. .sysclk(SNES_SYSCLK),
  129. .mclk(DAC_MCLK),
  130. .lrck(DAC_LRCK),
  131. .sdout(DAC_SDOUT),
  132. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  133. .pgm_address(dac_addr),
  134. .pgm_data(SD_DMA_SRAM_DATA),
  135. .DAC_STATUS(DAC_STATUS),
  136. .volume(msu_volumerq_out),
  137. .vol_latch(msu_volume_latch_out),
  138. .play(dac_play),
  139. .reset(dac_reset)
  140. );
  141. msu snes_msu (
  142. .clkin(CLK2),
  143. .enable(msu_enable),
  144. .pgm_address(msu_write_addr),
  145. .pgm_data(SD_DMA_SRAM_DATA),
  146. .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
  147. .reg_addr(SNES_ADDR[2:0]),
  148. .reg_data_in(MSU_SNES_DATA_IN),
  149. .reg_data_out(MSU_SNES_DATA_OUT),
  150. .reg_oe(SNES_READ),
  151. .reg_we(SNES_WRITE),
  152. .status_out(msu_status_out),
  153. .volume_out(msu_volumerq_out),
  154. .volume_latch_out(msu_volume_latch_out),
  155. .addr_out(msu_addressrq_out),
  156. .track_out(msu_trackrq_out),
  157. .status_reset_bits(msu_status_reset_bits),
  158. .status_set_bits(msu_status_set_bits),
  159. .status_reset_we(msu_status_reset_we),
  160. .msu_address_ext(msu_ptr_addr),
  161. .msu_address_ext_write(msu_addr_reset)
  162. );
  163. spi snes_spi(
  164. .clk(CLK2),
  165. .MOSI(SPI_MOSI),
  166. .MISO(SPI_MISO),
  167. .SSEL(SPI_SS),
  168. .SCK(SPI_SCK),
  169. .cmd_ready(spi_cmd_ready),
  170. .param_ready(spi_param_ready),
  171. .cmd_data(spi_cmd_data),
  172. .param_data(spi_param_data),
  173. .endmessage(spi_endmessage),
  174. .startmessage(spi_startmessage),
  175. .input_data(spi_input_data),
  176. .byte_cnt(spi_byte_cnt),
  177. .bit_cnt(spi_bit_cnt)
  178. );
  179. reg [7:0] MCU_DINr;
  180. wire [7:0] MCU_DOUT;
  181. mcu_cmd snes_mcu_cmd(
  182. .clk(CLK2),
  183. .snes_sysclk(SNES_SYSCLK),
  184. .cmd_ready(spi_cmd_ready),
  185. .param_ready(spi_param_ready),
  186. .cmd_data(spi_cmd_data),
  187. .param_data(spi_param_data),
  188. .mcu_mapper(MAPPER),
  189. .mcu_write(MCU_WRITE),
  190. .mcu_data_in(MCU_DINr),
  191. .mcu_data_out(MCU_DOUT),
  192. .spi_byte_cnt(spi_byte_cnt),
  193. .spi_bit_cnt(spi_bit_cnt),
  194. .spi_data_out(spi_input_data),
  195. .addr_out(MCU_ADDR),
  196. .saveram_mask_out(SAVERAM_MASK),
  197. .rom_mask_out(ROM_MASK),
  198. .SD_DMA_EN(SD_DMA_EN),
  199. .SD_DMA_STATUS(SD_DMA_STATUS),
  200. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  201. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  202. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  203. .SD_DMA_TGT(SD_DMA_TGT),
  204. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  205. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  206. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  207. .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
  208. .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
  209. .dac_addr_out(dac_addr),
  210. .DAC_STATUS(DAC_STATUS),
  211. // .dac_volume_out(dac_volume),
  212. // .dac_volume_latch_out(dac_vol_latch),
  213. .dac_play_out(dac_play),
  214. .dac_reset_out(dac_reset),
  215. .msu_addr_out(msu_write_addr),
  216. .MSU_STATUS(msu_status_out),
  217. .msu_status_reset_out(msu_status_reset_bits),
  218. .msu_status_set_out(msu_status_set_bits),
  219. .msu_status_reset_we(msu_status_reset_we),
  220. .msu_volumerq(msu_volumerq_out),
  221. .msu_addressrq(msu_addressrq_out),
  222. .msu_trackrq(msu_trackrq_out),
  223. .msu_ptr_out(msu_ptr_addr),
  224. .msu_reset_out(msu_addr_reset),
  225. .mcu_rrq(MCU_RRQ),
  226. .mcu_wrq(MCU_WRQ),
  227. .mcu_rq_rdy(MCU_RDY),
  228. .use_msu1(use_msu1),
  229. .cx4_datrom_addr_out(cx4_datrom_addr),
  230. .cx4_datrom_data_out(cx4_datrom_data),
  231. .cx4_datrom_we_out(cx4_datrom_we),
  232. .cx4_reset_out(cx4_reset),
  233. .region_out(mcu_region)
  234. );
  235. wire [7:0] DCM_STATUS;
  236. // dcm1: dfs 4x
  237. my_dcm snes_dcm(
  238. .CLKIN(CLKIN),
  239. .CLKFX(CLK2),
  240. .LOCKED(DCM_LOCKED),
  241. .RST(DCM_RST),
  242. .STATUS(DCM_STATUS)
  243. );
  244. assign DCM_RST=0;
  245. reg [7:0] SNES_PARDr;
  246. reg [7:0] SNES_PAWRr;
  247. reg [7:0] SNES_READr;
  248. reg [7:0] SNES_WRITEr;
  249. reg [7:0] SNES_CPU_CLKr;
  250. wire SNES_FAKE_CLK = &SNES_CPU_CLKr[2:1];
  251. //wire SNES_FAKE_CLK = ~(SNES_READ & SNES_WRITE);
  252. reg SNES_DEADr;
  253. initial SNES_DEADr = 0;
  254. wire SNES_PARD_start = (SNES_PARDr[7:1] == 7'b1111110);
  255. wire SNES_PAWR_start = (SNES_PAWRr[7:1] == 7'b0000001);
  256. wire SNES_RD_start = (SNES_READr[7:1] == 7'b1111110);
  257. wire SNES_WR_start = (SNES_WRITEr[7:1] == 7'b1111110);
  258. wire SNES_WR_end = (SNES_WRITEr[7:1] == 7'b0000001);
  259. wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000001);
  260. wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b111110);
  261. always @(posedge CLK2) begin
  262. SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD};
  263. end
  264. always @(posedge CLK2) begin
  265. SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR};
  266. SNES_READr <= {SNES_READr[6:0], SNES_READ};
  267. SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE};
  268. SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK};
  269. end
  270. address snes_addr(
  271. .CLK(CLK2),
  272. .MAPPER(MAPPER),
  273. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  274. .SNES_PA(SNES_PA),
  275. .SNES_CS(SNES_CS),
  276. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  277. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  278. .IS_SAVERAM(IS_SAVERAM),
  279. .IS_ROM(IS_ROM),
  280. .IS_WRITABLE(IS_WRITABLE),
  281. .SAVERAM_MASK(SAVERAM_MASK),
  282. .ROM_MASK(ROM_MASK),
  283. .use_msu1(use_msu1),
  284. //MSU-1
  285. .msu_enable(msu_enable),
  286. //CX4
  287. .cx4_enable(cx4_enable),
  288. .cx4_vect_enable(cx4_vect_enable),
  289. //region
  290. .r213f_enable(r213f_enable),
  291. //CMD Interface
  292. .snescmd_rd_enable(snescmd_rd_enable),
  293. .snescmd_wr_enable(snescmd_wr_enable)
  294. );
  295. reg [7:0] CX4_DINr;
  296. wire [23:0] CX4_ADDR;
  297. cx4 snes_cx4 (
  298. .DI(CX4_SNES_DATA_IN),
  299. .DO(CX4_SNES_DATA_OUT),
  300. .ADDR(SNES_ADDR[12:0]),
  301. .CS(cx4_enable),
  302. .SNES_VECT_EN(cx4_vect_enable),
  303. .nRD(SNES_READ),
  304. .nWR(SNES_WRITE),
  305. .CLK(CLK2),
  306. .DATROM_DI(cx4_datrom_data),
  307. .DATROM_WE(cx4_datrom_we),
  308. .DATROM_ADDR(cx4_datrom_addr),
  309. .BUS_DI(CX4_DINr),
  310. .BUS_ADDR(CX4_ADDR),
  311. .BUS_RRQ(CX4_RRQ),
  312. .BUS_RDY(CX4_RDY),
  313. .cx4_active(cx4_active)
  314. );
  315. parameter MODE_SNES = 1'b0;
  316. parameter MODE_MCU = 1'b1;
  317. parameter ST_IDLE = 21'b000000000000000000001;
  318. parameter ST_SNES_RD_ADDR = 21'b000000000000000000010;
  319. parameter ST_SNES_RD_WAIT = 21'b000000000000000000100;
  320. parameter ST_SNES_RD_END = 21'b000000000000000001000;
  321. parameter ST_SNES_WR_ADDR = 21'b000000000000000010000;
  322. parameter ST_SNES_WR_WAIT1= 21'b000000000000000100000;
  323. parameter ST_SNES_WR_DATA = 21'b000000000000001000000;
  324. parameter ST_SNES_WR_WAIT2= 21'b000000000000010000000;
  325. parameter ST_SNES_WR_END = 21'b000000000000100000000;
  326. parameter ST_MCU_RD_ADDR = 21'b000000000001000000000;
  327. parameter ST_MCU_RD_WAIT = 21'b000000000010000000000;
  328. parameter ST_MCU_RD_WAIT2 = 21'b000000000100000000000;
  329. parameter ST_MCU_RD_END = 21'b000000001000000000000;
  330. parameter ST_MCU_WR_ADDR = 21'b000000010000000000000;
  331. parameter ST_MCU_WR_WAIT = 21'b000000100000000000000;
  332. parameter ST_MCU_WR_WAIT2 = 21'b000001000000000000000;
  333. parameter ST_MCU_WR_END = 21'b000010000000000000000;
  334. parameter ST_CX4_RD_ADDR = 21'b000100000000000000000;
  335. parameter ST_CX4_RD_WAIT = 21'b001000000000000000000;
  336. parameter ST_CX4_RD_END = 21'b010000000000000000000;
  337. parameter ROM_RD_WAIT = 4'h1;
  338. parameter ROM_RD_WAIT_MCU = 4'h6;
  339. parameter ROM_WR_WAIT = 4'h4;
  340. parameter ROM_WR_WAIT1 = 4'h3;
  341. parameter ROM_WR_WAIT2 = 4'h1;
  342. parameter ROM_WR_WAIT_MCU = 4'h5;
  343. parameter ROM_RD_WAIT_CX4 = 4'h7;
  344. parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
  345. reg [20:0] STATE;
  346. initial STATE = ST_IDLE;
  347. reg [7:0] SNES_DINr;
  348. reg [7:0] SNES_DOUTr;
  349. reg [7:0] ROM_DOUTr;
  350. assign MSU_SNES_DATA_IN = SNES_DATA;
  351. assign CX4_SNES_DATA_IN = SNES_DATA;
  352. reg [7:0] r213fr;
  353. reg r213f_forceread;
  354. reg [2:0] r213f_delay;
  355. reg [1:0] r213f_state;
  356. initial r213fr = 8'h55;
  357. initial r213f_forceread = 0;
  358. initial r213f_state = 2'b01;
  359. initial r213f_delay = 3'b011;
  360. reg[7:0] snescmd_regs[15:0];
  361. assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
  362. :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
  363. :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
  364. ? (msu_enable ? MSU_SNES_DATA_OUT
  365. :cx4_enable ? CX4_SNES_DATA_OUT
  366. :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
  367. :SNES_DOUTr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
  368. reg [3:0] ST_MEM_DELAYr;
  369. reg MCU_RD_PENDr;
  370. reg MCU_WR_PENDr;
  371. reg CX4_RD_PENDr;
  372. reg [23:0] ROM_ADDRr;
  373. reg NEED_SNES_ADDRr;
  374. always @(posedge CLK2) begin
  375. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  376. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  377. end
  378. wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE;
  379. reg RQ_MCU_RDYr;
  380. initial RQ_MCU_RDYr = 1'b1;
  381. assign MCU_RDY = RQ_MCU_RDYr;
  382. reg RQ_CX4_RDYr;
  383. initial RQ_CX4_RDYr = 1'b1;
  384. assign CX4_RDY = RQ_CX4_RDYr;
  385. reg ROM_SAr;
  386. initial ROM_SAr = 1'b1;
  387. wire ROM_SA = ROM_SAr;
  388. reg ROM_CAr;
  389. initial ROM_CAr = 1'b0;
  390. wire ROM_CA = ROM_CAr;
  391. reg [23:0] CX4_ADDRr;
  392. assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : ROM_CA ? CX4_ADDRr[23:1] : ROM_SA ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
  393. assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : ROM_CA ? CX4_ADDRr[0] : ROM_SA ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  394. reg ROM_WEr;
  395. initial ROM_WEr = 1'b1;
  396. reg ROM_DOUT_ENr;
  397. initial ROM_DOUT_ENr = 1'b0;
  398. reg[17:0] SNES_DEAD_CNTr;
  399. initial SNES_DEAD_CNTr = 0;
  400. always @(posedge CLK2) begin
  401. if(cx4_active) begin
  402. if(CX4_RRQ) begin
  403. CX4_RD_PENDr <= 1'b1;
  404. RQ_CX4_RDYr <= 1'b0;
  405. CX4_ADDRr <= CX4_ADDR;
  406. end else if(STATE == ST_CX4_RD_END) begin
  407. CX4_RD_PENDr <= 1'b0;
  408. RQ_CX4_RDYr <= 1'b1;
  409. end
  410. end else begin
  411. CX4_RD_PENDr <= 1'b0;
  412. RQ_CX4_RDYr <= 1'b1;
  413. end
  414. end
  415. always @(posedge CLK2) begin
  416. if(MCU_RRQ) begin
  417. MCU_RD_PENDr <= 1'b1;
  418. RQ_MCU_RDYr <= 1'b0;
  419. ROM_ADDRr <= MCU_ADDR;
  420. end else if(MCU_WRQ) begin
  421. MCU_WR_PENDr <= 1'b1;
  422. RQ_MCU_RDYr <= 1'b0;
  423. ROM_ADDRr <= MCU_ADDR;
  424. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  425. MCU_RD_PENDr <= 1'b0;
  426. MCU_WR_PENDr <= 1'b0;
  427. RQ_MCU_RDYr <= 1'b1;
  428. end
  429. end
  430. always @(posedge CLK2) begin
  431. if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
  432. else SNES_DEAD_CNTr <= 17'h0;
  433. end
  434. always @(posedge CLK2) begin
  435. if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
  436. else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
  437. end
  438. always @(posedge CLK2) begin
  439. if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
  440. else
  441. case(STATE)
  442. ST_IDLE: begin
  443. ROM_SAr <= 1'b1;
  444. ROM_CAr <= 1'b0;
  445. ROM_DOUT_ENr <= 1'b0;
  446. if(cx4_active) begin
  447. if(CX4_RD_PENDr) STATE <= ST_CX4_RD_ADDR;
  448. end else if(SNES_cycle_start & ~SNES_WRITE) begin
  449. STATE <= ST_SNES_WR_ADDR;
  450. if(IS_SAVERAM | IS_WRITABLE) begin
  451. ROM_WEr <= 1'b0;
  452. ROM_DOUT_ENr <= 1'b1;
  453. end
  454. end else if(SNES_cycle_start) begin
  455. STATE <= ST_SNES_RD_ADDR;
  456. // STATE <= ST_SNES_RD_END;
  457. end else if(SNES_DEADr & MCU_RD_PENDr) begin
  458. STATE <= ST_MCU_RD_ADDR;
  459. end else if(SNES_DEADr & MCU_WR_PENDr) begin
  460. STATE <= ST_MCU_WR_ADDR;
  461. end
  462. end
  463. ST_SNES_RD_ADDR: begin
  464. ST_MEM_DELAYr <= ROM_RD_WAIT;
  465. STATE <= ST_SNES_RD_WAIT;
  466. end
  467. ST_SNES_RD_WAIT: begin
  468. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  469. if(ST_MEM_DELAYr == 0) begin
  470. STATE <= ST_SNES_RD_END;
  471. SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
  472. end
  473. else STATE <= ST_SNES_RD_WAIT;
  474. end
  475. ST_SNES_WR_ADDR: begin
  476. ROM_DOUT_ENr <= 1'b1;
  477. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  478. STATE <= ST_SNES_WR_WAIT1;
  479. end
  480. ST_SNES_WR_WAIT1: begin
  481. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  482. if(ST_MEM_DELAYr == 0) begin
  483. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  484. STATE <= ST_SNES_WR_WAIT2;
  485. ROM_DOUTr <= SNES_DATA;
  486. end
  487. else STATE <= ST_SNES_WR_WAIT1;
  488. end
  489. ST_SNES_WR_WAIT2: begin
  490. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  491. if(ST_MEM_DELAYr == 0) begin
  492. STATE <= ST_SNES_WR_END;
  493. ROM_WEr <= 1'b1;
  494. end
  495. else STATE <= ST_SNES_WR_WAIT2;
  496. end
  497. ST_SNES_RD_END, ST_SNES_WR_END: begin
  498. // ROM_DOUT_ENr <= 1'b0;
  499. if(MCU_RD_PENDr) begin
  500. STATE <= ST_MCU_RD_ADDR;
  501. end else if(MCU_WR_PENDr) begin
  502. STATE <= ST_MCU_WR_ADDR;
  503. end else STATE <= ST_IDLE;
  504. end
  505. ST_MCU_RD_ADDR: begin
  506. ROM_SAr <= 1'b0;
  507. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  508. STATE <= ST_MCU_RD_WAIT;
  509. end
  510. ST_MCU_RD_WAIT: begin
  511. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  512. if(ST_MEM_DELAYr == 0) begin
  513. STATE <= ST_MCU_RD_END;
  514. end
  515. else STATE <= ST_MCU_RD_WAIT;
  516. end
  517. ST_MCU_RD_END: begin
  518. MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
  519. STATE <= ST_IDLE;
  520. end
  521. ST_MCU_WR_ADDR: begin
  522. ROM_DOUTr <= MCU_DOUT;
  523. ROM_SAr <= 1'b0;
  524. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  525. STATE <= ST_MCU_WR_WAIT;
  526. ROM_WEr <= 1'b0;
  527. end
  528. ST_MCU_WR_WAIT: begin
  529. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  530. ROM_DOUT_ENr <= 1'b1;
  531. if(ST_MEM_DELAYr == 0) begin
  532. ROM_WEr <= 1'b1;
  533. STATE <= ST_MCU_WR_END;
  534. end
  535. else STATE <= ST_MCU_WR_WAIT;
  536. end
  537. ST_MCU_WR_END: begin
  538. ROM_DOUT_ENr <= 1'b0;
  539. STATE <= ST_IDLE;
  540. end
  541. ST_CX4_RD_ADDR: begin
  542. ROM_CAr <= 1'b1;
  543. ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
  544. STATE <= ST_CX4_RD_WAIT;
  545. end
  546. ST_CX4_RD_WAIT: begin
  547. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  548. if(ST_MEM_DELAYr == 0) begin
  549. CX4_DINr <= CX4_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
  550. STATE <= ST_CX4_RD_END;
  551. end
  552. else STATE <= ST_CX4_RD_WAIT;
  553. end
  554. ST_CX4_RD_END: begin
  555. ROM_CAr <= 1'b0;
  556. STATE <= ST_IDLE;
  557. end
  558. endcase
  559. end
  560. always @(posedge CLK2) begin
  561. if(SNES_cycle_end) r213f_forceread <= 1'b1;
  562. else if(SNES_PARD_start & r213f_enable) begin
  563. r213f_delay <= 3'b000;
  564. r213f_state <= 2'b10;
  565. end else if(r213f_state == 2'b10) begin
  566. r213f_delay <= r213f_delay - 1;
  567. if(r213f_delay == 3'b000) begin
  568. r213f_forceread <= 1'b0;
  569. r213f_state <= 2'b01;
  570. r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
  571. end
  572. end
  573. end
  574. always @(posedge CLK2) begin
  575. if(SNES_WR_end & snescmd_wr_enable) begin
  576. snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
  577. end
  578. end
  579. reg ROM_WE_1;
  580. reg MCU_WRITE_1;
  581. always @(posedge CLK2) begin
  582. ROM_WE_1 <= ROM_WE;
  583. MCU_WRITE_1<= MCU_WRITE;
  584. end
  585. assign ROM_DATA[7:0] = ROM_ADDR0
  586. ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  587. /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
  588. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
  589. )
  590. :8'bZ;
  591. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  592. :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  593. /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
  594. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
  595. );
  596. assign ROM_WE = SD_DMA_TO_ROM
  597. ?MCU_WRITE
  598. :/*(SNES_FAKE_CLK & (IS_WRITABLE | IS_FLASHWR)) ? SNES_WRITE :*/ ROM_WEr;
  599. // OE always active. Overridden by WE when needed.
  600. assign ROM_OE = 1'b0;
  601. assign ROM_CE = 1'b0;
  602. assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
  603. assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
  604. assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
  605. cx4_enable ? 1'b0 :
  606. (cx4_active & cx4_vect_enable) ? 1'b0 :
  607. r213f_enable & !SNES_PARD ? 1'b0 :
  608. (snescmd_wr_enable | snescmd_rd_enable) & !SNES_PARD ? 1'b0 :
  609. ((IS_ROM & SNES_CS)
  610. |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
  611. |(SNES_READr[0] & SNES_WRITEr[0])
  612. );
  613. assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
  614. ? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
  615. : 1'b0;
  616. assign SNES_IRQ = 1'b0;
  617. assign p113_out = 1'b0;
  618. /*
  619. wire [35:0] CONTROL0;
  620. icon icon (
  621. .CONTROL0(CONTROL0) // INOUT BUS [35:0]
  622. );
  623. ila ila (
  624. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  625. .CLK(CLK2), // IN
  626. .TRIG0(SNES_ADDR), // IN BUS [23:0]
  627. .TRIG1(SNES_DATA), // IN BUS [7:0]
  628. .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, cx4_active, ROM_WE, ROM_DOUT_ENr, ROM_SA, CX4_RRQ, CX4_RDY, ROM_CA}), // IN BUS [15:0]
  629. .TRIG3(ROM_ADDRr), // IN BUS [23:0]
  630. .TRIG4(CX4_ADDRr), // IN BUS [23:0]
  631. .TRIG5(ROM_DATA), // IN BUS [15:0]
  632. .TRIG6(CX4_DINr), // IN BUS [7:0]
  633. .TRIG7(STATE) // IN BUS [21:0]
  634. );*/
  635. /*
  636. ila ila (
  637. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  638. .CLK(CLK2), // IN
  639. .TRIG0(SNES_ADDR), // IN BUS [23:0]
  640. .TRIG1(SNES_DATA), // IN BUS [7:0]
  641. .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
  642. .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
  643. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  644. .TRIG5(ROM_DATA), // IN BUS [15:0]
  645. .TRIG6(MCU_DINr), // IN BUS [7:0]
  646. .TRIG7(spi_byte_cnt[3:0])
  647. );
  648. */
  649. /*
  650. ila_srtc ila (
  651. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  652. .CLK(CLK2), // IN
  653. .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
  654. .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
  655. .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
  656. .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
  657. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  658. .TRIG5(ROM_DATA), // IN BUS [15:0]
  659. .TRIG6(MCU_DINr), // IN BUS [7:0]
  660. .TRIG7(ST_MEM_DELAYr)
  661. );
  662. */
  663. endmodule