main.v 22 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR_IN,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. output SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. input SNES_SYSCLK,
  36. input [7:0] SNES_PA,
  37. input SNES_PARD,
  38. input SNES_PAWR,
  39. /* SRAM signals */
  40. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  41. inout [15:0] ROM_DATA,
  42. output [22:0] ROM_ADDR,
  43. output ROM_CE,
  44. output ROM_OE,
  45. output ROM_WE,
  46. output ROM_BHE,
  47. output ROM_BLE,
  48. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  49. inout [7:0] RAM_DATA,
  50. output [18:0] RAM_ADDR,
  51. output RAM_CE,
  52. output RAM_OE,
  53. output RAM_WE,
  54. /* MCU signals */
  55. input SPI_MOSI,
  56. inout SPI_MISO,
  57. input SPI_SS,
  58. inout SPI_SCK,
  59. input MCU_OVR,
  60. output MCU_RDY,
  61. output DAC_MCLK,
  62. output DAC_LRCK,
  63. output DAC_SDOUT,
  64. /* SD signals */
  65. input [3:0] SD_DAT,
  66. inout SD_CMD,
  67. inout SD_CLK,
  68. /* debug */
  69. output p113_out
  70. );
  71. wire CLK2;
  72. reg [23:0] SNES_ADDR_r [2:0];
  73. always @(posedge CLK2) begin
  74. SNES_ADDR_r[2] <= SNES_ADDR_r[1];
  75. SNES_ADDR_r[1] <= SNES_ADDR_r[0];
  76. SNES_ADDR_r[0] <= SNES_ADDR_IN;
  77. end
  78. wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
  79. wire dspx_dp_enable;
  80. wire [7:0] spi_cmd_data;
  81. wire [7:0] spi_param_data;
  82. wire [7:0] spi_input_data;
  83. wire [31:0] spi_byte_cnt;
  84. wire [2:0] spi_bit_cnt;
  85. wire [23:0] MCU_ADDR;
  86. wire [2:0] MAPPER;
  87. wire [23:0] SAVERAM_MASK;
  88. wire [23:0] ROM_MASK;
  89. wire [7:0] SD_DMA_SRAM_DATA;
  90. wire [1:0] SD_DMA_TGT;
  91. wire [10:0] SD_DMA_PARTIAL_START;
  92. wire [10:0] SD_DMA_PARTIAL_END;
  93. wire [10:0] dac_addr;
  94. //wire [7:0] dac_volume;
  95. wire [7:0] msu_volumerq_out;
  96. wire [6:0] msu_status_out;
  97. wire [31:0] msu_addressrq_out;
  98. wire [15:0] msu_trackrq_out;
  99. wire [13:0] msu_write_addr;
  100. wire [13:0] msu_ptr_addr;
  101. wire [7:0] MSU_SNES_DATA_IN;
  102. wire [7:0] MSU_SNES_DATA_OUT;
  103. wire [5:0] msu_status_reset_bits;
  104. wire [5:0] msu_status_set_bits;
  105. wire [14:0] bsx_regs;
  106. wire [7:0] BSX_SNES_DATA_IN;
  107. wire [7:0] BSX_SNES_DATA_OUT;
  108. wire [7:0] bsx_regs_reset_bits;
  109. wire [7:0] bsx_regs_set_bits;
  110. wire [59:0] rtc_data;
  111. wire [55:0] rtc_data_in;
  112. wire [59:0] srtc_rtc_data_out;
  113. wire [3:0] SRTC_SNES_DATA_IN;
  114. wire [7:0] SRTC_SNES_DATA_OUT;
  115. wire [7:0] DSPX_SNES_DATA_IN;
  116. wire [7:0] DSPX_SNES_DATA_OUT;
  117. wire [23:0] dspx_pgm_data;
  118. wire [10:0] dspx_pgm_addr;
  119. wire dspx_pgm_we;
  120. wire [15:0] dspx_dat_data;
  121. wire [10:0] dspx_dat_addr;
  122. wire dspx_dat_we;
  123. wire [7:0] featurebits;
  124. wire [23:0] MAPPED_SNES_ADDR;
  125. wire ROM_ADDR0;
  126. wire [9:0] bs_page;
  127. wire [8:0] bs_page_offset;
  128. wire bs_page_enable;
  129. wire [4:0] DBG_srtc_state;
  130. wire DBG_srtc_we_rising;
  131. wire [3:0] DBG_srtc_ptr;
  132. wire [5:0] DBG_srtc_we_sreg;
  133. wire [13:0] DBG_msu_address;
  134. wire DBG_msu_reg_oe_rising;
  135. wire DBG_msu_reg_oe_falling;
  136. wire DBG_msu_reg_we_rising;
  137. wire [2:0] SD_DMA_DBG_clkcnt;
  138. wire [10:0] SD_DMA_DBG_cyclecnt;
  139. sd_dma snes_sd_dma(
  140. .CLK(CLK2),
  141. .SD_DAT(SD_DAT),
  142. .SD_CLK(SD_CLK),
  143. .SD_DMA_EN(SD_DMA_EN),
  144. .SD_DMA_STATUS(SD_DMA_STATUS),
  145. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  146. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  147. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  148. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  149. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  150. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  151. .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
  152. .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
  153. .DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
  154. .DBG_clkcnt(SD_DMA_DBG_clkcnt)
  155. );
  156. wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
  157. dac snes_dac(
  158. .clkin(CLK2),
  159. .sysclk(SNES_SYSCLK),
  160. .mclk(DAC_MCLK),
  161. .lrck(DAC_LRCK),
  162. .sdout(DAC_SDOUT),
  163. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  164. .pgm_address(dac_addr),
  165. .pgm_data(SD_DMA_SRAM_DATA),
  166. .DAC_STATUS(DAC_STATUS),
  167. .volume(msu_volumerq_out),
  168. .vol_latch(msu_volume_latch_out),
  169. .play(dac_play),
  170. .reset(dac_reset)
  171. );
  172. srtc snes_srtc (
  173. .clkin(CLK2),
  174. .addr_in(SNES_ADDR[0]),
  175. .data_in(SRTC_SNES_DATA_IN),
  176. .data_out(SRTC_SNES_DATA_OUT),
  177. .rtc_data_in(rtc_data),
  178. .reg_we(SNES_WRITE),
  179. .reg_oe(SNES_READ),
  180. .enable(srtc_enable),
  181. .rtc_data_out(srtc_rtc_data_out),
  182. .rtc_we(srtc_rtc_we),
  183. .reset(srtc_reset),
  184. .srtc_state(DBG_srtc_state),
  185. .srtc_reg_we_rising(DBG_srtc_we_rising),
  186. .srtc_rtc_ptr(DBG_srtc_ptr),
  187. .srtc_we_sreg(DBG_srtc_we_sreg)
  188. );
  189. rtc snes_rtc (
  190. .clkin(CLKIN),
  191. .rtc_data(rtc_data),
  192. .rtc_data_in(rtc_data_in),
  193. .pgm_we(rtc_pgm_we),
  194. .rtc_data_in1(srtc_rtc_data_out),
  195. .we1(srtc_rtc_we)
  196. );
  197. msu snes_msu (
  198. .clkin(CLK2),
  199. .enable(msu_enable),
  200. .pgm_address(msu_write_addr),
  201. .pgm_data(SD_DMA_SRAM_DATA),
  202. .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
  203. .reg_addr(SNES_ADDR[2:0]),
  204. .reg_data_in(MSU_SNES_DATA_IN),
  205. .reg_data_out(MSU_SNES_DATA_OUT),
  206. .reg_oe(SNES_READ),
  207. .reg_we(SNES_WRITE),
  208. .status_out(msu_status_out),
  209. .volume_out(msu_volumerq_out),
  210. .volume_latch_out(msu_volume_latch_out),
  211. .addr_out(msu_addressrq_out),
  212. .track_out(msu_trackrq_out),
  213. .status_reset_bits(msu_status_reset_bits),
  214. .status_set_bits(msu_status_set_bits),
  215. .status_reset_we(msu_status_reset_we),
  216. .msu_address_ext(msu_ptr_addr),
  217. .msu_address_ext_write(msu_addr_reset),
  218. .DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
  219. .DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
  220. .DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
  221. .DBG_msu_address(DBG_msu_address),
  222. .DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
  223. );
  224. bsx snes_bsx(
  225. .clkin(CLK2),
  226. .use_bsx(use_bsx),
  227. .pgm_we(bsx_regs_reset_we),
  228. .snes_addr(SNES_ADDR),
  229. .reg_data_in(BSX_SNES_DATA_IN),
  230. .reg_data_out(BSX_SNES_DATA_OUT),
  231. .reg_oe(SNES_READ),
  232. .reg_we(SNES_WRITE),
  233. .regs_out(bsx_regs),
  234. .reg_reset_bits(bsx_regs_reset_bits),
  235. .reg_set_bits(bsx_regs_set_bits),
  236. .data_ovr(bsx_data_ovr),
  237. .flash_writable(IS_FLASHWR),
  238. .rtc_data(rtc_data[59:0]),
  239. .bs_page_out(bs_page), // support only page 0000-03ff
  240. .bs_page_enable(bs_page_enable),
  241. .bs_page_offset(bs_page_offset)
  242. );
  243. spi snes_spi(
  244. .clk(CLK2),
  245. .MOSI(SPI_MOSI),
  246. .MISO(SPI_MISO),
  247. .SSEL(SPI_SS),
  248. .SCK(SPI_SCK),
  249. .cmd_ready(spi_cmd_ready),
  250. .param_ready(spi_param_ready),
  251. .cmd_data(spi_cmd_data),
  252. .param_data(spi_param_data),
  253. .endmessage(spi_endmessage),
  254. .startmessage(spi_startmessage),
  255. .input_data(spi_input_data),
  256. .byte_cnt(spi_byte_cnt),
  257. .bit_cnt(spi_bit_cnt)
  258. );
  259. upd77c25 snes_dspx (
  260. .DI(DSPX_SNES_DATA_IN),
  261. .DO(DSPX_SNES_DATA_OUT),
  262. .A0(DSPX_A0),
  263. .nCS(~dspx_enable),
  264. .nRD(SNES_READ),
  265. .nWR(SNES_WRITE),
  266. .RST(~dspx_reset),
  267. .CLK(CLK2),
  268. .PGM_WR(dspx_pgm_we),
  269. .PGM_DI(dspx_pgm_data),
  270. .PGM_WR_ADDR(dspx_pgm_addr),
  271. .DAT_WR(dspx_dat_we),
  272. .DAT_DI(dspx_dat_data),
  273. .DAT_WR_ADDR(dspx_dat_addr),
  274. .DP_nCS(~dspx_dp_enable),
  275. .DP_ADDR(SNES_ADDR[10:0])
  276. );
  277. reg [7:0] MCU_DINr;
  278. wire [7:0] MCU_DOUT;
  279. mcu_cmd snes_mcu_cmd(
  280. .clk(CLK2),
  281. .snes_sysclk(SNES_SYSCLK),
  282. .cmd_ready(spi_cmd_ready),
  283. .param_ready(spi_param_ready),
  284. .cmd_data(spi_cmd_data),
  285. .param_data(spi_param_data),
  286. .mcu_mapper(MAPPER),
  287. .mcu_write(MCU_WRITE),
  288. .mcu_data_in(MCU_DINr),
  289. .mcu_data_out(MCU_DOUT),
  290. .spi_byte_cnt(spi_byte_cnt),
  291. .spi_bit_cnt(spi_bit_cnt),
  292. .spi_data_out(spi_input_data),
  293. .addr_out(MCU_ADDR),
  294. .saveram_mask_out(SAVERAM_MASK),
  295. .rom_mask_out(ROM_MASK),
  296. .SD_DMA_EN(SD_DMA_EN),
  297. .SD_DMA_STATUS(SD_DMA_STATUS),
  298. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  299. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  300. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  301. .SD_DMA_TGT(SD_DMA_TGT),
  302. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  303. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  304. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  305. .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
  306. .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
  307. .dac_addr_out(dac_addr),
  308. .DAC_STATUS(DAC_STATUS),
  309. // .dac_volume_out(dac_volume),
  310. // .dac_volume_latch_out(dac_vol_latch),
  311. .dac_play_out(dac_play),
  312. .dac_reset_out(dac_reset),
  313. .msu_addr_out(msu_write_addr),
  314. .MSU_STATUS(msu_status_out),
  315. .msu_status_reset_out(msu_status_reset_bits),
  316. .msu_status_set_out(msu_status_set_bits),
  317. .msu_status_reset_we(msu_status_reset_we),
  318. .msu_volumerq(msu_volumerq_out),
  319. .msu_addressrq(msu_addressrq_out),
  320. .msu_trackrq(msu_trackrq_out),
  321. .msu_ptr_out(msu_ptr_addr),
  322. .msu_reset_out(msu_addr_reset),
  323. .bsx_regs_set_out(bsx_regs_set_bits),
  324. .bsx_regs_reset_out(bsx_regs_reset_bits),
  325. .bsx_regs_reset_we(bsx_regs_reset_we),
  326. .rtc_data_out(rtc_data_in),
  327. .rtc_pgm_we(rtc_pgm_we),
  328. .srtc_reset(srtc_reset),
  329. .dspx_pgm_data_out(dspx_pgm_data),
  330. .dspx_pgm_addr_out(dspx_pgm_addr),
  331. .dspx_pgm_we_out(dspx_pgm_we),
  332. .dspx_dat_data_out(dspx_dat_data),
  333. .dspx_dat_addr_out(dspx_dat_addr),
  334. .dspx_dat_we_out(dspx_dat_we),
  335. .dspx_reset_out(dspx_reset),
  336. .featurebits_out(featurebits),
  337. .mcu_rrq(MCU_RRQ),
  338. .mcu_wrq(MCU_WRQ),
  339. .mcu_rq_rdy(MCU_RDY),
  340. .region_out(mcu_region),
  341. .DBG_mcu_nextaddr(DBG_mcu_nextaddr)
  342. );
  343. wire [7:0] DCM_STATUS;
  344. // dcm1: dfs 4x
  345. my_dcm snes_dcm(
  346. .CLKIN(CLKIN),
  347. .CLKFX(CLK2),
  348. .LOCKED(DCM_LOCKED),
  349. .RST(DCM_RST),
  350. .STATUS(DCM_STATUS)
  351. );
  352. assign DCM_RST=0;
  353. reg [7:0] SNES_PARDr;
  354. reg [7:0] SNES_PAWRr;
  355. reg [7:0] SNES_READr;
  356. reg [7:0] SNES_WRITEr;
  357. reg [7:0] SNES_CPU_CLKr;
  358. wire SNES_FAKE_CLK = &SNES_CPU_CLKr[2:1];
  359. //wire SNES_FAKE_CLK = ~(SNES_READ & SNES_WRITE);
  360. reg SNES_DEADr;
  361. initial SNES_DEADr = 0;
  362. wire SNES_PARD_start = (SNES_PARDr[7:1] == 7'b1111110);
  363. wire SNES_PAWR_start = (SNES_PAWRr[7:1] == 7'b0000001);
  364. wire SNES_RD_start = (SNES_READr[7:1] == 7'b1111110);
  365. wire SNES_WR_start = (SNES_WRITEr[7:1] == 7'b1111110);
  366. wire SNES_WR_end = (SNES_WRITEr[7:1] == 7'b0000001);
  367. wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000001);
  368. wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b111110);
  369. always @(posedge CLK2) begin
  370. SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD};
  371. end
  372. always @(posedge CLK2) begin
  373. SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR};
  374. SNES_READr <= {SNES_READr[6:0], SNES_READ};
  375. SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE};
  376. SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK};
  377. end
  378. address snes_addr(
  379. .CLK(CLK2),
  380. .MAPPER(MAPPER),
  381. .featurebits(featurebits),
  382. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  383. .SNES_PA(SNES_PA),
  384. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  385. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  386. .IS_SAVERAM(IS_SAVERAM),
  387. .IS_ROM(IS_ROM),
  388. .IS_WRITABLE(IS_WRITABLE),
  389. .SAVERAM_MASK(SAVERAM_MASK),
  390. .ROM_MASK(ROM_MASK),
  391. //MSU-1
  392. .msu_enable(msu_enable),
  393. //BS-X
  394. .use_bsx(use_bsx),
  395. .bsx_regs(bsx_regs),
  396. .bs_page_offset(bs_page_offset),
  397. .bs_page(bs_page),
  398. .bs_page_enable(bs_page_enable),
  399. .bsx_tristate(bsx_tristate),
  400. //SRTC
  401. .srtc_enable(srtc_enable),
  402. //uPD77C25
  403. .dspx_enable(dspx_enable),
  404. .dspx_dp_enable(dspx_dp_enable),
  405. .dspx_a0(DSPX_A0),
  406. .r213f_enable(r213f_enable),
  407. .snescmd_rd_enable(snescmd_rd_enable),
  408. .snescmd_wr_enable(snescmd_wr_enable)
  409. );
  410. parameter MODE_SNES = 1'b0;
  411. parameter MODE_MCU = 1'b1;
  412. parameter ST_IDLE = 18'b000000000000000001;
  413. parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
  414. parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
  415. parameter ST_SNES_RD_END = 18'b000000000000001000;
  416. parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
  417. parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
  418. parameter ST_SNES_WR_DATA = 18'b000000000001000000;
  419. parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
  420. parameter ST_SNES_WR_END = 18'b000000000100000000;
  421. parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
  422. parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
  423. parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
  424. parameter ST_MCU_RD_END = 18'b000001000000000000;
  425. parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
  426. parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
  427. parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
  428. parameter ST_MCU_WR_END = 18'b010000000000000000;
  429. parameter ROM_RD_WAIT = 4'h1;
  430. parameter ROM_RD_WAIT_MCU = 4'h6;
  431. parameter ROM_WR_WAIT = 4'h4;
  432. parameter ROM_WR_WAIT1 = 4'h3;
  433. parameter ROM_WR_WAIT2 = 4'h1;
  434. parameter ROM_WR_WAIT_MCU = 4'h5;
  435. parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
  436. reg [17:0] STATE;
  437. initial STATE = ST_IDLE;
  438. reg [7:0] SNES_DINr;
  439. reg [7:0] SNES_DOUTr;
  440. reg [7:0] ROM_DOUTr;
  441. assign DSPX_SNES_DATA_IN = SNES_DATA;
  442. assign SRTC_SNES_DATA_IN = SNES_DATA[3:0];
  443. assign MSU_SNES_DATA_IN = SNES_DATA;
  444. assign BSX_SNES_DATA_IN = SNES_DATA;
  445. reg [7:0] r213fr;
  446. reg r213f_forceread;
  447. reg [2:0] r213f_delay;
  448. reg [1:0] r213f_state;
  449. initial r213fr = 8'h55;
  450. initial r213f_forceread = 0;
  451. initial r213f_state = 2'b01;
  452. initial r213f_delay = 3'b011;
  453. reg[7:0] snescmd_regs[15:0];
  454. assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
  455. :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
  456. :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
  457. ? (srtc_enable ? SRTC_SNES_DATA_OUT
  458. :dspx_enable ? DSPX_SNES_DATA_OUT
  459. :dspx_dp_enable ? DSPX_SNES_DATA_OUT
  460. :msu_enable ? MSU_SNES_DATA_OUT
  461. :bsx_data_ovr ? BSX_SNES_DATA_OUT
  462. :SNES_DOUTr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
  463. reg [3:0] ST_MEM_DELAYr;
  464. reg MCU_RD_PENDr;
  465. reg MCU_WR_PENDr;
  466. reg [23:0] ROM_ADDRr;
  467. reg NEED_SNES_ADDRr;
  468. always @(posedge CLK2) begin
  469. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  470. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  471. end
  472. reg RQ_MCU_RDYr;
  473. initial RQ_MCU_RDYr = 1'b1;
  474. assign MCU_RDY = RQ_MCU_RDYr;
  475. reg ROM_SAr;
  476. initial ROM_SAr = 1'b1;
  477. //wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
  478. wire ROM_SA = ROM_SAr;
  479. //assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
  480. //assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  481. //WARNING DUE TO BAD SOLDER WE LOST HALF OF THE PSRAM!!!
  482. assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[22:0] : (ROM_SA) ? MAPPED_SNES_ADDR[22:0] : ROM_ADDRr[22:0];
  483. assign ROM_ADDR0 = 1'b0; //(SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  484. reg ROM_WEr;
  485. initial ROM_WEr = 1'b1;
  486. reg ROM_DOUT_ENr;
  487. initial ROM_DOUT_ENr = 1'b0;
  488. reg[17:0] SNES_DEAD_CNTr;
  489. initial SNES_DEAD_CNTr = 0;
  490. always @(posedge CLK2) begin
  491. if(MCU_RRQ) begin
  492. MCU_RD_PENDr <= 1'b1;
  493. RQ_MCU_RDYr <= 1'b0;
  494. ROM_ADDRr <= MCU_ADDR;
  495. end else if(MCU_WRQ) begin
  496. MCU_WR_PENDr <= 1'b1;
  497. RQ_MCU_RDYr <= 1'b0;
  498. ROM_ADDRr <= MCU_ADDR;
  499. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  500. MCU_RD_PENDr <= 1'b0;
  501. MCU_WR_PENDr <= 1'b0;
  502. RQ_MCU_RDYr <= 1'b1;
  503. end
  504. end
  505. always @(posedge CLK2) begin
  506. if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
  507. else SNES_DEAD_CNTr <= 17'h0;
  508. end
  509. always @(posedge CLK2) begin
  510. if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
  511. else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
  512. end
  513. reg snes_wr_cycle;
  514. always @(posedge CLK2) begin
  515. if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
  516. else
  517. case(STATE)
  518. ST_IDLE: begin
  519. ROM_SAr <= 1'b1;
  520. ROM_DOUT_ENr <= 1'b0;
  521. if(SNES_cycle_start & ~SNES_WRITE) begin
  522. STATE <= ST_SNES_WR_ADDR;
  523. if(IS_WRITABLE | (IS_FLASHWR & ~bsx_tristate)) begin
  524. ROM_WEr <= 1'b0;
  525. end
  526. end else if(SNES_cycle_start) begin
  527. STATE <= ST_SNES_RD_ADDR;
  528. // STATE <= ST_SNES_RD_END;
  529. end else if(SNES_DEADr & MCU_RD_PENDr) begin
  530. STATE <= ST_MCU_RD_ADDR;
  531. end else if(SNES_DEADr & MCU_WR_PENDr) begin
  532. STATE <= ST_MCU_WR_ADDR;
  533. end
  534. end
  535. ST_SNES_RD_ADDR: begin
  536. ST_MEM_DELAYr <= ROM_RD_WAIT;
  537. STATE <= ST_SNES_RD_WAIT;
  538. end
  539. ST_SNES_RD_WAIT: begin
  540. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  541. if(ST_MEM_DELAYr == 0) begin
  542. STATE <= ST_SNES_RD_END;
  543. SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
  544. end
  545. else STATE <= ST_SNES_RD_WAIT;
  546. end
  547. ST_SNES_WR_ADDR: begin
  548. ROM_DOUT_ENr <= 1'b1;
  549. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  550. STATE <= ST_SNES_WR_WAIT1;
  551. end
  552. ST_SNES_WR_WAIT1: begin
  553. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  554. if(ST_MEM_DELAYr == 0) begin
  555. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  556. STATE <= ST_SNES_WR_WAIT2;
  557. ROM_DOUTr <= SNES_DATA;
  558. end
  559. else STATE <= ST_SNES_WR_WAIT1;
  560. end
  561. ST_SNES_WR_WAIT2: begin
  562. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  563. if(ST_MEM_DELAYr == 0) begin
  564. STATE <= ST_SNES_WR_END;
  565. ROM_WEr <= 1'b1;
  566. ROM_DOUT_ENr <= 1'b0;
  567. end
  568. else STATE <= ST_SNES_WR_WAIT2;
  569. end
  570. ST_SNES_RD_END, ST_SNES_WR_END: begin
  571. // ROM_DOUT_ENr <= 1'b0;
  572. if(MCU_RD_PENDr) begin
  573. STATE <= ST_MCU_RD_ADDR;
  574. end else if(MCU_WR_PENDr) begin
  575. STATE <= ST_MCU_WR_ADDR;
  576. end else STATE <= ST_IDLE;
  577. end
  578. ST_MCU_RD_ADDR: begin
  579. ROM_SAr <= 1'b0;
  580. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  581. STATE <= ST_MCU_RD_WAIT;
  582. end
  583. ST_MCU_RD_WAIT: begin
  584. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  585. if(ST_MEM_DELAYr == 0) begin
  586. STATE <= ST_MCU_RD_END;
  587. end
  588. else STATE <= ST_MCU_RD_WAIT;
  589. end
  590. ST_MCU_RD_END: begin
  591. MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8]; /*ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];*/
  592. STATE <= ST_IDLE;
  593. end
  594. ST_MCU_WR_ADDR: begin
  595. ROM_DOUTr <= MCU_DOUT;
  596. ROM_SAr <= 1'b0;
  597. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  598. STATE <= ST_MCU_WR_WAIT;
  599. ROM_WEr <= 1'b0;
  600. end
  601. ST_MCU_WR_WAIT: begin
  602. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  603. ROM_DOUT_ENr <= 1'b1;
  604. if(ST_MEM_DELAYr == 0) begin
  605. ROM_WEr <= 1'b1;
  606. STATE <= ST_MCU_WR_END;
  607. end
  608. else STATE <= ST_MCU_WR_WAIT;
  609. end
  610. ST_MCU_WR_END: begin
  611. ROM_DOUT_ENr <= 1'b0;
  612. STATE <= ST_IDLE;
  613. end
  614. endcase
  615. end
  616. always @(posedge CLK2) begin
  617. if(SNES_cycle_end) r213f_forceread <= 1'b1;
  618. else if(SNES_PARD_start & r213f_enable) begin
  619. r213f_delay <= 3'b000;
  620. r213f_state <= 2'b10;
  621. end else if(r213f_state == 2'b10) begin
  622. r213f_delay <= r213f_delay - 1;
  623. if(r213f_delay == 3'b000) begin
  624. r213f_forceread <= 1'b0;
  625. r213f_state <= 2'b01;
  626. r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
  627. end
  628. end
  629. end
  630. always @(posedge CLK2) begin
  631. if(SNES_WR_end & snescmd_wr_enable) begin
  632. snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
  633. end
  634. end
  635. reg ROM_WE_1;
  636. reg MCU_WRITE_1;
  637. always @(posedge CLK2) begin
  638. ROM_WE_1 <= ROM_WE;
  639. MCU_WRITE_1<= MCU_WRITE;
  640. end
  641. /*
  642. assign ROM_DATA[7:0] = ROM_ADDR0
  643. ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  644. //: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA
  645. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
  646. )
  647. :8'bZ;
  648. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  649. :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  650. //: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA
  651. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
  652. );
  653. */
  654. assign ROM_DATA[7:0] = SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  655. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
  656. assign ROM_DATA[15:8] = SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  657. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
  658. assign ROM_WE = SD_DMA_TO_ROM
  659. ?MCU_WRITE
  660. :/*(SNES_FAKE_CLK & (IS_WRITABLE | IS_FLASHWR)) ? SNES_WRITE :*/ ROM_WEr;
  661. // OE always active. Overridden by WE when needed.
  662. assign ROM_OE = 1'b0;
  663. assign ROM_CE = 1'b0;
  664. assign ROM_BHE = 1'b0; ///*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
  665. assign ROM_BLE = 1'b0; ///*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
  666. assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
  667. msu_enable ? 1'b0 :
  668. bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
  669. srtc_enable ? (SNES_READ & SNES_WRITE) :
  670. bs_page_enable ? (SNES_READ) :
  671. r213f_enable & !SNES_PARD ? 1'b0 :
  672. (snescmd_wr_enable | snescmd_rd_enable) & !SNES_PARD ? 1'b0 :
  673. ((IS_ROM & SNES_CS)
  674. |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
  675. |(SNES_READr[0] & SNES_WRITEr[0])
  676. | bsx_tristate
  677. );
  678. assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
  679. ? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
  680. : 1'b0;
  681. assign SNES_IRQ = 1'b0;
  682. assign p113_out = 1'b1;
  683. /*
  684. wire [35:0] CONTROL0;
  685. icon icon (
  686. .CONTROL0(CONTROL0) // INOUT BUS [35:0]
  687. );
  688. ila_srtc ila (
  689. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  690. .CLK(CLK2), // IN
  691. .TRIG0(SNES_ADDR), // IN BUS [23:0]
  692. .TRIG1(SNES_DATA), // IN BUS [7:0]
  693. .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
  694. .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
  695. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  696. .TRIG5(ROM_DATA), // IN BUS [15:0]
  697. .TRIG6(MCU_DINr), // IN BUS [7:0]
  698. .TRIG7(spi_byte_cnt[3:0])
  699. );
  700. */
  701. /*
  702. ila_srtc ila (
  703. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  704. .CLK(CLK2), // IN
  705. .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
  706. .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
  707. .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
  708. .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
  709. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  710. .TRIG5(ROM_DATA), // IN BUS [15:0]
  711. .TRIG6(MCU_DINr), // IN BUS [7:0]
  712. .TRIG7(ST_MEM_DELAYr)
  713. );
  714. */
  715. endmodule