address.v 12 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: address
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Address logic w/ SaveRAM masking
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Additional Comments:
  18. //
  19. //////////////////////////////////////////////////////////////////////////////////
  20. module address(
  21. input CLK,
  22. input [7:0] featurebits, // peripheral enable/disable
  23. input [2:0] MAPPER, // MCU detected mapper
  24. input [23:0] SNES_ADDR, // requested address from SNES
  25. input [7:0] SNES_PA, // peripheral address from SNES
  26. output [23:0] ROM_ADDR, // Address to request from SRAM0
  27. output ROM_SEL, // enable SRAM0 (active low)
  28. output IS_SAVERAM, // address/CS mapped as SRAM?
  29. output IS_ROM, // address mapped as ROM?
  30. output IS_WRITABLE, // address somehow mapped as writable area?
  31. input [23:0] SAVERAM_MASK,
  32. input [23:0] ROM_MASK,
  33. output msu_enable,
  34. output srtc_enable,
  35. output use_bsx,
  36. output bsx_tristate,
  37. input [14:0] bsx_regs,
  38. output dspx_enable,
  39. output dspx_dp_enable,
  40. output dspx_a0,
  41. output r213f_enable,
  42. output snescmd_rd_enable,
  43. output snescmd_wr_enable,
  44. input [8:0] bs_page_offset,
  45. input [9:0] bs_page,
  46. input bs_page_enable
  47. );
  48. parameter [2:0]
  49. FEAT_DSPX = 0,
  50. FEAT_ST0010 = 1,
  51. FEAT_SRTC = 2,
  52. FEAT_MSU1 = 3,
  53. FEAT_213F = 4
  54. ;
  55. wire [23:0] SRAM_SNES_ADDR;
  56. /* currently supported mappers:
  57. Index Mapper
  58. 000 HiROM
  59. 001 LoROM
  60. 010 ExHiROM (48-64Mbit)
  61. 011 BS-X
  62. 110 brainfuck interleaved 96MBit Star Ocean =)
  63. 111 menu (ROM in upper SRAM)
  64. */
  65. /* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
  66. Offset 6000-7fff */
  67. assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
  68. |(SNES_ADDR[22]));
  69. /* HiROM SRAM is 8K end at 0x8000 and is at bank 0x20 and 0xA0 */
  70. assign IS_SAVERAM_HIROM = ((SNES_ADDR[22:21] == 2'b01)
  71. & SNES_ADDR[15:13] == 3'b011)
  72. /* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
  73. TODO: 0000-ffff for small ROMs? */
  74. assign IS_SAVERAM_LOROM = SNES_ADDR[22:16] == 7'b111
  75. ( &SNES_ADDR[22:20]
  76. & (SNES_ADDR[19:16] < 4'b1110)
  77. & !SNES_ADDR[15] )
  78. assign IS_SAVERAM_EXHIROM = (!SNES_ADDR[22]
  79. & SNES_ADDR[21]
  80. & &SNES_ADDR[14:13]
  81. & !SNES_ADDR[15])
  82. assign IS_SAVERAM_BSX = ( (SNES_ADDR[23:19] == 5'b00010)
  83. & (SNES_ADDR[15:12] == 4'b0101)
  84. )
  85. assign IS_SAVERAM_STARTOCEAN = (!SNES_ADDR[22]
  86. & SNES_ADDR[21]
  87. & &SNES_ADDR[14:13]
  88. & !SNES_ADDR[15])
  89. assign IS_SAVERAM_MENU = (!SNES_ADDR[22]
  90. & SNES_ADDR[21]
  91. & &SNES_ADDR[14:13]
  92. & !SNES_ADDR[15])
  93. assign IS_SAVERAM = SAVERAM_MASK[0]
  94. &(featurebits[FEAT_ST0010]
  95. ?((SNES_ADDR[22:19] == 4'b1101)
  96. & &(~SNES_ADDR[15:12])
  97. & SNES_ADDR[11])
  98. :(
  99. ( MAPPER == 3'b000
  100. || MAPPER == 3'b010
  101. || MAPPER == 3'b110
  102. || MAPPER == 3'b111)
  103. ? (!SNES_ADDR[22]
  104. & SNES_ADDR[21]
  105. & &SNES_ADDR[14:13]
  106. & !SNES_ADDR[15])
  107. /* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
  108. TODO: 0000-ffff for small ROMs? */
  109. :(MAPPER == 3'b001)
  110. ? ( &SNES_ADDR[22:20]
  111. & (SNES_ADDR[19:16] < 4'b1110)
  112. & !SNES_ADDR[15]
  113. )
  114. /* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
  115. :(MAPPER == 3'b011)
  116. ? ( (SNES_ADDR[23:19] == 5'b00010)
  117. & (SNES_ADDR[15:12] == 4'b0101)
  118. )
  119. : 1'b0
  120. )
  121. );
  122. /* BS-X has 4 MBits of extra RAM that can be mapped to various places */
  123. wire [2:0] BSX_PSRAM_BANK = {bsx_regs[2], bsx_regs[6], bsx_regs[5]};
  124. wire [23:0] BSX_CHKADDR = bsx_regs[2] ? SNES_ADDR : {SNES_ADDR[23], 1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]};
  125. wire BSX_PSRAM_LOHI = (bsx_regs[3] & ~SNES_ADDR[23]) | (bsx_regs[4] & SNES_ADDR[23]);
  126. wire BSX_IS_PSRAM = BSX_PSRAM_LOHI
  127. & (( (BSX_CHKADDR[22:20] == BSX_PSRAM_BANK)
  128. &(SNES_ADDR[15] | bsx_regs[2])
  129. &(~(SNES_ADDR[19] & bsx_regs[2])))
  130. | (bsx_regs[2]
  131. ? (SNES_ADDR[22:21] == 2'b01 & SNES_ADDR[15:13] == 3'b011)
  132. : (&SNES_ADDR[22:20] & ~SNES_ADDR[15]))
  133. );
  134. wire BSX_IS_CARTROM = ((bsx_regs[7] & (SNES_ADDR[23:22] == 2'b00))
  135. |(bsx_regs[8] & (SNES_ADDR[23:22] == 2'b10)))
  136. & SNES_ADDR[15];
  137. wire BSX_HOLE_LOHI = (bsx_regs[9] & ~SNES_ADDR[23]) | (bsx_regs[10] & SNES_ADDR[23]);
  138. wire BSX_IS_HOLE = BSX_HOLE_LOHI
  139. & (bsx_regs[2] ? (SNES_ADDR[21:20] == {bsx_regs[11], 1'b0})
  140. : (SNES_ADDR[22:21] == {bsx_regs[11], 1'b0}));
  141. assign bsx_tristate = (MAPPER == 3'b011) & ~BSX_IS_CARTROM & ~BSX_IS_PSRAM & BSX_IS_HOLE;
  142. assign IS_WRITABLE = IS_SAVERAM
  143. |((MAPPER == 3'b011)
  144. ? BSX_IS_PSRAM
  145. : 1'b0);
  146. wire [23:0] BSX_ADDR = bsx_regs[2] ? {1'b0, SNES_ADDR[22:0]}
  147. : {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]};
  148. /* BSX regs:
  149. Index Function
  150. 1 0=map flash to ROM area; 1=map PRAM to ROM area
  151. 2 1=HiROM; 0=LoROM
  152. 3 1=Mirror PRAM @60-6f:0000-ffff
  153. 5 1=DO NOT mirror PRAM @40-4f:0000-ffff
  154. 6 1=DO NOT mirror PRAM @50-5f:0000-ffff
  155. 7 1=map BSX cartridge ROM @00-1f:8000-ffff
  156. 8 1=map BSX cartridge ROM @80-9f:8000-ffff
  157. */
  158. assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
  159. ?(IS_SAVERAM
  160. ? 24'h600000 + ((SNES_ADDR[14:0] - 15'h6000)
  161. & SAVERAM_MASK)
  162. : ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
  163. :(MAPPER == 3'b001)
  164. ?(IS_SAVERAM
  165. ? 24'h600000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
  166. : ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
  167. & ROM_MASK))
  168. :(MAPPER == 3'b010)
  169. ?(IS_SAVERAM
  170. ? 24'h600000 + ((SNES_ADDR[14:0] - 15'h6000)
  171. & SAVERAM_MASK)
  172. : ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
  173. & ROM_MASK))
  174. :(MAPPER == 3'b011)
  175. ?(IS_SAVERAM
  176. ? 24'h600000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
  177. : IS_WRITABLE
  178. ? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
  179. : bs_page_enable
  180. ? (24'h900000 + {bs_page,bs_page_offset})
  181. :((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
  182. |(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
  183. ?(24'h800000
  184. + ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
  185. & 24'h0FFFFF)
  186. )
  187. :((bsx_regs[1]
  188. ? 24'h400000
  189. : 24'h000000
  190. )
  191. + bsx_regs[2]
  192. ?({2'b00, SNES_ADDR[21:0]}
  193. & (ROM_MASK /* >> bsx_regs[1] */)
  194. )
  195. :({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
  196. & (ROM_MASK /* >> bsx_regs[1] */)
  197. )
  198. )
  199. )
  200. :(MAPPER == 3'b110)
  201. ?(IS_SAVERAM
  202. ? 24'h600000 + ((SNES_ADDR[14:0] - 15'h6000)
  203. & SAVERAM_MASK)
  204. :(SNES_ADDR[15]
  205. ?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
  206. :({2'b10,
  207. SNES_ADDR[23],
  208. SNES_ADDR[21:16],
  209. SNES_ADDR[14:0]}
  210. )
  211. )
  212. )
  213. :(MAPPER == 3'b111)
  214. ?(IS_SAVERAM
  215. ? 24'h7F0000 + ((SNES_ADDR[14:0] - 15'h6000)
  216. & SAVERAM_MASK)
  217. : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
  218. + 24'hC00000)
  219. )
  220. : 24'b0);
  221. assign ROM_ADDR = SRAM_SNES_ADDR;
  222. assign ROM_SEL = 1'b0;
  223. assign msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
  224. //reg [5:0] msu_enable_r;
  225. //initial msu_enable_r = 6'b000000;
  226. //always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w};
  227. assign msu_enable = msu_enable_w /*&msu_enable_r[5:2]*/;
  228. assign use_bsx = (MAPPER == 3'b011);
  229. assign srtc_enable_w = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
  230. //reg [5:0] srtc_enable_r;
  231. //initial srtc_enable_r = 6'b000000;
  232. //always @(posedge CLK) srtc_enable_r <= {srtc_enable_r[4:0], srtc_enable_w};
  233. assign srtc_enable = srtc_enable_w /*&srtc_enable_r[3:0]*/ & featurebits[FEAT_SRTC];
  234. // DSP1 LoROM: DR=30-3f:8000-bfff; SR=30-3f:c000-ffff
  235. // or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
  236. // DSP1 HiROM: DR=00-0f:6000-6fff; SR=00-0f:7000-7fff
  237. wire dspx_enable_w =
  238. featurebits[FEAT_DSPX]
  239. ?((MAPPER == 3'b001)
  240. ?(ROM_MASK[20]
  241. ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
  242. :(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
  243. )
  244. :(MAPPER == 3'b000)
  245. ?(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15]
  246. & &SNES_ADDR[14:13])
  247. :1'b0)
  248. :featurebits[FEAT_ST0010]
  249. ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & &(~SNES_ADDR[19:16]) & ~SNES_ADDR[15])
  250. :1'b0;
  251. wire dspx_dp_enable_w = featurebits[FEAT_ST0010]
  252. &(SNES_ADDR[22:19] == 4'b1101
  253. && SNES_ADDR[15:11] == 5'b00000);
  254. assign dspx_a0 = featurebits[FEAT_DSPX]
  255. ?((MAPPER == 3'b001) ? SNES_ADDR[14]
  256. :(MAPPER == 3'b000) ? SNES_ADDR[12]
  257. :1'b1)
  258. :featurebits[FEAT_ST0010]
  259. ?SNES_ADDR[0]
  260. :1'b1;
  261. assign dspx_dp_enable = dspx_dp_enable_w;
  262. //reg [5:0] dspx_enable_r;
  263. //initial dspx_enable_r = 6'b000000;
  264. //always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[4:0], dspx_enable_w};
  265. assign dspx_enable = dspx_enable_w /*&dspx_enable_r[5:1]*/;
  266. wire r213f_enable_w = (SNES_PA == 8'h3f);
  267. //reg [5:0] r213f_enable_r;
  268. //initial r213f_enable_r = 6'b000000;
  269. //always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
  270. assign r213f_enable = r213f_enable_w /*&r213f_enable_r[5:2]*/ & featurebits[FEAT_213F];
  271. wire snescmd_rd_enable_w = (SNES_PA[7:4] == 4'b1111);
  272. //reg [5:0] snescmd_rd_enable_r;
  273. //initial snescmd_rd_enable_r = 6'b000000;
  274. //always @(posedge CLK) snescmd_rd_enable_r <= {snescmd_rd_enable_r[4:0], snescmd_rd_enable_w};
  275. assign snescmd_rd_enable = snescmd_rd_enable_w /*&snescmd_rd_enable_r[5:1]*/;
  276. assign snescmd_wr_enable_w = (SNES_ADDR[23:4] == 20'hccccc);
  277. //reg [5:0] snescmd_wr_enable_r;
  278. //initial snescmd_wr_enable_r = 6'b000000;
  279. //always @(posedge CLK) snescmd_wr_enable_r <= {snescmd_wr_enable_r[4:0], snescmd_wr_enable_w};
  280. assign snescmd_wr_enable = snescmd_wr_enable_w /*&snescmd_wr_enable_r[5:1]*/;
  281. endmodule