sdnative.c 30 KB

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  1. #include <arm/NXP/LPC17xx/LPC17xx.h>
  2. #include <stdio.h>
  3. #include "config.h"
  4. #include "crc.h"
  5. #include "crc16.h"
  6. #include "diskio.h"
  7. #include "spi.h"
  8. #include "timer.h"
  9. #include "uart.h"
  10. #include "led.h"
  11. #include "sdnative.h"
  12. #include "fileops.h"
  13. #include "bits.h"
  14. #include "fpga_spi.h"
  15. #include "memory.h"
  16. #define MAX_CARDS 1
  17. // SD/MMC commands
  18. #define GO_IDLE_STATE 0
  19. #define SEND_OP_COND 1
  20. #define ALL_SEND_CID 2
  21. #define SEND_RELATIVE_ADDR 3
  22. #define SWITCH_FUNC 6
  23. #define SELECT_CARD 7
  24. #define SEND_IF_COND 8
  25. #define SEND_CSD 9
  26. #define SEND_CID 10
  27. #define STOP_TRANSMISSION 12
  28. #define SEND_STATUS 13
  29. #define GO_INACTIVE_STATE 15
  30. #define SET_BLOCKLEN 16
  31. #define READ_SINGLE_BLOCK 17
  32. #define READ_MULTIPLE_BLOCK 18
  33. #define WRITE_BLOCK 24
  34. #define WRITE_MULTIPLE_BLOCK 25
  35. #define PROGRAM_CSD 27
  36. #define SET_WRITE_PROT 28
  37. #define CLR_WRITE_PROT 29
  38. #define SEND_WRITE_PROT 30
  39. #define ERASE_WR_BLK_STAR_ADDR 32
  40. #define ERASE_WR_BLK_END_ADDR 33
  41. #define ERASE 38
  42. #define LOCK_UNLOCK 42
  43. #define APP_CMD 55
  44. #define GEN_CMD 56
  45. #define READ_OCR 58
  46. #define CRC_ON_OFF 59
  47. // SD ACMDs
  48. #define SD_SET_BUS_WIDTH 6
  49. #define SD_STATUS 13
  50. #define SD_SEND_NUM_WR_BLOCKS 22
  51. #define SD_SET_WR_BLK_ERASE_COUNT 23
  52. #define SD_SEND_OP_COND 41
  53. #define SD_SET_CLR_CARD_DETECT 42
  54. #define SD_SEND_SCR 51
  55. // R1 status bits
  56. #define STATUS_IN_IDLE 1
  57. #define STATUS_ERASE_RESET 2
  58. #define STATUS_ILLEGAL_COMMAND 4
  59. #define STATUS_CRC_ERROR 8
  60. #define STATUS_ERASE_SEQ_ERROR 16
  61. #define STATUS_ADDRESS_ERROR 32
  62. #define STATUS_PARAMETER_ERROR 64
  63. /* Card types - cardtype == 0 is MMC */
  64. #define CARD_SD (1<<0)
  65. #define CARD_SDHC (1<<1)
  66. /*
  67. Rev.A Rev.C
  68. 1 DAT3/SS P0.6 P2.3
  69. 2 CMD/DI P0.9 P0.9
  70. 5 Clock P0.7 P0.7
  71. 7 DAT0/DO P0.8 P2.0
  72. 8 DAT1/IRQ P1.14 P2.1
  73. 9 DAT2/NC P1.15 P2.2
  74. */
  75. /* SD init procedure
  76. =================
  77. - initial clock frequency: ~100kHz
  78. - cycle the clock for at least 74 cycles (some more may be safer)
  79. - send CMD0
  80. - send CMD8 (SEND_OP_COND); if no response -> HCS=0; else HCS=1
  81. - send ACMD41 until OCR[31] (busy) becomes 1 (means: ready)
  82. - if OCR[30] (CCS) set -> SDHC; else SDSC
  83. - send CMD2 (read CID) (maybe log some stuff from the CID)
  84. - send CMD3 (read RCA), store RCA
  85. == end of initialisation ==
  86. - send CMD9 (read CSD) with RCA, maybe do sth with TRAN_SPEED
  87. - send CMD7 with RCA, select card, put card in tran
  88. - maybe send CMD13 with RCA to check state (tran)
  89. - send ACMD51 with RCA to read SCR (maybe, to check 4bit support)
  90. - increase clock speed
  91. - send ACMD6 with RCA to set 4bit bus width
  92. - send transfer cmds
  93. */
  94. /*
  95. static CMD payloads. (no CRC calc required)
  96. - CMD0: 0x40 0x00 0x00 0x00 0x00 0x95
  97. - CMD8: 0x48 0x00 0x00 0x01 0xaa 0x87
  98. - CMD2: 0x42 0x00 0x00 0x00 0x00 0x4d
  99. - CMD3: 0x43 0x00 0x00 0x00 0x00 0x21
  100. - CMD55: 0x77 0x00 0x00 0x00 0x00 0x65
  101. */
  102. uint8_t cmd[6]={0,0,0,0,0,0};
  103. uint8_t rsp[17];
  104. uint8_t csd[17];
  105. uint8_t cid[17];
  106. diskinfo0_t di;
  107. uint8_t ccs=0;
  108. uint32_t rca;
  109. enum trans_state { TRANS_NONE = 0, TRANS_READ, TRANS_WRITE, TRANS_MID };
  110. enum cmd_state { CMD_RSP = 0, CMD_RSPDAT, CMD_DAT };
  111. int during_blocktrans = TRANS_NONE;
  112. uint32_t last_block = 0;
  113. uint16_t last_offset = 0;
  114. volatile int sd_changed;
  115. /**
  116. * getbits - read value from bit buffer
  117. * @buffer: pointer to the data buffer
  118. * @start : index of the first bit in the value
  119. * @bits : number of bits in the value
  120. *
  121. * This function returns a value from the memory region passed as
  122. * buffer, starting with bit "start" and "bits" bit long. The buffer
  123. * is assumed to be MSB first, passing 0 for start will read starting
  124. * from the highest-value bit of the first byte of the buffer.
  125. */
  126. static uint32_t getbits(void *buffer, uint16_t start, int8_t bits) {
  127. uint8_t *buf = buffer;
  128. uint32_t result = 0;
  129. if ((start % 8) != 0) {
  130. /* Unaligned start */
  131. result += buf[start / 8] & (0xff >> (start % 8));
  132. bits -= 8 - (start % 8);
  133. start += 8 - (start % 8);
  134. }
  135. while (bits >= 8) {
  136. result = (result << 8) + buf[start / 8];
  137. start += 8;
  138. bits -= 8;
  139. }
  140. if (bits > 0) {
  141. result = result << bits;
  142. result = result + (buf[start / 8] >> (8-bits));
  143. } else if (bits < 0) {
  144. /* Fraction of a single byte */
  145. result = result >> -bits;
  146. }
  147. return result;
  148. }
  149. void sdn_checkinit(BYTE drv) {
  150. if(disk_state == DISK_CHANGED) {
  151. disk_initialize(drv);
  152. }
  153. }
  154. uint8_t* sdn_getcid() {
  155. sdn_checkinit(0);
  156. return cid;
  157. }
  158. static inline void wiggle_slow_pos(uint16_t times) {
  159. while(times--) {
  160. delay_us(2);
  161. BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1;
  162. delay_us(2);
  163. BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1;
  164. }
  165. }
  166. static inline void wiggle_slow_neg(uint16_t times) {
  167. while(times--) {
  168. delay_us(2);
  169. BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1;
  170. delay_us(2);
  171. BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1;
  172. }
  173. }
  174. static inline void wiggle_fast_pos(uint16_t times) {
  175. while(times--) {
  176. BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1;
  177. BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1;
  178. }
  179. }
  180. static inline void wiggle_fast_neg(uint16_t times) {
  181. while(times--) {
  182. BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1;
  183. BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1;
  184. }
  185. }
  186. static inline void wiggle_fast_neg1(void) {
  187. BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1;
  188. BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1;
  189. }
  190. static inline void wiggle_fast_pos1(void) {
  191. BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1;
  192. BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1;
  193. }
  194. int get_and_check_datacrc(uint8_t *buf) {
  195. uint16_t crc0=0, crc1=0, crc2=0, crc3=0;
  196. uint16_t sdcrc0=0, sdcrc1=0, sdcrc2=0, sdcrc3=0;
  197. uint8_t d0=0, d1=0, d2=0, d3=0;
  198. uint8_t datdata;
  199. uint16_t datcnt;
  200. /* get crcs from card */
  201. for (datcnt=0; datcnt < 16; datcnt++) {
  202. datdata = SD_DAT;
  203. wiggle_fast_neg1();
  204. sdcrc0 = ((sdcrc0 << 1) & 0xfffe) | ((datdata >> 3) & 0x0001);
  205. sdcrc1 = ((sdcrc1 << 1) & 0xfffe) | ((datdata >> 2) & 0x0001);
  206. sdcrc2 = ((sdcrc2 << 1) & 0xfffe) | ((datdata >> 1) & 0x0001);
  207. sdcrc3 = ((sdcrc3 << 1) & 0xfffe) | ((datdata >> 0) & 0x0001);
  208. }
  209. wiggle_fast_neg1();
  210. /* calc crcs from data */
  211. for (datcnt=0; datcnt < 512; datcnt++) {
  212. d0 = ((d0 << 2) & 0xfc) | ((buf[datcnt] >> 6) & 0x02) | ((buf[datcnt] >> 3) & 0x01) ;
  213. d1 = ((d1 << 2) & 0xfc) | ((buf[datcnt] >> 5) & 0x02) | ((buf[datcnt] >> 2) & 0x01) ;
  214. d2 = ((d2 << 2) & 0xfc) | ((buf[datcnt] >> 4) & 0x02) | ((buf[datcnt] >> 1) & 0x01) ;
  215. d3 = ((d3 << 2) & 0xfc) | ((buf[datcnt] >> 3) & 0x02) | ((buf[datcnt] >> 0) & 0x01) ;
  216. if((datcnt % 4) == 3) {
  217. crc0 = crc_xmodem_update(crc0, d0);
  218. crc1 = crc_xmodem_update(crc1, d1);
  219. crc2 = crc_xmodem_update(crc2, d2);
  220. crc3 = crc_xmodem_update(crc3, d3);
  221. }
  222. }
  223. if((crc0 != sdcrc0) || (crc1 != sdcrc1) || (crc2 != sdcrc2) || (crc3 != sdcrc3)) {
  224. printf("CRC mismatch\nSDCRC CRC\n %04x %04x\n %04x %04x\n %04x %04x\n %04x %04x\n", sdcrc0, crc0, sdcrc1, crc1, sdcrc2, crc2, sdcrc3, crc3);
  225. return 1;
  226. }
  227. return 0;
  228. }
  229. static inline void wait_busy(void) {
  230. while(!(BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN))) {
  231. wiggle_fast_neg1();
  232. }
  233. wiggle_fast_neg(4);
  234. }
  235. /*
  236. send_command_slow
  237. send SD command and put response in rsp.
  238. returns length of response or 0 if there was no response
  239. */
  240. int send_command_slow(uint8_t* cmd, uint8_t* rsp){
  241. uint8_t shift, i=6;
  242. int rsplen;
  243. uint8_t cmdno = *cmd & 0x3f;
  244. wiggle_slow_pos(5);
  245. switch(*cmd & 0x3f) {
  246. case 0:
  247. rsplen = 0;
  248. break;
  249. case 2:
  250. case 9:
  251. case 10:
  252. rsplen = 17;
  253. break;
  254. default:
  255. rsplen = 6;
  256. }
  257. /* send command */
  258. BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1;
  259. while(i--) {
  260. shift = 8;
  261. do {
  262. shift--;
  263. uint8_t data = *cmd;
  264. *cmd<<=1;
  265. if(data&0x80) {
  266. BITBAND(SD_CMDREG->FIOSET, SD_CMDPIN) = 1;
  267. } else {
  268. BITBAND(SD_CMDREG->FIOCLR, SD_CMDPIN) = 1;
  269. }
  270. wiggle_slow_pos(1);
  271. } while (shift);
  272. cmd++;
  273. }
  274. wiggle_slow_pos(1);
  275. BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 0;
  276. if(rsplen) {
  277. uint16_t timeout=1000;
  278. while((BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) && --timeout) {
  279. wiggle_slow_neg(1);
  280. }
  281. if(!timeout) {
  282. printf("CMD%d timed out\n", cmdno);
  283. return 0; /* no response within timeout */
  284. }
  285. i=rsplen;
  286. while(i--) {
  287. shift = 8;
  288. uint8_t data=0;
  289. do {
  290. shift--;
  291. data |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << shift;
  292. wiggle_slow_neg(1);
  293. } while (shift);
  294. *rsp=data;
  295. rsp++;
  296. }
  297. }
  298. return rsplen;
  299. }
  300. /*
  301. send_command_fast
  302. send SD command and put response in rsp.
  303. returns length of response or 0 if there was no response
  304. */
  305. int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){
  306. uint8_t datshift=8, cmdshift, i=6;
  307. uint8_t cmdno = *cmd & 0x3f;
  308. int rsplen, dat=0, waitbusy=0, datcnt=512, j=0;
  309. static int state=CMD_RSP;
  310. wiggle_fast_pos(9); /* give the card >=8 cycles after last command */
  311. DBG_SD printf("send_command_fast: sending CMD%d; payload=%02x%02x%02x%02x%02x%02x...\n", cmdno, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], cmd[5]);
  312. switch(*cmd & 0x3f) {
  313. case 0:
  314. rsplen = 0;
  315. break;
  316. case 2:
  317. case 9:
  318. case 10:
  319. rsplen = 17;
  320. break;
  321. case 12:
  322. rsplen = 6;
  323. waitbusy = 1;
  324. break;
  325. case 13:
  326. case 17:
  327. case 18:
  328. dat = 1;
  329. default:
  330. rsplen = 6;
  331. }
  332. if(dat && (buf==NULL) && !sd_offload) {
  333. printf("send_command_fast error: buf is null but data transfer expected.\n");
  334. return 0;
  335. }
  336. /* send command */
  337. BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1;
  338. while(i--) {
  339. uint8_t data = *cmd;
  340. cmdshift = 8;
  341. do {
  342. cmdshift--;
  343. if(data&0x80) {
  344. BITBAND(SD_CMDREG->FIOSET, SD_CMDPIN) = 1;
  345. } else {
  346. BITBAND(SD_CMDREG->FIOCLR, SD_CMDPIN) = 1;
  347. }
  348. data<<=1;
  349. wiggle_fast_pos1();
  350. } while (cmdshift);
  351. cmd++;
  352. }
  353. wiggle_fast_pos1();
  354. BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 0;
  355. if(rsplen) {
  356. uint32_t timeout=200000;
  357. /* wait for response */
  358. while((BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) && --timeout) {
  359. wiggle_fast_neg1();
  360. }
  361. if(!timeout) {
  362. printf("CMD%d timed out\n", cmdno);
  363. return 0; /* no response within timeout */
  364. }
  365. i=rsplen;
  366. uint8_t cmddata=0, datdata=0;
  367. while(i--) { /* process response */
  368. cmdshift = 8;
  369. do {
  370. if(dat) {
  371. if(!(BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN))) {
  372. printf("data start during response\n");
  373. j=datcnt;
  374. state=CMD_RSPDAT;
  375. break;
  376. }
  377. }
  378. cmdshift--;
  379. cmddata |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << cmdshift;
  380. wiggle_fast_neg1();
  381. } while (cmdshift);
  382. if(state==CMD_RSPDAT)break;
  383. *rsp=cmddata;
  384. cmddata=0;
  385. rsp++;
  386. }
  387. if(state==CMD_RSPDAT) { /* process response+data */
  388. int startbit=1;
  389. DBG_SD printf("processing rsp+data cmdshift=%d i=%d j=%d\n", cmdshift, i, j);
  390. datshift=8;
  391. while(1) {
  392. cmdshift--;
  393. cmddata |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << cmdshift;
  394. if(!cmdshift) {
  395. cmdshift=8;
  396. *rsp=cmddata;
  397. cmddata=0;
  398. rsp++;
  399. i--;
  400. if(!i) {
  401. DBG_SD printf("response end\n");
  402. if(j) state=CMD_DAT; /* response over, remaining data */
  403. break;
  404. }
  405. }
  406. if(!startbit) {
  407. datshift-=4;
  408. datdata |= SD_DAT << datshift;
  409. if(!datshift) {
  410. datshift=8;
  411. *buf=datdata;
  412. datdata=0;
  413. buf++;
  414. j--;
  415. if(!j) break;
  416. }
  417. }
  418. startbit=0;
  419. wiggle_fast_neg1();
  420. }
  421. }
  422. if(dat && state != CMD_DAT) { /* response ended before data */
  423. BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1;
  424. state=CMD_DAT;
  425. j=datcnt;
  426. datshift=8;
  427. timeout=2000000;
  428. DBG_SD printf("response over, waiting for data...\n");
  429. /* wait for data start bit on DAT0 */
  430. while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) {
  431. wiggle_fast_neg1();
  432. }
  433. // printf("%ld\n", timeout);
  434. if(!timeout) printf("timed out!\n");
  435. wiggle_fast_neg1(); /* eat the start bit */
  436. if(sd_offload) {
  437. if(sd_offload_partial) {
  438. if(sd_offload_partial_start != 0) {
  439. if(during_blocktrans == TRANS_MID) sd_offload_partial_start |= 0x8000;
  440. }
  441. if(sd_offload_partial_end != 512) {
  442. sd_offload_partial_end |= 0x8000;
  443. }
  444. DBG_SD printf("new partial %d - %d\n", sd_offload_partial_start, sd_offload_partial_end);
  445. fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end);
  446. fpga_sddma(sd_offload_tgt, 1);
  447. // sd_offload_partial=0;
  448. last_offset=sd_offload_partial_end;
  449. } else {
  450. fpga_sddma(sd_offload_tgt, 0);
  451. last_offset=0;
  452. }
  453. state=CMD_RSP;
  454. return rsplen;
  455. }
  456. }
  457. if(state==CMD_DAT) { /* transfer rest of data */
  458. DBG_SD printf("remaining data: %d\n", j);
  459. if(datshift==8) {
  460. while(1) {
  461. datdata |= SD_DAT << 4;
  462. wiggle_fast_neg1();
  463. datdata |= SD_DAT;
  464. wiggle_fast_neg1();
  465. *buf=datdata;
  466. datdata=0;
  467. buf++;
  468. j--;
  469. if(!j) break;
  470. }
  471. } else {
  472. while(1) {
  473. datshift-=4;
  474. datdata |= SD_DAT << datshift;
  475. if(!datshift) {
  476. datshift=8;
  477. *buf=datdata;
  478. datdata=0;
  479. buf++;
  480. j--;
  481. if(!j) break;
  482. }
  483. wiggle_fast_neg1();
  484. }
  485. }
  486. }
  487. if(dat) {
  488. #ifdef CONFIG_SD_DATACRC
  489. if(get_and_check_datacrc(buf-512)) {
  490. return CRC_ERROR;
  491. }
  492. #else
  493. /* eat the crcs */
  494. wiggle_fast_neg(17);
  495. #endif
  496. }
  497. if(waitbusy) {
  498. DBG_SD printf("waitbusy after send_cmd\n");
  499. wait_busy();
  500. }
  501. state=CMD_RSP;
  502. }
  503. rsp-=rsplen;
  504. DBG_SD printf("send_command_fast: CMD%d response: %02x%02x%02x%02x%02x%02x\n", cmdno, rsp[0], rsp[1], rsp[2], rsp[3], rsp[4], rsp[5]);
  505. BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1;
  506. return rsplen;
  507. }
  508. static inline void make_crc7(uint8_t* cmd) {
  509. cmd[5]=crc7update(0, cmd[0]);
  510. cmd[5]=crc7update(cmd[5], cmd[1]);
  511. cmd[5]=crc7update(cmd[5], cmd[2]);
  512. cmd[5]=crc7update(cmd[5], cmd[3]);
  513. cmd[5]=crc7update(cmd[5], cmd[4]);
  514. cmd[5]=(cmd[5] << 1) | 1;
  515. }
  516. int cmd_slow(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* rsp) {
  517. uint8_t cmdbuf[6];
  518. cmdbuf[0] = 0x40 | cmd;
  519. cmdbuf[1] = param >> 24;
  520. cmdbuf[2] = param >> 16;
  521. cmdbuf[3] = param >> 8;
  522. cmdbuf[4] = param;
  523. if(!crc) {
  524. make_crc7(cmdbuf);
  525. } else {
  526. cmdbuf[5] = crc;
  527. }
  528. return send_command_slow(cmdbuf, rsp);
  529. }
  530. int acmd_slow(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* rsp) {
  531. if(!(cmd_slow(APP_CMD, rca, 0, NULL, rsp))) {
  532. return 0;
  533. }
  534. return cmd_slow(cmd, param, crc, dat, rsp);
  535. }
  536. int cmd_fast(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* rsp) {
  537. uint8_t cmdbuf[6];
  538. cmdbuf[0] = 0x40 | cmd;
  539. cmdbuf[1] = param >> 24;
  540. cmdbuf[2] = param >> 16;
  541. cmdbuf[3] = param >> 8;
  542. cmdbuf[4] = param;
  543. if(!crc) {
  544. make_crc7(cmdbuf);
  545. } else {
  546. cmdbuf[5] = crc;
  547. }
  548. return send_command_fast(cmdbuf, rsp, dat);
  549. }
  550. int acmd_fast(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* rsp) {
  551. if(!(cmd_fast(APP_CMD, rca, 0, NULL, rsp))) {
  552. return 0;
  553. }
  554. return cmd_fast(cmd, param, crc, dat, rsp);
  555. }
  556. int stream_datablock(uint8_t *buf) {
  557. // uint8_t datshift=8;
  558. int j=512;
  559. uint8_t datdata=0;
  560. uint32_t timeout=1000000;
  561. DBG_SD printf("stream_datablock: wait for ready...\n");
  562. if(during_blocktrans != TRANS_MID) {
  563. while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) {
  564. wiggle_fast_neg1();
  565. }
  566. DBG_SD if(!timeout) printf("timeout!\n");
  567. wiggle_fast_neg1(); /* eat the start bit */
  568. }
  569. if(sd_offload) {
  570. if(sd_offload_partial) {
  571. if(sd_offload_partial_start != 0) {
  572. if(during_blocktrans == TRANS_MID) sd_offload_partial_start |= 0x8000;
  573. }
  574. if(sd_offload_partial_end != 512) {
  575. sd_offload_partial_end |= 0x8000;
  576. }
  577. DBG_SD printf("str partial %d - %d\n", sd_offload_partial_start, sd_offload_partial_end);
  578. fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end);
  579. fpga_sddma(sd_offload_tgt, 1);
  580. } else {
  581. fpga_sddma(sd_offload_tgt, 0);
  582. }
  583. } else {
  584. while(1) {
  585. datdata = SD_DAT << 4;
  586. wiggle_fast_neg1();
  587. datdata |= SD_DAT;
  588. wiggle_fast_neg1();
  589. *buf=datdata;
  590. buf++;
  591. j--;
  592. if(!j) break;
  593. }
  594. #ifdef CONFIG_SD_DATACRC
  595. return get_and_check_datacrc(buf-512);
  596. #else
  597. /* eat the crcs */
  598. wiggle_fast_neg(17);
  599. #endif
  600. }
  601. return 0;
  602. }
  603. void send_datablock(uint8_t *buf) {
  604. uint16_t crc0=0, crc1=0, crc2=0, crc3=0, cnt=512;
  605. uint8_t dat0=0, dat1=0, dat2=0, dat3=0, crcshift, datshift;
  606. wiggle_fast_pos1();
  607. BITBAND(SD_DAT0REG->FIODIR, SD_DAT0PIN) = 1;
  608. BITBAND(SD_DAT1REG->FIODIR, SD_DAT1PIN) = 1;
  609. BITBAND(SD_DAT2REG->FIODIR, SD_DAT2PIN) = 1;
  610. BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 1;
  611. BITBAND(SD_DAT0REG->FIOCLR, SD_DAT0PIN) = 1;
  612. BITBAND(SD_DAT1REG->FIOCLR, SD_DAT1PIN) = 1;
  613. BITBAND(SD_DAT2REG->FIOCLR, SD_DAT2PIN) = 1;
  614. BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1;
  615. wiggle_fast_pos1(); /* send start bit to card */
  616. crcshift=8;
  617. while(cnt--) {
  618. datshift=8;
  619. do {
  620. datshift-=4;
  621. /* if(((*buf)>>datshift) & 0x8) {
  622. BITBAND(SD_DAT3REG->FIOSET, SD_DAT3PIN) = 1;
  623. } else {
  624. BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1;
  625. }
  626. if(((*buf)>>datshift) & 0x4) {
  627. BITBAND(SD_DAT2REG->FIOSET, SD_DAT2PIN) = 1;
  628. } else {
  629. BITBAND(SD_DAT2REG->FIOCLR, SD_DAT2PIN) = 1;
  630. }
  631. if(((*buf)>>datshift) & 0x2){
  632. BITBAND(SD_DAT1REG->FIOSET, SD_DAT1PIN) = 1;
  633. } else {
  634. BITBAND(SD_DAT1REG->FIOCLR, SD_DAT1PIN) = 1;
  635. }
  636. if(((*buf)>>datshift) & 0x1){
  637. BITBAND(SD_DAT0REG->FIOSET, SD_DAT0PIN) = 1;
  638. } else {
  639. BITBAND(SD_DAT0REG->FIOCLR, SD_DAT0PIN) = 1;
  640. }*/
  641. SD_DAT0REG->FIOPIN0 = (*buf) >> datshift;
  642. wiggle_fast_pos1();
  643. } while (datshift);
  644. crcshift-=2;
  645. dat0 |= (((*buf)&0x01) | (((*buf)&0x10) >> 3)) << crcshift;
  646. dat1 |= ((((*buf)&0x02) >> 1) | (((*buf)&0x20) >> 4)) << crcshift;
  647. dat2 |= ((((*buf)&0x04) >> 2) | (((*buf)&0x40) >> 5)) << crcshift;
  648. dat3 |= ((((*buf)&0x08) >> 3) | (((*buf)&0x80) >> 6)) << crcshift;
  649. if(!crcshift) {
  650. crc0 = crc_xmodem_update(crc0, dat0);
  651. crc1 = crc_xmodem_update(crc1, dat1);
  652. crc2 = crc_xmodem_update(crc2, dat2);
  653. crc3 = crc_xmodem_update(crc3, dat3);
  654. crcshift=8;
  655. dat0=0;
  656. dat1=0;
  657. dat2=0;
  658. dat3=0;
  659. }
  660. buf++;
  661. }
  662. // printf("crc0=%04x crc1=%04x crc2=%04x crc3=%04x ", crc0, crc1, crc2, crc3);
  663. /* send crcs */
  664. datshift=16;
  665. do {
  666. datshift--;
  667. if((crc0 >> datshift) & 1) {
  668. BITBAND(SD_DAT0REG->FIOSET, SD_DAT0PIN) = 1;
  669. } else {
  670. BITBAND(SD_DAT0REG->FIOCLR, SD_DAT0PIN) = 1;
  671. }
  672. if((crc1 >> datshift) & 1) {
  673. BITBAND(SD_DAT1REG->FIOSET, SD_DAT1PIN) = 1;
  674. } else {
  675. BITBAND(SD_DAT1REG->FIOCLR, SD_DAT1PIN) = 1;
  676. }
  677. if((crc2 >> datshift) & 1) {
  678. BITBAND(SD_DAT2REG->FIOSET, SD_DAT2PIN) = 1;
  679. } else {
  680. BITBAND(SD_DAT2REG->FIOCLR, SD_DAT2PIN) = 1;
  681. }
  682. if((crc3 >> datshift) & 1) {
  683. BITBAND(SD_DAT3REG->FIOSET, SD_DAT3PIN) = 1;
  684. } else {
  685. BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1;
  686. }
  687. wiggle_fast_pos1();
  688. } while(datshift);
  689. /* send end bit */
  690. BITBAND(SD_DAT0REG->FIOSET, SD_DAT0PIN) = 1;
  691. BITBAND(SD_DAT1REG->FIOSET, SD_DAT1PIN) = 1;
  692. BITBAND(SD_DAT2REG->FIOSET, SD_DAT2PIN) = 1;
  693. BITBAND(SD_DAT3REG->FIOSET, SD_DAT3PIN) = 1;
  694. wiggle_fast_pos1();
  695. BITBAND(SD_DAT0REG->FIODIR, SD_DAT0PIN) = 0;
  696. BITBAND(SD_DAT1REG->FIODIR, SD_DAT1PIN) = 0;
  697. BITBAND(SD_DAT2REG->FIODIR, SD_DAT2PIN) = 0;
  698. BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0;
  699. wiggle_fast_neg(3);
  700. dat0=0;
  701. datshift=4;
  702. do {
  703. datshift--;
  704. dat0 |= ((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) << datshift);
  705. wiggle_fast_neg1();
  706. } while (datshift);
  707. DBG_SD printf("crc %02x\n", dat0);
  708. if((dat0 & 7) != 2) {
  709. printf("crc error! %02x\n", dat0);
  710. while(1);
  711. }
  712. if(dat0 & 8) {
  713. printf("missing start bit in CRC status response...\n");
  714. }
  715. wiggle_fast_neg(2);
  716. wait_busy();
  717. }
  718. void read_block(uint32_t address, uint8_t *buf) {
  719. DBG_SD printf("read_block addr=%08lx last_addr=%08lx offld=%d/%d offst=%04x offed=%04x last_off=%04x\n", address, last_block, sd_offload, sd_offload_partial, sd_offload_partial_start, sd_offload_partial_end, last_offset);
  720. if(during_blocktrans == TRANS_READ && (last_block == address-1)) {
  721. //uart_putc('r');
  722. #ifdef CONFIG_SD_DATACRC
  723. int cmd_res;
  724. if((cmd_res = stream_datablock(buf)) == CRC_ERROR) {
  725. while(cmd_res == CRC_ERROR) {
  726. cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
  727. cmd_res = cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp);
  728. }
  729. }
  730. #else
  731. stream_datablock(buf);
  732. #endif
  733. last_block = address;
  734. last_offset = sd_offload_partial_end & 0x1ff;
  735. if(sd_offload_partial && sd_offload_partial_end != 512) {
  736. during_blocktrans = TRANS_MID;
  737. }
  738. sd_offload_partial = 0;
  739. } else if (during_blocktrans == TRANS_MID
  740. && last_block == address
  741. && last_offset == sd_offload_partial_start
  742. && sd_offload_partial) {
  743. sd_offload_partial_start |= 0x8000;
  744. stream_datablock(buf);
  745. during_blocktrans = TRANS_READ;
  746. last_offset = sd_offload_partial_end & 0x1ff;
  747. sd_offload_partial = 0;
  748. } else {
  749. if(during_blocktrans) {
  750. // uart_putc('_');
  751. //printf("nonseq read (%lx -> %lx), restarting transmission\n", last_block, address);
  752. /* send STOP_TRANSMISSION to end an open READ/WRITE_MULTIPLE_BLOCK */
  753. cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
  754. }
  755. during_blocktrans = TRANS_READ;
  756. last_block = address;
  757. if(!ccs) {
  758. address <<= 9;
  759. }
  760. #ifdef CONFIG_SD_DATACRC
  761. while(1) {
  762. if(cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp) != CRC_ERROR) break;
  763. cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
  764. };
  765. #else
  766. cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp);
  767. #endif
  768. sd_offload_partial = 0;
  769. }
  770. // printf("trans state = %d\n", during_blocktrans);
  771. }
  772. void write_block(uint32_t address, uint8_t* buf) {
  773. if(during_blocktrans == TRANS_WRITE && (last_block == address-1)) {
  774. wait_busy();
  775. send_datablock(buf);
  776. last_block=address;
  777. } else {
  778. if(during_blocktrans) {
  779. /* send STOP_TRANSMISSION to end an open READ/WRITE_MULTIPLE_BLOCK */
  780. cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
  781. }
  782. wait_busy();
  783. last_block=address;
  784. if(!ccs) {
  785. address <<= 9;
  786. }
  787. /* only send cmd & get response */
  788. cmd_fast(WRITE_MULTIPLE_BLOCK, address, 0, NULL, rsp);
  789. DBG_SD printf("write_block: CMD25 response = %02x%02x%02x%02x%02x%02x\n", rsp[0], rsp[1], rsp[2], rsp[3], rsp[4], rsp[5]);
  790. wiggle_fast_pos(8);
  791. send_datablock(buf);
  792. during_blocktrans = TRANS_WRITE;
  793. }
  794. }
  795. /* send STOP_TRANSMISSION after multiple block write
  796. * and reset during_blocktrans status */
  797. void flush_write(void) {
  798. cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
  799. wait_busy();
  800. during_blocktrans = TRANS_NONE;
  801. }
  802. //
  803. // Public functions
  804. //
  805. DRESULT sdn_ioctl(BYTE drv, BYTE cmd, void *buffer) {
  806. DRESULT res;
  807. if(drv >= MAX_CARDS) {
  808. res = STA_NOINIT|STA_NODISK;
  809. } else {
  810. switch(cmd) {
  811. case CTRL_SYNC:
  812. flush_write();
  813. res = RES_OK;
  814. break;
  815. default:
  816. res = RES_PARERR;
  817. }
  818. }
  819. return res;
  820. }
  821. DRESULT disk_ioctl(BYTE drv, BYTE cmd, void *buffer) __attribute__ ((weak, alias("sdn_ioctl")));
  822. DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
  823. uint8_t sec;
  824. if(drv >= MAX_CARDS) {
  825. return RES_PARERR;
  826. }
  827. readled(1);
  828. for(sec=0; sec<count; sec++) {
  829. read_block(sector+sec, buffer);
  830. buffer+=512;
  831. }
  832. readled(0);
  833. return RES_OK;
  834. }
  835. DRESULT disk_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) __attribute__ ((weak, alias("sdn_read")));
  836. DSTATUS sdn_initialize(BYTE drv) {
  837. uint8_t rsp[17]; /* space for response */
  838. int rsplen;
  839. uint8_t hcs=0;
  840. rca = 0;
  841. if(drv>=MAX_CARDS) {
  842. return STA_NOINIT|STA_NODISK;
  843. }
  844. if(sdn_status(drv) & STA_NODISK) {
  845. return STA_NOINIT|STA_NODISK;
  846. }
  847. /* if the card is sending data from before a reset we try to deselect it
  848. prior to initialization */
  849. for(rsplen=0; rsplen<2042; rsplen++) {
  850. if(!(BITBAND(SD_DAT3REG->FIOPIN, SD_DAT3PIN))) {
  851. printf("card seems to be sending data, attempting deselect\n");
  852. cmd_slow(SELECT_CARD, 0, 0, NULL, rsp);
  853. }
  854. wiggle_slow_neg(1);
  855. }
  856. printf("sd_init start\n");
  857. BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 1;
  858. BITBAND(SD_DAT3REG->FIOSET, SD_DAT3PIN) = 1;
  859. cmd_slow(GO_IDLE_STATE, 0, 0x95, NULL, rsp);
  860. if((rsplen=cmd_slow(SEND_IF_COND, 0x000001aa, 0x87, NULL, rsp))) {
  861. DBG_SD printf("CMD8 response:\n");
  862. DBG_SD uart_trace(rsp, 0, rsplen, 0);
  863. hcs=1;
  864. }
  865. while(1) {
  866. if(!(acmd_slow(SD_SEND_OP_COND, (hcs << 30) | 0xfc0000, 0, NULL, rsp))) {
  867. printf("ACMD41 no response!\n");
  868. }
  869. if(rsp[1]&0x80) break;
  870. }
  871. BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0;
  872. BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1;
  873. ccs = (rsp[1]>>6) & 1; /* SDHC/XC */
  874. cmd_slow(ALL_SEND_CID, 0, 0x4d, NULL, rsp);
  875. if(cmd_slow(SEND_RELATIVE_ADDR, 0, 0x21, NULL, rsp)) {
  876. rca=(rsp[1]<<24) | (rsp[2]<<16);
  877. printf("RCA: %04lx\n", rca>>16);
  878. } else {
  879. printf("CMD3 no response!\n");
  880. rca=0;
  881. }
  882. /* record CSD for getinfo */
  883. cmd_slow(SEND_CSD, rca, 0, NULL, csd);
  884. sdn_getinfo(drv, 0, &di);
  885. /* record CID */
  886. cmd_slow(SEND_CID, rca, 0, NULL, cid);
  887. /* select the card */
  888. if(cmd_slow(SELECT_CARD, rca, 0, NULL, rsp)) {
  889. printf("card selected!\n");
  890. } else {
  891. printf("CMD7 no response!\n");
  892. }
  893. /* get card status */
  894. cmd_slow(SEND_STATUS, rca, 0, NULL, rsp);
  895. /* set bus width */
  896. acmd_slow(SD_SET_BUS_WIDTH, 0x2, 0, NULL, rsp);
  897. /* set block length */
  898. cmd_slow(SET_BLOCKLEN, 0x200, 0, NULL, rsp);
  899. printf("SD init complete. SDHC/XC=%d\n", ccs);
  900. disk_state = DISK_OK;
  901. during_blocktrans = TRANS_NONE;
  902. return sdn_status(drv);
  903. }
  904. DSTATUS disk_initialize(BYTE drv) __attribute__ ((weak, alias("sdn_initialize")));
  905. void sdn_init(void) {
  906. /* enable GPIO interrupt on SD detect pin, both edges */
  907. /* NVIC_EnableIRQ(EINT3_IRQn);
  908. SD_DT_INT_SETUP(); */
  909. /* disconnect SSP1 */
  910. LPC_PINCON->PINSEL0 &= ~(BV(13) | BV(15) | BV(17) | BV(19));
  911. /* prepare GPIOs */
  912. BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0;
  913. BITBAND(SD_DAT2REG->FIODIR, SD_DAT2PIN) = 0;
  914. BITBAND(SD_DAT1REG->FIODIR, SD_DAT1PIN) = 0;
  915. BITBAND(SD_DAT0REG->FIODIR, SD_DAT0PIN) = 0;
  916. BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
  917. BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1;
  918. BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN) = 1;
  919. LPC_PINCON->PINMODE0 &= ~(BV(14) | BV(15));
  920. LPC_GPIO2->FIOPIN0 = 0x00;
  921. LPC_GPIO2->FIOMASK0 = ~0xf;
  922. }
  923. void disk_init(void) __attribute__ ((weak, alias("sdn_init")));
  924. DSTATUS sdn_status(BYTE drv) {
  925. if (SDCARD_DETECT) {
  926. if (SDCARD_WP) {
  927. return STA_PROTECT;
  928. } else {
  929. return RES_OK;
  930. }
  931. } else {
  932. return STA_NOINIT|STA_NODISK;
  933. }
  934. }
  935. DSTATUS disk_status(BYTE drv) __attribute__ ((weak, alias("sdn_status")));
  936. DRESULT sdn_getinfo(BYTE drv, BYTE page, void *buffer) {
  937. uint32_t capacity;
  938. if (drv >= MAX_CARDS) {
  939. return RES_NOTRDY;
  940. }
  941. if (sdn_status(drv) & STA_NODISK) {
  942. return RES_NOTRDY;
  943. }
  944. if (page != 0) {
  945. return RES_ERROR;
  946. }
  947. if (ccs) {
  948. /* Special CSD for SDHC cards */
  949. capacity = (1 + getbits(csd,127-69+8,22)) * 1024;
  950. } else {
  951. /* Assume that MMC-CSD 1.0/1.1/1.2 and SD-CSD 1.1 are the same... */
  952. uint8_t exponent = 2 + getbits(csd, 127-49+8, 3);
  953. capacity = 1 + getbits(csd, 127-73+8, 12);
  954. exponent += getbits(csd, 127-83+8,4) - 9;
  955. while (exponent--) capacity *= 2;
  956. }
  957. diskinfo0_t *di = buffer;
  958. di->validbytes = sizeof(diskinfo0_t);
  959. di->disktype = DISK_TYPE_SD;
  960. di->sectorsize = 2;
  961. di->sectorcount = capacity;
  962. printf("card capacity: %lu sectors\n", capacity);
  963. return RES_OK;
  964. }
  965. DRESULT disk_getinfo(BYTE drv, BYTE page, void *buffer) __attribute__ ((weak, alias("sdn_getinfo")));
  966. DRESULT sdn_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count) {
  967. uint8_t sec;
  968. uint8_t *buf = (uint8_t*)buffer;
  969. if(drv >= MAX_CARDS) {
  970. return RES_NOTRDY;
  971. }
  972. if (sdn_status(drv) & STA_NODISK) {
  973. return RES_NOTRDY;
  974. }
  975. writeled(1);
  976. for(sec=0; sec<count; sec++) {
  977. write_block(sector+sec, buf);
  978. buf+=512;
  979. }
  980. writeled(0);
  981. return RES_OK;
  982. }
  983. DRESULT disk_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count) __attribute__ ((weak, alias("sdn_write")));
  984. /* Detect changes of SD card 0 */
  985. void sdn_changed() {
  986. if (sd_changed) {
  987. printf("ch ");
  988. if(SDCARD_DETECT) {
  989. disk_state = DISK_CHANGED;
  990. } else {
  991. disk_state = DISK_REMOVED;
  992. }
  993. sd_changed = 0;
  994. }
  995. }
  996. /* measure sd access time */
  997. void sdn_gettacc(uint32_t *tacc_max, uint32_t *tacc_avg) {
  998. uint32_t sec1 = 0;
  999. uint32_t sec2 = 0;
  1000. uint32_t time, time_max = 0;
  1001. uint32_t time_avg = 0LL;
  1002. uint32_t numread = 16384;
  1003. int i;
  1004. int sec_step = di.sectorcount / numread - 1;
  1005. if(disk_state == DISK_REMOVED) return;
  1006. sdn_checkinit(0);
  1007. for (i=0; i < 128; i++) {
  1008. sd_offload_tgt=2;
  1009. sd_offload=1;
  1010. sdn_read(0, NULL, 0, 1);
  1011. sd_offload_tgt=2;
  1012. sd_offload=1;
  1013. sdn_read(0, NULL, i*sec_step, 1);
  1014. }
  1015. for (i=0; i < numread && sram_readbyte(SRAM_CMD_ADDR) != 0x00 && disk_state != DISK_REMOVED; i++) {
  1016. /* reset timer */
  1017. LPC_RIT->RICTRL = 0;
  1018. sd_offload_tgt=2;
  1019. sd_offload=1;
  1020. sdn_read(0, NULL, sec1, 2);
  1021. sec1 += 2;
  1022. /* start timer */
  1023. LPC_RIT->RICOUNTER = 0;
  1024. LPC_RIT->RICTRL = BV(RITEN);
  1025. sd_offload_tgt=2;
  1026. sd_offload=1;
  1027. sdn_read(0, NULL, sec2, 1);
  1028. /* read timer */
  1029. time = LPC_RIT->RICOUNTER;
  1030. /* sd_offload_tgt=2;
  1031. sd_offload=1;
  1032. sdn_read(0, NULL, sec2, 15);*/
  1033. time_avg += time/16;
  1034. if(time > time_max) {
  1035. time_max = time;
  1036. }
  1037. sec2 += sec_step;
  1038. }
  1039. time_avg = time_avg / (i+1) * 16;
  1040. sd_offload=0;
  1041. LPC_RIT->RICTRL = 0;
  1042. if(disk_state != DISK_REMOVED) {
  1043. *tacc_max = time_max/(CONFIG_CPU_FREQUENCY / 1000000)-114;
  1044. *tacc_avg = time_avg/(CONFIG_CPU_FREQUENCY / 1000000)-114;
  1045. }
  1046. }