fpga_spi.h 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. /* sd2snes - SD card based universal cartridge for the SNES
  2. Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
  3. uC firmware portion
  4. Inspired by and based on code from sd2iec, written by Ingo Korb et al.
  5. See sdcard.c|h, config.h.
  6. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
  7. see ff.c|h.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; version 2 of the License only.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. fpga_spi.h: functions for SPI ctrl, SRAM interfacing and feature configuration
  19. */
  20. #ifndef _FPGA_SPI_H
  21. #define _FPGA_SPI_H
  22. #include <arm/NXP/LPC17xx/LPC17xx.h>
  23. #include "bits.h"
  24. #include "spi.h"
  25. #include "config.h"
  26. #define FPGA_SS_BIT 16
  27. #define FPGA_SS_REG LPC_GPIO0
  28. #define FPGA_SELECT() do {FPGA_TX_SYNC(); BITBAND(FPGA_SS_REG->FIOCLR, FPGA_SS_BIT) = 1;} while (0)
  29. #define FPGA_SELECT_ASYNC() do {BITBAND(FPGA_SS_REG->FIOCLR, FPGA_SS_BIT) = 1;} while (0)
  30. #define FPGA_DESELECT() do {FPGA_TX_SYNC(); BITBAND(FPGA_SS_REG->FIOSET, FPGA_SS_BIT) = 1;} while (0)
  31. #define FPGA_DESELECT_ASYNC() do {BITBAND(FPGA_SS_REG->FIOSET, FPGA_SS_BIT) = 1;} while (0)
  32. #define FPGA_TX_SYNC() spi_tx_sync()
  33. #define FPGA_TX_BYTE(x) spi_tx_byte(x)
  34. #define FPGA_RX_BYTE() spi_rx_byte()
  35. #define FPGA_TXRX_BYTE(x) spi_txrx_byte(x)
  36. #define FPGA_TX_BLOCK(x,y) spi_tx_block(x,y)
  37. #define FPGA_RX_BLOCK(x,y) spi_rx_block(x,y)
  38. #define FEAT_213F (1 << 4)
  39. #define FEAT_MSU1 (1 << 3)
  40. #define FEAT_SRTC (1 << 2)
  41. #define FEAT_ST0010 (1 << 1)
  42. #define FEAT_DSPX (1 << 0)
  43. #define FEAT_CX4 (1 << 4)
  44. #define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
  45. /* command parameters */
  46. #define FPGA_MEM_AUTOINC (0x8)
  47. #define FPGA_SDDMA_PARTIAL (0x4)
  48. #define FPGA_TGT_MEM (0x0)
  49. #define FPGA_TGT_DACBUF (0x1)
  50. #define FPGA_TGT_MSUBUF (0x2)
  51. /* commands */
  52. #define FPGA_CMD_SETADDR (0x00)
  53. #define FPGA_CMD_SETROMMASK (0x10)
  54. #define FPGA_CMD_SETRAMMASK (0x20)
  55. #define FPGA_CMD_SETMAPPER(x) (0x30 | (x & 15))
  56. #define FPGA_CMD_SDDMA (0x40)
  57. #define FPGA_CMD_SDDMA_RANGE (0x60)
  58. #define FPGA_CMD_READMEM (0x80)
  59. #define FPGA_CMD_WRITEMEM (0x90)
  60. #define FPGA_CMD_MSUSETBITS (0xe0)
  61. #define FPGA_CMD_DACPAUSE (0xe1)
  62. #define FPGA_CMD_DACPLAY (0xe2)
  63. #define FPGA_CMD_DACRESETPTR (0xe3)
  64. #define FPGA_CMD_MSUSETPTR (0xe4)
  65. #define FPGA_CMD_RTCSET (0xe5)
  66. #define FPGA_CMD_BSXSETBITS (0xe6)
  67. #define FPGA_CMD_SRTCRESET (0xe7)
  68. #define FPGA_CMD_DSPRESETPTR (0xe8)
  69. #define FPGA_CMD_DSPWRITEPGM (0xe9)
  70. #define FPGA_CMD_DSPWRITEDAT (0xea)
  71. #define FPGA_CMD_DSPRESET (0xeb)
  72. #define FPGA_CMD_DSPUNRESET (0xec)
  73. #define FPGA_CMD_SETFEATURE (0xed)
  74. #define FPGA_CMD_SET213F (0xee)
  75. #define FPGA_CMD_TEST (0xf0)
  76. #define FPGA_CMD_GETSTATUS (0xf1)
  77. #define FPGA_CMD_MSUGETADDR (0xf2)
  78. #define FPGA_CMD_MSUGETTRACK (0xf3)
  79. #define FPGA_CMD_GETSYSCLK (0xfe)
  80. #define FPGA_CMD_ECHO (0xff)
  81. void fpga_spi_init(void);
  82. uint8_t fpga_test(void);
  83. uint16_t fpga_status(void);
  84. void spi_fpga(void);
  85. void spi_sd(void);
  86. void spi_none(void);
  87. void set_mcu_addr(uint32_t);
  88. void set_dac_addr(uint16_t);
  89. void dac_play(void);
  90. void dac_pause(void);
  91. void dac_reset(void);
  92. void msu_reset(uint16_t);
  93. void set_msu_addr(uint16_t);
  94. void set_msu_status(uint8_t set, uint8_t reset);
  95. void set_saveram_mask(uint32_t);
  96. void set_rom_mask(uint32_t);
  97. void set_mapper(uint8_t val);
  98. void fpga_sddma(uint8_t tgt, uint8_t partial);
  99. void fpga_set_sddma_range(uint16_t start, uint16_t end);
  100. uint16_t get_msu_track(void);
  101. uint32_t get_msu_offset(void);
  102. uint32_t get_snes_sysclk(void);
  103. void set_bsx_regs(uint8_t set, uint8_t reset);
  104. void set_fpga_time(uint64_t time);
  105. void fpga_reset_srtc_state(void);
  106. void fpga_reset_dspx_addr(void);
  107. void fpga_write_dspx_pgm(uint32_t data);
  108. void fpga_write_dspx_dat(uint16_t data);
  109. void fpga_dspx_reset(uint8_t reset);
  110. void fpga_set_features(uint8_t feat);
  111. void fpga_set_213f(uint8_t data);
  112. #endif