fpga_spi.c 10 KB

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  1. /* sd2snes - SD card based universal cartridge for the SNES
  2. Copyright (C) 2009-2012 Maximilian Rehkopf <otakon@gmx.net>
  3. uC firmware portion
  4. Inspired by and based on code from sd2iec, written by Ingo Korb et al.
  5. See sdcard.c|h, config.h.
  6. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
  7. see ff.c|h.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; version 2 of the License only.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. fpga_spi.h: functions for SPI ctrl, SRAM interfacing and feature configuration
  19. */
  20. /*
  21. SPI commands
  22. cmd param function
  23. =============================================
  24. 0t bbhhll set address to 0xbbhhll
  25. t = target
  26. target: 0 = RAM
  27. 1 = MSU Audio buffer
  28. 2 = MSU Data buffer
  29. targets 1 & 2 only require 2 address bytes to
  30. be written.
  31. 10 bbhhll set SNES input address mask to 0xbbhhll
  32. 20 bbhhll set SRAM address mask to 0xbbhhll
  33. 3m - set mapper to m
  34. 0=HiROM, 1=LoROM, 2=ExHiROM, 6=SF96, 7=Menu
  35. 4s - trigger SD DMA (512b from SD to memory)
  36. s: Bit 2 = partial, Bit 1:0 = target
  37. target: see above
  38. 60 xsssyeee set SD DMA partial transfer parameters
  39. x: 0 = read from sector start (skip until
  40. start offset reached)
  41. 8 = assume mid-sector position and read
  42. immediately
  43. sss = start offset (msb first)
  44. y: 0 = skip rest of SD sector
  45. 8 = stop mid-sector if end offset reached
  46. eee = end offset (msb first)
  47. 8p - read (RAM only)
  48. p: 0 = no increment after read
  49. 8 = increment after read
  50. 9p {xx}* write xx
  51. p: i-tt
  52. tt = target (see above)
  53. i = increment (see above)
  54. E0 ssrr set MSU-1 status register (=FPGA status [7:0])
  55. ss = bits to set in status register (1=set)
  56. rr = bits to reset in status register (1=reset)
  57. E1 - pause DAC
  58. E2 - resume/play DAC
  59. E3 - reset DAC playback pointer (0)
  60. E4 hhll set MSU read pointer
  61. E5 tt{7} set RTC (SPC7110 format + 1000s of year,
  62. nibbles packed)
  63. eg 0x20111210094816 is 2011-12-10, 9:48:16
  64. E6 ssrr set/reset BS-X status register [7:0]
  65. E7 - reset SRTC state
  66. E8 - reset DSP program and data ROM write pointers
  67. E9 hhmmllxxxx write+incr. DSP program ROM (xxxx=dummy writes)
  68. EA hhllxxxx write+incr. DSP data ROM (xxxx=dummy writes)
  69. EB - put DSP into reset
  70. EC - release DSP from reset
  71. ED - set feature enable bits (see below)
  72. EE - set $213f override value (0=NTSC, 1=PAL)
  73. F0 - receive test token (to see if FPGA is alive)
  74. F1 - receive status (16bit, MSB first), see below
  75. F2 - get MSU data address (32bit, MSB first)
  76. F3 - get MSU audio track no. (16bit, MSB first)
  77. F4 - get MSU volume (8bit)
  78. FE - get SNES master clock frequency (32bit, MSB first)
  79. measured 1x/sec
  80. FF {xx}* echo (returns the sent data in the next byte)
  81. FPGA status word:
  82. bit function
  83. ==========================================================================
  84. 15 SD DMA busy (0=idle, 1=busy)
  85. 14 DAC read pointer MSB
  86. 13 MSU read pointer MSB
  87. 12 reserved (0)
  88. 11 reserved (0)
  89. 10 reserved (0)
  90. 9 reserved (0)
  91. 8 reserved (0)
  92. 7 reserved (0)
  93. 6 reserved (0)
  94. 5 MSU1 Audio request from SNES
  95. 4 MSU1 Data request from SNES
  96. 3 reserved (0)
  97. 2 MSU1 Audio control status: 0=no repeat, 1=repeat
  98. 1 MSU1 Audio control status: 0=pause, 1=play
  99. 0 MSU1 Audio control request
  100. FPGA feature enable bits:
  101. bit function
  102. ==========================================================================
  103. 7 -
  104. 6 -
  105. 5 -
  106. 4 enable $213F override
  107. 3 enable MSU1 registers
  108. 2 enable SRTC registers
  109. 1 enable ST0010 mapping
  110. 0 enable DSPx mapping
  111. */
  112. #include <arm/NXP/LPC17xx/LPC17xx.h>
  113. #include "bits.h"
  114. #include "fpga.h"
  115. #include "config.h"
  116. #include "uart.h"
  117. #include "spi.h"
  118. #include "fpga_spi.h"
  119. #include "timer.h"
  120. #include "sdnative.h"
  121. void fpga_spi_init(void) {
  122. spi_init();
  123. BITBAND(FPGA_MCU_RDY_REG->FIODIR, FPGA_MCU_RDY_BIT) = 0;
  124. }
  125. void set_msu_addr(uint16_t address) {
  126. FPGA_SELECT();
  127. FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_MSUBUF);
  128. FPGA_TX_BYTE((address>>8)&0xff);
  129. FPGA_TX_BYTE((address)&0xff);
  130. FPGA_DESELECT();
  131. }
  132. void set_dac_addr(uint16_t address) {
  133. FPGA_SELECT();
  134. FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_DACBUF);
  135. FPGA_TX_BYTE((address>>8)&0xff);
  136. FPGA_TX_BYTE((address)&0xff);
  137. FPGA_DESELECT();
  138. }
  139. void set_mcu_addr(uint32_t address) {
  140. FPGA_SELECT();
  141. FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_MEM);
  142. FPGA_TX_BYTE((address>>16)&0xff);
  143. FPGA_TX_BYTE((address>>8)&0xff);
  144. FPGA_TX_BYTE((address)&0xff);
  145. FPGA_DESELECT();
  146. }
  147. void set_saveram_mask(uint32_t mask) {
  148. FPGA_SELECT();
  149. FPGA_TX_BYTE(FPGA_CMD_SETRAMMASK);
  150. FPGA_TX_BYTE((mask>>16)&0xff);
  151. FPGA_TX_BYTE((mask>>8)&0xff);
  152. FPGA_TX_BYTE((mask)&0xff);
  153. FPGA_DESELECT();
  154. }
  155. void set_rom_mask(uint32_t mask) {
  156. FPGA_SELECT();
  157. FPGA_TX_BYTE(FPGA_CMD_SETROMMASK);
  158. FPGA_TX_BYTE((mask>>16)&0xff);
  159. FPGA_TX_BYTE((mask>>8)&0xff);
  160. FPGA_TX_BYTE((mask)&0xff);
  161. FPGA_DESELECT();
  162. }
  163. void set_mapper(uint8_t val) {
  164. FPGA_SELECT();
  165. FPGA_TX_BYTE(FPGA_CMD_SETMAPPER(val));
  166. FPGA_DESELECT();
  167. }
  168. uint8_t fpga_test() {
  169. FPGA_SELECT();
  170. FPGA_TX_BYTE(FPGA_CMD_TEST);
  171. uint8_t result = FPGA_RX_BYTE();
  172. FPGA_DESELECT();
  173. return result;
  174. }
  175. uint16_t fpga_status() {
  176. FPGA_SELECT();
  177. FPGA_TX_BYTE(FPGA_CMD_GETSTATUS);
  178. uint16_t result = (FPGA_RX_BYTE()) << 8;
  179. result |= FPGA_RX_BYTE();
  180. FPGA_DESELECT();
  181. return result;
  182. }
  183. void fpga_set_sddma_range(uint16_t start, uint16_t end) {
  184. printf("%s %08X -> %08X\n", __func__, start, end);
  185. FPGA_SELECT();
  186. FPGA_TX_BYTE(FPGA_CMD_SDDMA_RANGE);
  187. FPGA_TX_BYTE(start>>8);
  188. FPGA_TX_BYTE(start&0xff);
  189. FPGA_TX_BYTE(end>>8);
  190. FPGA_TX_BYTE(end&0xff);
  191. FPGA_DESELECT();
  192. }
  193. void fpga_sddma(uint8_t tgt, uint8_t partial) {
  194. //printf("%s %02X -> %02X\n", __func__, tgt, partial);
  195. uint32_t test = 0;
  196. uint8_t status = 0;
  197. BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 0;
  198. FPGA_SELECT();
  199. FPGA_TX_BYTE(FPGA_CMD_SDDMA | (tgt & 3) | (partial ? FPGA_SDDMA_PARTIAL : 0));
  200. FPGA_TX_BYTE(0x00); /* dummy for falling DMA_EN edge */
  201. FPGA_DESELECT();
  202. FPGA_SELECT();
  203. FPGA_TX_BYTE(FPGA_CMD_GETSTATUS);
  204. DBG_SD printf("FPGA DMA request sent, wait for completion...");
  205. while(FPGA_RX_BYTE() & 0x80) {
  206. FPGA_RX_BYTE(); /* eat the 2nd status byte */
  207. }
  208. DBG_SD printf("...complete\n");
  209. FPGA_DESELECT();
  210. BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
  211. }
  212. void dac_play() {
  213. FPGA_SELECT();
  214. FPGA_TX_BYTE(FPGA_CMD_DACPLAY);
  215. FPGA_TX_BYTE(0x00); /* latch reset */
  216. FPGA_DESELECT();
  217. }
  218. void dac_pause() {
  219. FPGA_SELECT();
  220. FPGA_TX_BYTE(FPGA_CMD_DACPAUSE);
  221. FPGA_TX_BYTE(0x00); /* latch reset */
  222. FPGA_DESELECT();
  223. }
  224. void dac_reset() {
  225. FPGA_SELECT();
  226. FPGA_TX_BYTE(FPGA_CMD_DACRESETPTR);
  227. FPGA_TX_BYTE(0x00); /* latch reset */
  228. FPGA_TX_BYTE(0x00); /* latch reset */
  229. FPGA_DESELECT();
  230. }
  231. void msu_reset(uint16_t address) {
  232. FPGA_SELECT();
  233. FPGA_TX_BYTE(FPGA_CMD_MSUSETPTR);
  234. FPGA_TX_BYTE((address>>8) & 0xff); /* address hi */
  235. FPGA_TX_BYTE(address & 0xff); /* address lo */
  236. FPGA_TX_BYTE(0x00); /* latch reset */
  237. FPGA_TX_BYTE(0x00); /* latch reset */
  238. FPGA_DESELECT();
  239. }
  240. void set_msu_status(uint8_t set, uint8_t reset) {
  241. FPGA_SELECT();
  242. FPGA_TX_BYTE(FPGA_CMD_MSUSETBITS);
  243. FPGA_TX_BYTE(set);
  244. FPGA_TX_BYTE(reset);
  245. FPGA_TX_BYTE(0x00); /* latch reset */
  246. FPGA_DESELECT();
  247. }
  248. uint16_t get_msu_track() {
  249. FPGA_SELECT();
  250. FPGA_TX_BYTE(FPGA_CMD_MSUGETTRACK);
  251. uint16_t result = (FPGA_RX_BYTE()) << 8;
  252. result |= FPGA_RX_BYTE();
  253. FPGA_DESELECT();
  254. return result;
  255. }
  256. uint32_t get_msu_offset() {
  257. FPGA_SELECT();
  258. FPGA_TX_BYTE(FPGA_CMD_MSUGETADDR);
  259. uint32_t result = (FPGA_RX_BYTE()) << 24;
  260. result |= (FPGA_RX_BYTE()) << 16;
  261. result |= (FPGA_RX_BYTE()) << 8;
  262. result |= (FPGA_RX_BYTE());
  263. FPGA_DESELECT();
  264. return result;
  265. }
  266. uint32_t get_snes_sysclk() {
  267. FPGA_SELECT();
  268. FPGA_TX_BYTE(FPGA_CMD_GETSYSCLK);
  269. FPGA_TX_BYTE(0x00); /* dummy (copy current sysclk count to register) */
  270. uint32_t result = (FPGA_RX_BYTE()) << 24;
  271. result |= (FPGA_RX_BYTE()) << 16;
  272. result |= (FPGA_RX_BYTE()) << 8;
  273. result |= (FPGA_RX_BYTE());
  274. FPGA_DESELECT();
  275. return result;
  276. }
  277. void set_bsx_regs(uint8_t set, uint8_t reset) {
  278. FPGA_SELECT();
  279. FPGA_TX_BYTE(FPGA_CMD_BSXSETBITS);
  280. FPGA_TX_BYTE(set);
  281. FPGA_TX_BYTE(reset);
  282. FPGA_TX_BYTE(0x00); /* latch reset */
  283. FPGA_DESELECT();
  284. }
  285. void set_fpga_time(uint64_t time) {
  286. FPGA_SELECT();
  287. FPGA_TX_BYTE(FPGA_CMD_RTCSET);
  288. FPGA_TX_BYTE((time >> 48) & 0xff);
  289. FPGA_TX_BYTE((time >> 40) & 0xff);
  290. FPGA_TX_BYTE((time >> 32) & 0xff);
  291. FPGA_TX_BYTE((time >> 24) & 0xff);
  292. FPGA_TX_BYTE((time >> 16) & 0xff);
  293. FPGA_TX_BYTE((time >> 8) & 0xff);
  294. FPGA_TX_BYTE(time & 0xff);
  295. FPGA_TX_BYTE(0x00);
  296. FPGA_DESELECT();
  297. }
  298. void fpga_reset_srtc_state() {
  299. FPGA_SELECT();
  300. FPGA_TX_BYTE(FPGA_CMD_SRTCRESET);
  301. FPGA_TX_BYTE(0x00);
  302. FPGA_TX_BYTE(0x00);
  303. FPGA_DESELECT();
  304. }
  305. void fpga_reset_dspx_addr() {
  306. FPGA_SELECT();
  307. FPGA_TX_BYTE(FPGA_CMD_DSPRESETPTR);
  308. FPGA_TX_BYTE(0x00);
  309. FPGA_TX_BYTE(0x00);
  310. FPGA_DESELECT();
  311. }
  312. void fpga_write_dspx_pgm(uint32_t data) {
  313. FPGA_SELECT();
  314. FPGA_TX_BYTE(FPGA_CMD_DSPWRITEPGM);
  315. FPGA_TX_BYTE((data>>16)&0xff);
  316. FPGA_TX_BYTE((data>>8)&0xff);
  317. FPGA_TX_BYTE((data)&0xff);
  318. FPGA_TX_BYTE(0x00);
  319. FPGA_TX_BYTE(0x00);
  320. FPGA_DESELECT();
  321. }
  322. void fpga_write_dspx_dat(uint16_t data) {
  323. FPGA_SELECT();
  324. FPGA_TX_BYTE(FPGA_CMD_DSPWRITEDAT);
  325. FPGA_TX_BYTE((data>>8)&0xff);
  326. FPGA_TX_BYTE((data)&0xff);
  327. FPGA_TX_BYTE(0x00);
  328. FPGA_TX_BYTE(0x00);
  329. FPGA_DESELECT();
  330. }
  331. void fpga_dspx_reset(uint8_t reset) {
  332. FPGA_SELECT();
  333. FPGA_TX_BYTE(reset ? FPGA_CMD_DSPRESET : FPGA_CMD_DSPUNRESET);
  334. FPGA_TX_BYTE(0x00);
  335. FPGA_DESELECT();
  336. }
  337. void fpga_set_features(uint8_t feat) {
  338. printf("set features: %02x\n", feat);
  339. FPGA_SELECT();
  340. FPGA_TX_BYTE(FPGA_CMD_SETFEATURE);
  341. FPGA_TX_BYTE(feat);
  342. FPGA_DESELECT();
  343. }
  344. void fpga_set_213f(uint8_t data) {
  345. printf("set 213f: %d\n", data);
  346. FPGA_SELECT();
  347. FPGA_TX_BYTE(FPGA_CMD_SET213F);
  348. FPGA_TX_BYTE(data);
  349. FPGA_DESELECT();
  350. }