clock.c 2.0 KB

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  1. /* ___DISCLAIMER___ */
  2. /* clock.c: PLL, CCLK, PCLK controls */
  3. #include <arm/NXP/LPC17xx/LPC17xx.h>
  4. #include "clock.h"
  5. #include "bits.h"
  6. #include "uart.h"
  7. void clock_disconnect() {
  8. disconnectPLL0();
  9. disablePLL0();
  10. }
  11. void clock_init() {
  12. /* set flash access time to 5 clks (80<f<=100MHz) */
  13. setFlashAccessTime(5);
  14. /* setup PLL0 for ~44100*256*8 Hz
  15. Base clock: 12MHz
  16. Multiplier: 429
  17. Pre-Divisor: 19
  18. Divisor: 6
  19. (want: 90316800, get: 90315789.47)
  20. -> DAC freq = 44099.5 Hz
  21. -> FPGA freq = 11289473.7Hz
  22. First, disable and disconnect PLL0.
  23. */
  24. clock_disconnect();
  25. /* PLL is disabled and disconnected. setup PCLK NOW as it cannot be changed
  26. reliably with PLL0 connected.
  27. see:
  28. http://ics.nxp.com/support/documents/microcontrollers/pdf/errata.lpc1754.pdf
  29. */
  30. /* continue with PLL0 setup:
  31. enable the xtal oscillator and wait for it to become stable
  32. set the oscillator as clk source for PLL0
  33. set PLL0 multiplier+predivider
  34. enable PLL0
  35. set CCLK divider
  36. wait for PLL0 to lock
  37. connect PLL0
  38. done
  39. */
  40. enableMainOsc();
  41. setClkSrc(CLKSRC_MAINOSC);
  42. setPLL0MultPrediv(22, 1);
  43. enablePLL0();
  44. setCCLKDiv(6);
  45. connectPLL0();
  46. }
  47. void setFlashAccessTime(uint8_t clocks) {
  48. LPC_SC->FLASHCFG=FLASHTIM(clocks);
  49. }
  50. void setPLL0MultPrediv(uint16_t mult, uint8_t prediv) {
  51. LPC_SC->PLL0CFG=PLL_MULT(mult) | PLL_PREDIV(prediv);
  52. PLL0feed();
  53. }
  54. void enablePLL0() {
  55. LPC_SC->PLL0CON |= PLLE0;
  56. PLL0feed();
  57. }
  58. void disablePLL0() {
  59. LPC_SC->PLL0CON &= ~PLLE0;
  60. PLL0feed();
  61. }
  62. void connectPLL0() {
  63. while(!(LPC_SC->PLL0STAT & PLOCK0));
  64. LPC_SC->PLL0CON |= PLLC0;
  65. PLL0feed();
  66. }
  67. void disconnectPLL0() {
  68. LPC_SC->PLL0CON &= ~PLLC0;
  69. PLL0feed();
  70. }
  71. void setCCLKDiv(uint8_t div) {
  72. LPC_SC->CCLKCFG=CCLK_DIV(div);
  73. }
  74. void enableMainOsc() {
  75. LPC_SC->SCS=OSCEN;
  76. while(!(LPC_SC->SCS&OSCSTAT));
  77. }
  78. void disableMainOsc() {
  79. LPC_SC->SCS=0;
  80. }
  81. void PLL0feed() {
  82. LPC_SC->PLL0FEED=0xaa;
  83. LPC_SC->PLL0FEED=0x55;
  84. }
  85. void setClkSrc(uint8_t src) {
  86. LPC_SC->CLKSRCSEL=src;
  87. }