memory.c 5.9 KB

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  1. // insert cool lengthy disclaimer here
  2. // memory.c: SRAM operations
  3. #include <stdint.h>
  4. #include <avr/pgmspace.h>
  5. #include <util/delay.h>
  6. #include "config.h"
  7. #include "uart.h"
  8. #include "fpga.h"
  9. #include "crc16.h"
  10. #include "ff.h"
  11. #include "fileops.h"
  12. #include "spi.h"
  13. #include "fpga_spi.h"
  14. #include "avrcompat.h"
  15. #include "led.h"
  16. #include "smc.h"
  17. #include "fpga_spi.h"
  18. #include "memory.h"
  19. #include "snes.h"
  20. char* hex = "0123456789ABCDEF";
  21. void sram_hexdump(uint32_t addr, uint32_t len) {
  22. static uint8_t buf[16];
  23. uint32_t ptr;
  24. for(ptr=0; ptr < len; ptr += 16) {
  25. sram_readblock((void*)buf, ptr+addr, 16);
  26. uart_trace(buf, 0, 16);
  27. }
  28. }
  29. void sram_writebyte(uint8_t val, uint32_t addr) {
  30. set_avr_addr(addr);
  31. spi_fpga();
  32. spiTransferByte(0x91); // WRITE
  33. spiTransferByte(val);
  34. spiTransferByte(0x00); // dummy
  35. spi_none();
  36. }
  37. uint8_t sram_readbyte(uint32_t addr) {
  38. set_avr_addr(addr);
  39. spi_fpga();
  40. spiTransferByte(0x81); // READ
  41. spiTransferByte(0x00); // dummy
  42. uint8_t val = spiTransferByte(0x00);
  43. spi_none();
  44. return val;
  45. }
  46. void sram_writeshort(uint16_t val, uint32_t addr) {
  47. set_avr_addr(addr);
  48. spi_fpga();
  49. spiTransferByte(0x91); // WRITE
  50. spiTransferByte(val&0xff); // 7-0
  51. spiTransferByte((val>>8)&0xff); // 15-8
  52. spiTransferByte(0x00); // dummy
  53. spi_none();
  54. }
  55. void sram_writelong(uint32_t val, uint32_t addr) {
  56. set_avr_addr(addr);
  57. spi_fpga();
  58. spiTransferByte(0x91); // WRITE
  59. spiTransferByte(val&0xff); // 7-0
  60. spiTransferByte((val>>8)&0xff); // 15-8
  61. spiTransferByte((val>>16)&0xff); // 23-15
  62. spiTransferByte((val>>24)&0xff); // 31-24
  63. spiTransferByte(0x00); // dummy
  64. spi_none();
  65. }
  66. uint16_t sram_readshort(uint32_t addr) {
  67. set_avr_addr(addr);
  68. spi_fpga();
  69. spiTransferByte(0x81);
  70. spiTransferByte(0x00);
  71. uint32_t val = spiTransferByte(0x00);
  72. val |= ((uint32_t)spiTransferByte(0x00)<<8);
  73. spi_none();
  74. return val;
  75. }
  76. uint32_t sram_readlong(uint32_t addr) {
  77. set_avr_addr(addr);
  78. spi_fpga();
  79. spiTransferByte(0x81);
  80. spiTransferByte(0x00);
  81. uint32_t val = spiTransferByte(0x00);
  82. val |= ((uint32_t)spiTransferByte(0x00)<<8);
  83. val |= ((uint32_t)spiTransferByte(0x00)<<16);
  84. val |= ((uint32_t)spiTransferByte(0x00)<<24);
  85. spi_none();
  86. return val;
  87. }
  88. void sram_readblock(void* buf, uint32_t addr, uint16_t size) {
  89. uint16_t count=size;
  90. uint8_t* tgt = buf;
  91. set_avr_addr(addr);
  92. spi_fpga();
  93. spiTransferByte(0x81); // READ
  94. spiTransferByte(0x00); // dummy
  95. while(count--) {
  96. *(tgt++) = spiTransferByte(0x00);
  97. }
  98. spi_none();
  99. }
  100. void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
  101. uint16_t count=size;
  102. uint8_t* src = buf;
  103. set_avr_addr(addr);
  104. spi_fpga();
  105. spiTransferByte(0x91); // WRITE
  106. while(count--) {
  107. spiTransferByte(*src++);
  108. }
  109. spiTransferByte(0x00); // dummy
  110. spi_none();
  111. }
  112. uint32_t load_rom(uint8_t* filename) {
  113. snes_romprops_t romprops;
  114. set_avr_bank(0);
  115. UINT bytes_read;
  116. DWORD filesize;
  117. UINT count=0;
  118. file_open(filename, FA_READ);
  119. filesize = file_handle.fsize;
  120. smc_id(&romprops);
  121. if(file_res) {
  122. uart_putc('?');
  123. uart_putc(0x30+file_res);
  124. return 0;
  125. }
  126. f_lseek(&file_handle, romprops.offset);
  127. for(;;) {
  128. FPGA_SS_HIGH();
  129. SPI_SS_LOW();
  130. bytes_read = file_read();
  131. SPI_SS_HIGH();
  132. if (file_res || !bytes_read) break;
  133. FPGA_SS_LOW();
  134. spiTransferByte(0x91); // write w/ increment
  135. if(!(count++ % 8)) {
  136. // toggle_busy_led();
  137. bounce_busy_led();
  138. uart_putc('.');
  139. }
  140. for(int j=0; j<bytes_read; j++) {
  141. spiTransferByte(file_buf[j]);
  142. }
  143. spiTransferByte(0x00); // dummy tx for increment+write pulse
  144. FPGA_SS_HIGH();
  145. }
  146. file_close();
  147. spi_none();
  148. set_avr_mapper(romprops.mapper_id);
  149. uart_puthex(romprops.header.map);
  150. uart_putc(0x30+romprops.mapper_id);
  151. uint32_t rammask;
  152. uint32_t rommask;
  153. if(filesize > (romprops.romsize_bytes + romprops.offset)) {
  154. romprops.romsize_bytes <<= 1;
  155. }
  156. if(romprops.header.ramsize == 0) {
  157. rammask = 0;
  158. } else {
  159. rammask = romprops.ramsize_bytes - 1;
  160. }
  161. rommask = romprops.romsize_bytes - 1;
  162. uart_putc(' ');
  163. uart_puthex(romprops.header.ramsize);
  164. uart_putc('-');
  165. uart_puthexlong(rammask);
  166. uart_putc(' ');
  167. uart_puthex(romprops.header.romsize);
  168. uart_putc('-');
  169. uart_puthexlong(rommask);
  170. set_saveram_mask(rammask);
  171. set_rom_mask(rommask);
  172. return (uint32_t)filesize;
  173. }
  174. uint32_t load_sram(uint8_t* filename, uint32_t base_addr) {
  175. set_avr_addr(base_addr);
  176. UINT bytes_read;
  177. DWORD filesize;
  178. file_open(filename, FA_READ);
  179. filesize = file_handle.fsize;
  180. if(file_res) return 0;
  181. for(;;) {
  182. FPGA_SS_HIGH();
  183. SPI_SS_LOW();
  184. bytes_read = file_read();
  185. SPI_SS_HIGH();
  186. if (file_res || !bytes_read) break;
  187. FPGA_SS_LOW();
  188. spiTransferByte(0x91);
  189. for(int j=0; j<bytes_read; j++) {
  190. spiTransferByte(file_buf[j]);
  191. }
  192. spiTransferByte(0x00); // dummy tx
  193. FPGA_SS_HIGH();
  194. }
  195. file_close();
  196. return (uint32_t)filesize;
  197. }
  198. void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
  199. uint32_t count = 0;
  200. uint32_t num = 0;
  201. spi_none();
  202. file_open(filename, FA_CREATE_ALWAYS | FA_WRITE);
  203. if(file_res) {
  204. uart_putc(0x30+file_res);
  205. }
  206. while(count<sram_size) {
  207. set_avr_addr(base_addr+count);
  208. spi_fpga();
  209. spiTransferByte(0x81); // read
  210. spiTransferByte(0); // dummy
  211. for(int j=0; j<sizeof(file_buf); j++) {
  212. file_buf[j] = spiTransferByte(0x00);
  213. count++;
  214. }
  215. spi_none();
  216. num = file_write();
  217. if(file_res) {
  218. uart_putc(0x30+file_res);
  219. }
  220. }
  221. file_close();
  222. }
  223. uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size) {
  224. uint8_t data;
  225. uint32_t count;
  226. uint16_t crc;
  227. crc=0;
  228. crc_valid=1;
  229. set_avr_addr(base_addr);
  230. spi_fpga();
  231. spiTransferByte(0x81);
  232. spiTransferByte(0x00);
  233. for(count=0; count<size; count++) {
  234. data = spiTransferByte(0);
  235. if(get_snes_reset()) {
  236. crc_valid = 0;
  237. break;
  238. }
  239. crc += crc16_update(crc, &data, 1);
  240. }
  241. spi_none();
  242. return crc;
  243. }
  244. uint8_t sram_reliable() {
  245. uint16_t score=0;
  246. uint32_t val = sram_readlong(SRAM_SCRATCHPAD);
  247. while(score<SRAM_RELIABILITY_SCORE) {
  248. if(sram_readlong(SRAM_SCRATCHPAD)==val) {
  249. score++;
  250. } else {
  251. score=0;
  252. }
  253. }
  254. return 1;
  255. }