fpga_spi.h 3.3 KB

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  1. /* sd2snes - SD card based universal cartridge for the SNES
  2. Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
  3. uC firmware portion
  4. Inspired by and based on code from sd2iec, written by Ingo Korb et al.
  5. See sdcard.c|h, config.h.
  6. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
  7. see ff.c|h.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; version 2 of the License only.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. fpga_spi.h: functions for SPI ctrl, SRAM interfacing and feature configuration
  19. */
  20. #ifndef _FPGA_SPI_H
  21. #define _FPGA_SPI_H
  22. #include <arm/NXP/LPC17xx/LPC17xx.h>
  23. #include "bits.h"
  24. #include "spi.h"
  25. #include "config.h"
  26. #define FPGA_SS_BIT 16
  27. #define FPGA_SS_REG LPC_GPIO0
  28. #define FPGA_SELECT() do {FPGA_TX_SYNC(); BITBAND(FPGA_SS_REG->FIOCLR, FPGA_SS_BIT) = 1;} while (0)
  29. #define FPGA_SELECT_ASYNC() do {BITBAND(FPGA_SS_REG->FIOCLR, FPGA_SS_BIT) = 1;} while (0)
  30. #define FPGA_DESELECT() do {FPGA_TX_SYNC(); BITBAND(FPGA_SS_REG->FIOSET, FPGA_SS_BIT) = 1;} while (0)
  31. #define FPGA_DESELECT_ASYNC() do {BITBAND(FPGA_SS_REG->FIOSET, FPGA_SS_BIT) = 1;} while (0)
  32. #define FPGA_TX_SYNC() spi_tx_sync()
  33. #define FPGA_TX_BYTE(x) spi_tx_byte(x)
  34. #define FPGA_RX_BYTE() spi_rx_byte()
  35. #define FPGA_TXRX_BYTE(x) spi_txrx_byte(x)
  36. #define FPGA_TX_BLOCK(x,y) spi_tx_block(x,y)
  37. #define FPGA_RX_BLOCK(x,y) spi_rx_block(x,y)
  38. #define FEAT_213F (1 << 4)
  39. #define FEAT_MSU1 (1 << 3)
  40. #define FEAT_SRTC (1 << 2)
  41. #define FEAT_ST0010 (1 << 1)
  42. #define FEAT_DSPX (1 << 0)
  43. #define FEAT_CX4 (1 << 4)
  44. #define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
  45. void fpga_spi_init(void);
  46. uint8_t fpga_test(void);
  47. uint16_t fpga_status(void);
  48. void spi_fpga(void);
  49. void spi_sd(void);
  50. void spi_none(void);
  51. void set_mcu_addr(uint32_t);
  52. void set_dac_addr(uint16_t);
  53. void set_dac_vol(uint8_t);
  54. void dac_play(void);
  55. void dac_pause(void);
  56. void dac_reset(void);
  57. void msu_reset(uint16_t);
  58. void set_msu_addr(uint16_t);
  59. void set_msu_status(uint8_t set, uint8_t reset);
  60. void set_saveram_mask(uint32_t);
  61. void set_rom_mask(uint32_t);
  62. void set_mapper(uint8_t val);
  63. void fpga_sddma(uint8_t tgt, uint8_t partial);
  64. void fpga_set_sddma_range(uint16_t start, uint16_t end);
  65. uint8_t get_msu_volume(void);
  66. uint16_t get_msu_track(void);
  67. uint32_t get_msu_offset(void);
  68. uint32_t get_snes_sysclk(void);
  69. void set_bsx_regs(uint8_t set, uint8_t reset);
  70. void set_fpga_time(uint64_t time);
  71. void fpga_reset_srtc_state(void);
  72. void fpga_reset_dspx_addr(void);
  73. void fpga_write_dspx_pgm(uint32_t data);
  74. void fpga_write_dspx_dat(uint16_t data);
  75. void fpga_dspx_reset(uint8_t reset);
  76. void fpga_set_features(uint8_t feat);
  77. void fpga_set_213f(uint8_t data);
  78. #endif