/* sd2snes - SD card based universal cartridge for the SNES Copyright (C) 2009-2010 Maximilian Rehkopf AVR firmware portion Inspired by and based on code from sd2iec, written by Ingo Korb et al. See sdcard.c|h, config.h. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, see ff.c|h. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; version 2 of the License only. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA memory.c: RAM operations */ #include "config.h" #include "uart.h" #include "fpga.h" #include "crc.h" #include "crc32.h" #include "ff.h" #include "fileops.h" #include "spi.h" #include "fpga_spi.h" #include "led.h" #include "smc.h" #include "memory.h" #include "snes.h" #include "timer.h" #include "rle.h" #include "diskio.h" #include "snesboot.h" #include "msu1.h" #include char* hex = "0123456789ABCDEF"; extern snes_romprops_t romprops; void sram_hexdump(uint32_t addr, uint32_t len) { static uint8_t buf[16]; uint32_t ptr; for(ptr=0; ptr < len; ptr += 16) { sram_readblock((void*)buf, ptr+addr, 16); uart_trace(buf, 0, 16); } } void sram_writebyte(uint8_t val, uint32_t addr) { set_mcu_addr(addr); FPGA_SELECT(); FPGA_TX_BYTE(0x98); /* WRITE */ FPGA_TX_BYTE(val); FPGA_TX_BYTE(0x00); /* dummy */ FPGA_DESELECT(); } uint8_t sram_readbyte(uint32_t addr) { set_mcu_addr(addr); FPGA_SELECT(); FPGA_TX_BYTE(0x88); /* READ */ FPGA_TX_BYTE(0x00); /* dummy */ uint8_t val = FPGA_TXRX_BYTE(0x00); FPGA_DESELECT(); return val; } void sram_writeshort(uint16_t val, uint32_t addr) { set_mcu_addr(addr); FPGA_SELECT(); FPGA_TX_BYTE(0x98); /* WRITE */ FPGA_TX_BYTE(val&0xff); FPGA_TX_BYTE((val>>8)&0xff); FPGA_TX_BYTE(0x00); /* dummy */ FPGA_DESELECT(); } void sram_writelong(uint32_t val, uint32_t addr) { set_mcu_addr(addr); FPGA_SELECT(); FPGA_TX_BYTE(0x98); /* WRITE */ FPGA_TX_BYTE(val&0xff); FPGA_TX_BYTE((val>>8)&0xff); FPGA_TX_BYTE((val>>16)&0xff); FPGA_TX_BYTE((val>>24)&0xff); FPGA_TX_BYTE(0x00); FPGA_DESELECT(); } uint16_t sram_readshort(uint32_t addr) { set_mcu_addr(addr); FPGA_SELECT(); FPGA_TX_BYTE(0x88); FPGA_TX_BYTE(0x00); uint32_t val = FPGA_TXRX_BYTE(0x00); val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<8); FPGA_DESELECT(); return val; } uint32_t sram_readlong(uint32_t addr) { set_mcu_addr(addr); FPGA_SELECT(); FPGA_TX_BYTE(0x88); FPGA_TX_BYTE(0x00); uint32_t val = FPGA_TXRX_BYTE(0x00); val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<8); val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<16); val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<24); FPGA_DESELECT(); return val; } void sram_readlongblock(uint32_t* buf, uint32_t addr, uint16_t count) { set_mcu_addr(addr); FPGA_SELECT(); FPGA_TX_BYTE(0x88); FPGA_TX_BYTE(0x00); uint16_t i=0; while(i (romprops.romsize_bytes + romprops.offset)) { romprops.romsize_bytes <<= 1; } if(romprops.header.ramsize == 0) { rammask = 0; } else { rammask = romprops.ramsize_bytes - 1; } rommask = romprops.romsize_bytes - 1; printf("ramsize=%x rammask=%lx\nromsize=%x rommask=%lx\n", romprops.header.ramsize, rammask, romprops.header.romsize, rommask); set_saveram_mask(rammask); set_rom_mask(rommask); readled(0); if(flags & LOADROM_WITH_SRAM) { if(romprops.ramsize_bytes) { strcpy(strrchr((char*)filename, (int)'.'), ".srm"); printf("SRM file: %s\n", filename); load_sram(filename, SRAM_SAVE_ADDR); } else { printf("No SRAM\n"); } } printf("check MSU..."); if(msu1_check(filename)) { romprops.fpga_features |= FEAT_MSU1; romprops.has_msu1 = 1; } printf("done\n"); romprops.fpga_features |= FEAT_SRTC; fpga_set_features(romprops.fpga_features); if(flags & LOADROM_WITH_RESET) { set_mcu_ovr(0); fpga_dspx_reset(1); snes_reset(1); delay_ms(10); snes_reset(0); fpga_dspx_reset(0); } return (uint32_t)filesize; } uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr) { set_mcu_addr(base_addr); UINT bytes_read; DWORD filesize; file_open(filename, FA_READ); filesize = file_handle.fsize; if(file_res) return 0; for(;;) { ff_sd_offload=1; sd_offload_tgt=0; bytes_read = file_read(); if (file_res || !bytes_read) break; } file_close(); return (uint32_t)filesize; } uint32_t load_sram(uint8_t* filename, uint32_t base_addr) { set_mcu_addr(base_addr); UINT bytes_read; DWORD filesize; file_open(filename, FA_READ); filesize = file_handle.fsize; if(file_res) return 0; for(;;) { bytes_read = file_read(); if (file_res || !bytes_read) break; FPGA_SELECT(); FPGA_TX_BYTE(0x98); for(int j=0; j