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@@ -56,7 +56,14 @@ module main(
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//output DCM_IN_STOPPED,
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//output DCM_FX_STOPPED
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//input DCM_RST
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+ ,
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+ output DBG_P44,
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+ output DBG_P46,
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+ output DBG_P47,
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+ output DBG_P52,
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+ output DBG_P53
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);
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+
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wire [7:0] spi_cmd_data;
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wire [7:0] spi_param_data;
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wire [7:0] spi_input_data;
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@@ -197,7 +204,7 @@ wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
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wire SNES_CSs = (SNES_CSr == 2'b11);
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wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
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wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
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-wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001);
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+wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000011); // slight delay, RD/WR comes after CLK
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wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
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wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
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@@ -326,21 +333,34 @@ initial begin
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SRAM_WE_ARRAY[2'b10] = 13'b1_111111_000000;
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SRAM_WE_ARRAY[2'b11] = 13'b1_111111_111111;
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- SRAM_OE_ARRAY[2'b00] = 13'b1_111111_111111;
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- SRAM_OE_ARRAY[2'b01] = 13'b1_111111_000000;
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+ SRAM_OE_ARRAY[2'b00] = 13'b0_111111_111111;
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+ SRAM_OE_ARRAY[2'b01] = 13'b0_111111_000000;
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SRAM_OE_ARRAY[2'b10] = 13'b0_000000_111111;
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SRAM_OE_ARRAY[2'b11] = 13'b0_000000_000000;
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- SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_001000_000000; // SNES write
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- /* 13'b0001000000000 */
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- SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // SNES read
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+ // *************************************************************
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+ // enable sequences for data path related operations. These
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+ // control when to take a data value from SNES or AVR to the
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+ // SRAM bus and vice versa.
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+ // *************************************************************
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+ // SNES write. Data cannot be latched earlier because data from
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+ // the SNES is not valid before ~50ns after falling edge of /WR.
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+ // This timing is *just* enough to satisfy SRAM's t_SD (Data Setup to
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+ // write end) _and_ SNES's data valid delay.
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+ SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_000100_000000;
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+ // SNES read. No transfers to SRAM.
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+ SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000;
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+
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+ // AVR write. Data is buffered via the SPI module and has to be
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+ // used at any given point.
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AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111; // AVR write
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-// AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // AVR write
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-
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+ // AVR read. No transfers to SRAM.
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AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // AVR read
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+ // SNES write. No transfers from SRAM.
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SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0_000000_000000; // SNES write
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+ // SNES read. 000001 _should_ work but might get too close to the next edge of CE/BHE/ADDR???
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SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0_000100_000000; // SNES read
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/* 13'b0000100000000; */
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@@ -363,7 +383,7 @@ end
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always @(posedge CLK2) begin
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AVR_READ_CYCLE <= AVR_READ;
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AVR_WRITE_CYCLE <= AVR_WRITE;
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- if (SNES_RW_start) begin
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+ if (SNES_cycle_start) begin
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SNES_READ_CYCLE <= SNES_READ;
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SNES_WRITE_CYCLE <= SNES_WRITE;
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STATE <= STATE_0;
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@@ -473,11 +493,14 @@ assign SRAM_WE = !AVR_ENA ? AVR_WRITE
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assign SRAM_OE = !AVR_ENA ? AVR_READ
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: SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
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-assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
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-assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
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+// This crashes after a couple million instructions under rare
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+// circumstances. I don't have the slightest.
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//assign SRAM_BHE = SRAM_ADDR0;
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//assign SRAM_BLE = ~SRAM_ADDR0;
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+// This works
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+assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
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+assign SRAM_BLE = !SRAM_WE ? ~SRAM_ADDR0 : 1'b0;
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// dumb version
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//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
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@@ -498,4 +521,15 @@ assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
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assign IRQ_DIR = 1'b0;
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assign SNES_IRQ = 1'bZ;
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+
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+// DEBUG
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+
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+ assign DBG_P44 = SRAM_DATA[0];
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+ assign DBG_P46 = SRAM_DATA[1];
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+ assign DBG_P47 = SRAM_DATA[2];
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+ assign DBG_P52 = SRAM_OE;
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+ assign DBG_P53 = SRAM_DATA_TO_SNES_MEM;
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+ //SNES_ADDR==24'hC0F000 || SNES_ADDR==24'h40F000 || SNES_ADDR==24'h80F000 || SNES_ADDR==24'h00F000;
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+
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+
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endmodule
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