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@@ -473,10 +473,10 @@ parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
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parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
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parameter ST_MCU_WR_END = 18'b010000000000000000;
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-parameter ROM_RD_WAIT = 4'h0;
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+parameter ROM_RD_WAIT = 4'h1;
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parameter ROM_RD_WAIT_MCU = 4'h6;
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parameter ROM_WR_WAIT = 4'h4;
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-parameter ROM_WR_WAIT1 = 4'h2;
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+parameter ROM_WR_WAIT1 = 4'h3;
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parameter ROM_WR_WAIT2 = 4'h1;
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parameter ROM_WR_WAIT_MCU = 4'h5;
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@@ -582,14 +582,12 @@ always @(posedge CLK2) begin
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ROM_DOUT_ENr <= 1'b0;
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if(SNES_cycle_start & ~SNES_WRITE) begin
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STATE <= ST_SNES_WR_ADDR;
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- if(IS_SAVERAM | IS_WRITABLE | IS_FLASHWR) begin
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+ if(IS_WRITABLE | (IS_FLASHWR & ~bsx_tristate)) begin
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ROM_WEr <= 1'b0;
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- ROM_DOUT_ENr <= 1'b1;
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end
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end else if(SNES_cycle_start) begin
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-// STATE <= ST_SNES_RD_ADDR;
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- STATE <= ST_SNES_RD_END;
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- SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
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+ STATE <= ST_SNES_RD_ADDR;
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+// STATE <= ST_SNES_RD_END;
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end else if(SNES_DEADr & MCU_RD_PENDr) begin
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STATE <= ST_MCU_RD_ADDR;
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end else if(SNES_DEADr & MCU_WR_PENDr) begin
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@@ -602,12 +600,15 @@ always @(posedge CLK2) begin
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end
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ST_SNES_RD_WAIT: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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-// if(ST_MEM_DELAYr == 0) begin
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-// end
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-// else STATE <= ST_SNES_RD_WAIT;
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+ if(ST_MEM_DELAYr == 0) begin
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+ STATE <= ST_SNES_RD_END;
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+ SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
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+ end
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+ else STATE <= ST_SNES_RD_WAIT;
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end
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ST_SNES_WR_ADDR: begin
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+ ROM_DOUT_ENr <= 1'b1;
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ST_MEM_DELAYr <= ROM_WR_WAIT1;
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STATE <= ST_SNES_WR_WAIT1;
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end
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@@ -625,11 +626,12 @@ always @(posedge CLK2) begin
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if(ST_MEM_DELAYr == 0) begin
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STATE <= ST_SNES_WR_END;
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ROM_WEr <= 1'b1;
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+ ROM_DOUT_ENr <= 1'b0;
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end
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else STATE <= ST_SNES_WR_WAIT2;
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end
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ST_SNES_RD_END, ST_SNES_WR_END: begin
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- ROM_DOUT_ENr <= 1'b0;
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+// ROM_DOUT_ENr <= 1'b0;
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if(MCU_RD_PENDr) begin
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STATE <= ST_MCU_RD_ADDR;
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end else if(MCU_WR_PENDr) begin
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@@ -658,18 +660,18 @@ always @(posedge CLK2) begin
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ROM_SAr <= 1'b0;
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ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
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STATE <= ST_MCU_WR_WAIT;
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- ROM_DOUT_ENr <= 1'b1;
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ROM_WEr <= 1'b0;
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end
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ST_MCU_WR_WAIT: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+ ROM_DOUT_ENr <= 1'b1;
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if(ST_MEM_DELAYr == 0) begin
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ROM_WEr <= 1'b1;
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STATE <= ST_MCU_WR_END;
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end
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else STATE <= ST_MCU_WR_WAIT;
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end
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- ST_MCU_WR_END: begin
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+ ST_MCU_WR_END: begin
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ROM_DOUT_ENr <= 1'b0;
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STATE <= ST_IDLE;
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end
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