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@@ -111,28 +111,64 @@ my_dcm snes_dcm(.CLKIN(CLKIN),
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.CLK2X(CLK),
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.CLKFB(CLKFB),
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.CLKFX(CLK2),
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- .CLK0(CLK0)
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+ .CLK0(CLK0),
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+ .LOCKED(DCM_LOCKED),
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+ .RST(DCM_RST)
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);
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+
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+my_dcm2 snes_dcm2(.CLKIN(CLK2),
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+ .CLKFB(CLKFB2),
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+ .CLKFX(FASTCLK),
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+ .CLK0(CLK0_2));
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+
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+assign CLKFB2 = CLK0_2;
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+/*
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+reg DCM_RESET_ACK;
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+reg DCM_RST_BUF;
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+reg [1:0] DCM_LOCKEDr;
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+assign DCM_RST = DCM_RST_BUF;
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+assign DCM_FAIL = (DCM_LOCKEDr == 2'b10);
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+
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+always @(posedge CLKIN) begin
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+ DCM_LOCKEDr <= {DCM_LOCKEDr[0], DCM_LOCKED};
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+end
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+always @(posedge CLKIN) begin
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+ if (DCM_FAIL) begin
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+ DCM_RST_BUF <= 1;
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+ end else begin
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+ DCM_RST_BUF <= 0;
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+ end
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+end*/
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/*my_dcm snes_dcm2(.CLKIN(CLK),
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.CLK2X(CLK2),
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.CLKFB(CLKFB2),
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.CLKFX(CLKFX2)
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);*/
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-assign CLKFB = CLK0;
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+//assign CLKFB = CLK0;
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//assign CLKFB2 = CLK2;
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wire SNES_RW;
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-reg SNES_READs;
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-reg SNES_WRITEs;
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-reg SNES_CSs;
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+reg [1:0] SNES_READr;
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+reg [1:0] SNES_WRITEr;
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+reg [1:0] SNES_CSr;
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+reg [1:0] SNES_CPU_CLKr;
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+reg [3:0] SNES_RWr;
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+
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+wire SNES_READs = (SNES_READr == 2'b11);
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+wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
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+wire SNES_CSs = (SNES_CSr == 2'b11);
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+wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
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+wire SNES_RW_start = (SNES_RWr == 4'b1110); // falling edge marks beginning of cycle
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-assign SNES_RW = (SNES_READs & SNES_WRITEs);
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+assign SNES_RW = (SNES_READ & SNES_WRITE);
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always @(posedge CLK2) begin
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- SNES_READs <= SNES_READ;
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- SNES_WRITEs <= SNES_WRITE;
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- SNES_CSs <= SNES_CS;
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+ SNES_READr <= {SNES_READr[0], SNES_READ};
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+ SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
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+ SNES_CSr <= {SNES_CSr[0], SNES_CS};
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+ SNES_CPU_CLKr <= {SNES_CPU_CLKr[0], SNES_CPU_CLK};
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+ SNES_RWr <= {SNES_RWr[2:0], SNES_RW};
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end
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reg ADDR_WRITE;
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@@ -186,7 +222,7 @@ parameter STATE_7 = 10'b0010000000;
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parameter STATE_8 = 10'b0100000000;
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parameter STATE_9 = 10'b1000000000;
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-reg [9:0] STATE;
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+reg [10:0] STATE;
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reg [3:0] STATEIDX;
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reg STATE_RESET, CYCLE_RESET, CYCLE_RESET_ACK;
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@@ -264,18 +300,25 @@ end
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// the minimum of 6 cycles to get everything done.
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always @(posedge CLK2) begin
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- if (!SNES_RW /* || !AVR_ENA */) begin
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- if (!CYCLE_RESET_ACK)
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+ if (SNES_RW_start /* || !AVR_ENA */) //begin
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+// if (!CYCLE_RESET_ACK)
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CYCLE_RESET <= 1;
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else
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CYCLE_RESET <= 0;
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- end
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+// end
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end
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always @(posedge CLK2) begin
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- if (CYCLE_RESET && !CYCLE_RESET_ACK) begin
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- CYCLE_RESET_ACK <= 1;
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+ if (SNES_RW_start/* && !CYCLE_RESET_ACK*/) begin
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+// CYCLE_RESET_ACK <= 1;
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STATE <= STATE_0;
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+ SNES_READ_CYCLE <= SNES_READ;
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+ SNES_WRITE_CYCLE <= SNES_WRITE;
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+ AVR_READ_CYCLE <= AVR_READ;
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+ AVR_WRITE_CYCLE <= AVR_WRITE;
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+
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+// end else if (!DCM_LOCKED) begin
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+// CYCLE_RESET_ACK <= 0; // ready for new cycle
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end else begin
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case (STATE)
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STATE_0:
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@@ -311,10 +354,6 @@ always @(posedge CLK2) begin
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case (STATE)
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STATE_9: begin
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- SNES_READ_CYCLE <= SNES_READs;
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- SNES_WRITE_CYCLE <= SNES_WRITEs;
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- AVR_READ_CYCLE <= AVR_READ;
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- AVR_WRITE_CYCLE <= AVR_WRITE;
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STATEIDX <= 9;
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end
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@@ -353,6 +392,8 @@ always @(posedge CLK2) begin
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STATE_8: begin
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STATEIDX <= 0;
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end
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+ default:
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+ STATEIDX <= 9;
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endcase
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end
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