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reduced FPGA config: cleanup...

ikari vor 13 Jahren
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d803252866

+ 0 - 52
verilog/sd2sneslite/clk_test.v

@@ -1,52 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    22:40:46 12/20/2010 
-// Design Name: 
-// Module Name:    clk_test 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module clk_test(
-    input clk,
-    input sysclk,
-    output [31:0] snes_sysclk_freq
-    );
-
-reg [31:0] snes_sysclk_freq_r;
-assign snes_sysclk_freq = snes_sysclk_freq_r;
-
-reg [31:0] sysclk_counter;
-reg [31:0] sysclk_value;
-
-initial snes_sysclk_freq_r = 32'hFFFFFFFF;
-initial sysclk_counter = 0;
-initial sysclk_value = 0;
-
-reg [1:0] sysclk_sreg;
-always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
-wire sysclk_rising = (sysclk_sreg == 2'b01);
-
-always @(posedge clk) begin
-  if(sysclk_counter < 90315789) begin
-    sysclk_counter <= sysclk_counter + 1;
-    if(sysclk_rising) sysclk_value <= sysclk_value + 1;
-  end else begin
-    snes_sysclk_freq_r <= sysclk_value;
-	 sysclk_counter <= 0;
-	 sysclk_value <= 0;
-  end
-end
-
-endmodule

+ 0 - 106
verilog/sd2sneslite/dac_dcm.v

@@ -1,106 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    11:00:52 12/29/2010 
-// Design Name: 
-// Module Name:    dac_dcm 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module dac_dcm(
-    input CLKIN,
-    output CLKFX
-    );
-
-   // DCM: Digital Clock Manager Circuit
-   //      Spartan-3
-   // Xilinx HDL Language Template, version 11.1
-
-   DCM #(
-      .SIM_MODE("SAFE"),  // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
-      .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-                          //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-      .CLKFX_DIVIDE(2),   // Can be any integer from 1 to 32
-      .CLKFX_MULTIPLY(19), // Can be any integer from 2 to 32
-      .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
-      .CLKIN_PERIOD(46.560),  // Specify period of input clock
-      .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
-      .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
-      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-                                            //   an integer from 0 to 15
-      .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
-      .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
-      .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
-      .FACTORY_JF(16'hFFFF),   // FACTORY JF values
-//      .LOC("DCM_X0Y0"),
-      .PHASE_SHIFT(0),     // Amount of fixed phase shift from -255 to 255
-      .STARTUP_WAIT("TRUE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
-   ) DCM_inst1 (
-      .CLKFX(CLKFX1),   // DCM CLK synthesis out (M/D)
-      .CLKIN(CLKIN),   // Clock input (from IBUFG, BUFG or DCM)
-      .RST(1'b0)        // DCM asynchronous reset input
-   );
-
-
-   DCM #(
-      .SIM_MODE("SAFE"),  // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
-      .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-                          //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-      .CLKFX_DIVIDE(29),   // Can be any integer from 1 to 32
-      .CLKFX_MULTIPLY(19), // Can be any integer from 2 to 32
-      .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
-      .CLKIN_PERIOD(4.901),  // Specify period of input clock
-      .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
-      .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
-      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-                                            //   an integer from 0 to 15
-      .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
-      .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
-      .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
-      .FACTORY_JF(16'hFFFF),   // FACTORY JF values
-//      .LOC("DCM_X0Y0"),
-      .PHASE_SHIFT(0),     // Amount of fixed phase shift from -255 to 255
-      .STARTUP_WAIT("TRUE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
-   ) DCM_inst2 (
-      .CLKFX(CLKFX2),   // DCM CLK synthesis out (M/D)
-      .CLKIN(CLKFX1),   // Clock input (from IBUFG, BUFG or DCM)
-      .RST(1'b0)        // DCM asynchronous reset input
-   );
-
-   DCM #(
-      .SIM_MODE("SAFE"),  // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
-      .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-                          //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-      .CLKFX_DIVIDE(31),   // Can be any integer from 1 to 32
-      .CLKFX_MULTIPLY(21), // Can be any integer from 2 to 32
-      .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
-      .CLKIN_PERIOD(7.480),  // Specify period of input clock
-      .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
-      .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
-      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-                                            //   an integer from 0 to 15
-      .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
-      .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
-      .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
-      .FACTORY_JF(16'hFFFF),   // FACTORY JF values
-//      .LOC("DCM_X0Y0"),
-      .PHASE_SHIFT(0),     // Amount of fixed phase shift from -255 to 255
-      .STARTUP_WAIT("TRUE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
-   ) DCM_inst3 (
-      .CLKFX(CLKFX),   // DCM CLK synthesis out (M/D)
-      .CLKIN(CLKFX2),   // Clock input (from IBUFG, BUFG or DCM)
-      .RST(1'b0)        // DCM asynchronous reset input
-   );
-
-endmodule

+ 0 - 168
verilog/sd2sneslite/dac_test.v

@@ -1,168 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    19:26:11 07/23/2010 
-// Design Name: 
-// Module Name:    dac_test 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module dac_test(
-	 input clkin,
-    input sysclk,
-	 input we,
-	 input[10:0] pgm_address,
-	 input[7:0] pgm_data,
-	 input[7:0] volume,
-	 input vol_latch,
-	 input play,
-	 input reset,
-    output sdout,
-    output lrck,
-    output mclk,
-	 output DAC_STATUS
-    );
-
-reg[8:0] dac_address_r;
-wire[8:0] dac_address = dac_address_r;
-reg dac_nextaddr_r;
-
-wire[31:0] dac_data;
-assign DAC_STATUS = dac_address_r[8];
-reg[7:0] vol_reg;
-reg[7:0] vol_target_reg;
-reg[1:0] vol_latch_reg;
-reg vol_valid;
-reg[2:0] sysclk_sreg;
-wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
-
-reg [25:0] interpol_count;
-reg interpol_overflow;
-
-always @(posedge clkin) begin
-  sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
-end
-
-dac_buf snes_dac_buf (
-	.clka(clkin),
-	.wea(~we), // Bus [0 : 0] 
-	.addra(pgm_address), // Bus [10 : 0] 
-	.dina(pgm_data), // Bus [7 : 0] 
-	.clkb(clkin),
-	.addrb(dac_address), // Bus [9 : 0] 
-	.doutb(dac_data)); // Bus [15 : 0] 
-
-reg [15:0] cnt;
-reg [15:0] smpcnt;
-reg [15:0] samples;
-wire [15:0] sample = {smpcnt[10] ? ~smpcnt[9:0] : smpcnt[9:0], 6'b0};
-wire [15:0] sample2 = {smpcnt[9] ? ~smpcnt[8:0] : smpcnt[8:0], 7'b0};
-reg [15:0] smpshift;
-reg [15:0] smpdata;
-
-assign mclk = cnt[2];   // mclk = clk/8
-assign lrck = cnt[10];	// lrck = mclk/256
-wire sclk = cnt[5];		// sclk = lrck*32
-
-reg [2:0] lrck_sreg;
-reg [2:0] sclk_sreg;
-wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01);
-wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10);
-
-wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01);
-
-wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
-reg sdout_reg;
-assign sdout = sdout_reg;
-
-reg [1:0] reset_sreg;
-wire reset_rising = (reset_sreg[1:0] == 2'b01);
-
-reg play_r;
-
-initial begin
-	cnt = 16'hff00;
-	smpcnt = 16'b0;
-	lrck_sreg = 2'b11;
-	sclk_sreg = 1'b0;
-	dac_address_r = 11'b0;
-	vol_valid = 1'b0;
-	vol_latch_reg = 1'b0;
-	vol_reg = 8'h0;
-	vol_target_reg = 8'hff;
-	samples <= 16'h0;
-end
-
-always @(posedge clkin) begin
-  if(reset_rising) begin
-    dac_address_r <= 0;
-	 interpol_overflow <= 0;
-	 interpol_count <= 0;
-  end else if(sysclk_rising) begin
-    if(interpol_count > 59378938) begin
-	   interpol_count <= interpol_count + 122500 - 59501439;
-      dac_address_r <= dac_address_r + play_r;
-		interpol_overflow <= 1;
-	 end else begin
-		interpol_count <= interpol_count + 122500;
-		interpol_overflow <= 0;
-	 end
-  end
-end
-
-always @(posedge clkin) begin
-	cnt <= cnt + 1;
-	lrck_sreg <= {lrck_sreg[1:0], lrck};
-	sclk_sreg <= {sclk_sreg[1:0], sclk};
-	vol_latch_reg <= {vol_latch_reg[0], vol_latch};
-	play_r <= play;
-	reset_sreg <= {reset_sreg[0], reset};
-end
-
-always @(posedge clkin) begin
-	if (vol_latch_rising) begin
-	   vol_valid <= 1'b1;
-	end 
-	else if(vol_valid) begin
-		vol_target_reg <= volume;
-      vol_valid <= 1'b0;
-	end
-end
-
-// ramp volume only every 4 samples
-always @(posedge clkin) begin
-	if (lrck_rising && &samples[1:0]) begin
-	   if(vol_reg > vol_target_reg)
-			vol_reg <= vol_reg - 1;
-		else if(vol_reg < vol_target_reg)
-			vol_reg <= vol_reg + 1;
-	end
-end
-
-always @(posedge clkin) begin
-   if (lrck_rising) begin	// right channel
-		smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
-		samples <= samples + 1;
-	end else if (lrck_falling) begin		// left channel
-		smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
-	end else begin
-		if (sclk_rising) begin
-			smpcnt <= smpcnt + 1;
-			sdout_reg <= smpshift[15];
-			smpshift <= {smpshift[14:0], 1'b0};
-		end
-	end
-end
-
-endmodule

+ 0 - 182
verilog/sd2sneslite/msu.v

@@ -1,182 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    14:55:04 12/14/2010 
-// Design Name: 
-// Module Name:    msu 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module msu(
-    input clkin,
-	 input enable,
-    input [13:0] pgm_address,
-    input [7:0] pgm_data,
-	 input pgm_we,
-    input [2:0] reg_addr,
-    input [7:0] reg_data_in,
-	 output [7:0] reg_data_out,
-    input reg_oe,
-    input reg_we,
-    output [6:0] status_out,
-    output [7:0] volume_out,
-	 output volume_latch_out,
-    output [31:0] addr_out,
-	 output [15:0] track_out,
-	 input [5:0] status_reset_bits,
-	 input [5:0] status_set_bits,
-	 input status_reset_we,
-	 input [13:0] msu_address_ext,
-	 input msu_address_ext_write
-    );
-
-reg [1:0] status_reset_we_r;
-always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
-wire status_reset_en = (status_reset_we_r == 2'b01);
-
-reg [13:0] msu_address_r;
-wire [13:0] msu_address = msu_address_r;
-
-wire [7:0] msu_data;
-reg [7:0] msu_data_r;
-
-reg [1:0] msu_address_ext_write_sreg;
-always @(posedge clkin) msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write};
-wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01);
-
-reg [5:0] reg_oe_sreg;
-always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
-wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000);
-wire reg_oe_rising = (reg_oe_sreg[5:0] == 6'b000001);
-
-reg [1:0] reg_we_sreg;
-always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we};
-wire reg_we_rising = (reg_we_sreg[1:0] == 2'b01);
-
-reg [31:0] addr_out_r;
-assign addr_out = addr_out_r;
-
-reg [15:0] track_out_r;
-assign track_out = track_out_r;
-
-reg [7:0] volume_r;
-assign volume_out = volume_r;
-
-reg volume_start_r;
-assign volume_latch_out = volume_start_r;
-
-reg audio_start_r;
-reg audio_busy_r;
-reg data_start_r;
-reg data_busy_r;
-reg ctrl_start_r;
-reg [1:0] audio_ctrl_r;
-reg [1:0] audio_status_r;
-
-initial begin
-	audio_busy_r <= 1'b1;
-	data_busy_r <= 1'b1;
-end
-
-assign status_out = {msu_address_r[13], 
-                     audio_start_r, data_start_r, volume_start_r, audio_ctrl_r, ctrl_start_r};
-
-initial msu_address_r = 14'h1234;
-
-msu_databuf snes_msu_databuf (
-	.clka(clkin),
-	.wea(~pgm_we), // Bus [0 : 0] 
-	.addra(pgm_address), // Bus [13 : 0] 
-	.dina(pgm_data), // Bus [7 : 0] 
-	.clkb(clkin),
-	.addrb(msu_address), // Bus [13 : 0] 
-	.doutb(msu_data)); // Bus [7 : 0] 
-
-reg [7:0] msu_regs [7:0];
-
-reg [7:0] data_out_r;
-reg [7:0] data_in_r;
-assign reg_data_out = data_out_r;
-always @(posedge clkin) data_in_r <= reg_data_in;
-
-always @(posedge clkin) begin
-  case(reg_addr)
-      3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001};
-	   3'h1: data_out_r <= msu_data_r;
-	   3'h2: data_out_r <= 8'h53;
-	   3'h3: data_out_r <= 8'h2d;
-	   3'h4: data_out_r <= 8'h4d;
-	   3'h5: data_out_r <= 8'h53;
-	   3'h6: data_out_r <= 8'h55;
-	   3'h7: data_out_r <= 8'h31;
-  endcase
-end
-
-always @(posedge clkin) begin
-  if(reg_we_rising && enable) begin
-    case(reg_addr)
-      3'h0: addr_out_r[7:0] <= reg_data_in;
-		3'h1: addr_out_r[15:8] <= reg_data_in;
-		3'h2: addr_out_r[23:16] <= reg_data_in;
-		3'h3: begin
-		  addr_out_r[31:24] <= reg_data_in;
-        data_start_r <= 1'b1;
-		  data_busy_r <= 1'b1;
-		end
-		3'h4: begin
-		  track_out_r[7:0] <= reg_data_in;
-		end
-		3'h5: begin
-		  track_out_r[15:8] <= reg_data_in;
-		  audio_start_r <= 1'b1;
-		  audio_busy_r <= 1'b1;
-		end
-		3'h6: begin
-		  volume_r <= reg_data_in;
-        volume_start_r <= 1'b1;
-		end
-		3'h7: begin
-		  if(!audio_busy_r) begin
-		    audio_ctrl_r <= reg_data_in[1:0];
-			 ctrl_start_r <= 1'b1;
-		  end
-		end
-	 endcase
-  end else if (status_reset_en) begin
-	 audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
-	 if(status_reset_bits[5]) audio_start_r <= 1'b0;
-	 
-	 data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
-	 if(status_reset_bits[4]) data_start_r <= 1'b0;
-
-//	 volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3];
-
-	 audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
-	 
-	 ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
-  end else begin
-    volume_start_r <= 1'b0;
-  end
-end
-
-always @(posedge clkin) begin
-  if(msu_address_ext_write_rising)
-    msu_address_r <= msu_address_ext;
-  else if(enable && reg_addr == 3'h1 && reg_oe_falling) begin
-    msu_address_r <= msu_address_r + 1;
-	 msu_data_r <= msu_data;
-  end
-end
-
-endmodule

+ 0 - 4
verilog/sd2sneslite/sd2sneslite.xise

@@ -35,10 +35,6 @@
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="Implementation"/>
     </file>
-    <file xil_pn:name="dac_dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
     <file xil_pn:name="avr_cmd.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="Implementation"/>

+ 0 - 132
verilog/sd2sneslite/sd_dma.v

@@ -1,132 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    19:19:08 12/01/2010 
-// Design Name: 
-// Module Name:    sd_dma 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module sd_dma(
-    input [3:0] SD_DAT,
-    inout SD_CLK,
-    input CLK,
-    input SD_DMA_EN,
-	 input SD_DMA_TGT,
-    output SD_DMA_STATUS,
-    output SD_DMA_SRAM_WE,
-    output SD_DMA_NEXTADDR,
-    output [7:0] SD_DMA_SRAM_DATA,
-	 input SD_DMA_PARTIAL,
-	 input [10:0] SD_DMA_PARTIAL_START,
-	 input [10:0] SD_DMA_PARTIAL_END
-    );
-
-reg [10:0] SD_DMA_STARTr;
-reg [10:0] SD_DMA_ENDr;
-reg SD_DMA_PARTIALr;
-always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
-
-reg SD_DMA_DONEr;
-reg[2:0] SD_DMA_DONEr2;
-initial begin
-  SD_DMA_DONEr2 = 3'b000;
-  SD_DMA_DONEr = 1'b0;
-end
-always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[1:0], SD_DMA_DONEr};
-wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
-
-reg [2:0] SD_DMA_ENr;
-initial SD_DMA_ENr = 3'b000;
-always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[1:0], SD_DMA_EN};
-wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
-
-reg SD_DMA_STATUSr;
-assign SD_DMA_STATUS = SD_DMA_STATUSr;
-
-// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
-reg [10:0] cyclecnt;
-initial cyclecnt = 11'd0;
-
-reg SD_DMA_SRAM_WEr;
-assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
-
-reg SD_DMA_NEXTADDRr;
-assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
-
-reg[7:0] SD_DMA_SRAM_DATAr;
-assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
-
-// we have 4 internal cycles per SD clock
-reg [12:0] clkcnt;
-initial clkcnt = 13'd0;
-reg SD_CLKr;
-always @(posedge CLK) SD_CLKr <= clkcnt[1];
-assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ;
-
-always @(posedge CLK) begin
-  if(SD_DMA_EN_rising) begin
-    SD_DMA_STATUSr <= 1'b1;
-	 SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
-	 SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
-  end 
-  else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
-end
-
-always @(posedge CLK) begin
-  if(cyclecnt == 1042) SD_DMA_DONEr <= 1;
-  else SD_DMA_DONEr <= 0;
-end
-
-always @(posedge CLK) begin
-  if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
-	 clkcnt <= 0;
-  end else begin
-	 if(SD_DMA_STATUSr) begin
-	   clkcnt <= clkcnt + 1;
-	 end
-  end
-end
-
-always @(posedge CLK) begin
-  if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0;
-  else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1;
-end
-
-// we have 8 clk cycles to complete one RAM write
-// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
-always @(posedge CLK) begin
-  if(SD_DMA_STATUSr) begin
-    case(clkcnt[2:0])
-      3'h0: begin
-	     SD_DMA_SRAM_WEr <= 1'b1;
-		  SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
-		  if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
-	   end
-	   3'h1:
-        SD_DMA_NEXTADDRr <= 1'b0;
-//	 3'h2:
-      3'h3:
-        if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
-      3'h4:
-        SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
-//	 3'h5:
-//	 3'h6:
-//  3'h7:
-    endcase
-  end
-end
-
-endmodule
-