|
@@ -1,106 +0,0 @@
|
|
|
-`timescale 1ns / 1ps
|
|
|
-//////////////////////////////////////////////////////////////////////////////////
|
|
|
-// Company:
|
|
|
-// Engineer:
|
|
|
-//
|
|
|
-// Create Date: 11:00:52 12/29/2010
|
|
|
-// Design Name:
|
|
|
-// Module Name: dac_dcm
|
|
|
-// Project Name:
|
|
|
-// Target Devices:
|
|
|
-// Tool versions:
|
|
|
-// Description:
|
|
|
-//
|
|
|
-// Dependencies:
|
|
|
-//
|
|
|
-// Revision:
|
|
|
-// Revision 0.01 - File Created
|
|
|
-// Additional Comments:
|
|
|
-//
|
|
|
-//////////////////////////////////////////////////////////////////////////////////
|
|
|
-module dac_dcm(
|
|
|
- input CLKIN,
|
|
|
- output CLKFX
|
|
|
- );
|
|
|
-
|
|
|
- // DCM: Digital Clock Manager Circuit
|
|
|
- // Spartan-3
|
|
|
- // Xilinx HDL Language Template, version 11.1
|
|
|
-
|
|
|
- DCM #(
|
|
|
- .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
|
- .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
|
- // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
|
- .CLKFX_DIVIDE(2), // Can be any integer from 1 to 32
|
|
|
- .CLKFX_MULTIPLY(19), // Can be any integer from 2 to 32
|
|
|
- .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
|
- .CLKIN_PERIOD(46.560), // Specify period of input clock
|
|
|
- .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
|
|
- .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
|
|
|
- .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
|
- // an integer from 0 to 15
|
|
|
- .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
|
|
- .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
|
|
- .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
|
- .FACTORY_JF(16'hFFFF), // FACTORY JF values
|
|
|
-// .LOC("DCM_X0Y0"),
|
|
|
- .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
|
|
- .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
|
- ) DCM_inst1 (
|
|
|
- .CLKFX(CLKFX1), // DCM CLK synthesis out (M/D)
|
|
|
- .CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
|
- .RST(1'b0) // DCM asynchronous reset input
|
|
|
- );
|
|
|
-
|
|
|
-
|
|
|
- DCM #(
|
|
|
- .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
|
- .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
|
- // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
|
- .CLKFX_DIVIDE(29), // Can be any integer from 1 to 32
|
|
|
- .CLKFX_MULTIPLY(19), // Can be any integer from 2 to 32
|
|
|
- .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
|
- .CLKIN_PERIOD(4.901), // Specify period of input clock
|
|
|
- .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
|
|
- .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
|
|
|
- .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
|
- // an integer from 0 to 15
|
|
|
- .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
|
|
- .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
|
|
- .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
|
- .FACTORY_JF(16'hFFFF), // FACTORY JF values
|
|
|
-// .LOC("DCM_X0Y0"),
|
|
|
- .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
|
|
- .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
|
- ) DCM_inst2 (
|
|
|
- .CLKFX(CLKFX2), // DCM CLK synthesis out (M/D)
|
|
|
- .CLKIN(CLKFX1), // Clock input (from IBUFG, BUFG or DCM)
|
|
|
- .RST(1'b0) // DCM asynchronous reset input
|
|
|
- );
|
|
|
-
|
|
|
- DCM #(
|
|
|
- .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
|
- .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
|
- // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
|
- .CLKFX_DIVIDE(31), // Can be any integer from 1 to 32
|
|
|
- .CLKFX_MULTIPLY(21), // Can be any integer from 2 to 32
|
|
|
- .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
|
- .CLKIN_PERIOD(7.480), // Specify period of input clock
|
|
|
- .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
|
|
- .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
|
|
|
- .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
|
- // an integer from 0 to 15
|
|
|
- .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
|
|
- .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
|
|
- .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
|
- .FACTORY_JF(16'hFFFF), // FACTORY JF values
|
|
|
-// .LOC("DCM_X0Y0"),
|
|
|
- .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
|
|
- .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
|
- ) DCM_inst3 (
|
|
|
- .CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
|
- .CLKIN(CLKFX2), // Clock input (from IBUFG, BUFG or DCM)
|
|
|
- .RST(1'b0) // DCM asynchronous reset input
|
|
|
- );
|
|
|
-
|
|
|
-endmodule
|