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@@ -1,194 +1,611 @@
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NET "CLKIN" TNM_NET = CLKIN;
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-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 12.288 MHz HIGH 50 %;
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-NET "AVR_ENA" IOSTANDARD = LVCMOS33;
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+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.579 MHz HIGH 50 %;
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+NET "SNES_CS" IOSTANDARD = LVCMOS33;
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+NET "SNES_READ" IOSTANDARD = LVCMOS33;
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+NET "SNES_WRITE" IOSTANDARD = LVCMOS33;
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+NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33;
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+NET "SNES_REFRESH" IOSTANDARD = LVCMOS33;
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+
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+NET "CLKIN" IOSTANDARD = LVCMOS33;
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+//NET "CLKIN" PULLUP;
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+NET "SPI_SS" PULLUP;
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+//NET "DCM_RST" LOC = P46;
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+//NET "DCM_RST" IOSTANDARD = LVCMOS33;
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+NET "IRQ_DIR" IOSTANDARD = LVCMOS33;
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+NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33;
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+NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33;
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+NET "SNES_IRQ" IOSTANDARD = LVCMOS33;
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+NET "SPI_DMA_CTRL" PULLUP;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "SNES_ADDR[0]" LOC = P119;
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+NET "SNES_ADDR[10]" LOC = P146;
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+NET "SNES_ADDR[11]" LOC = P148;
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+NET "SNES_ADDR[12]" LOC = P147;
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+NET "SNES_ADDR[13]" LOC = P144;
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+NET "SNES_ADDR[14]" LOC = P141;
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+NET "SNES_ADDR[15]" LOC = P139;
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+NET "SNES_ADDR[16]" LOC = P137;
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+NET "SNES_ADDR[17]" LOC = P133;
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+NET "SNES_ADDR[18]" LOC = P131;
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+NET "SNES_ADDR[19]" LOC = P128;
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+NET "SNES_ADDR[1]" LOC = P122;
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+NET "SNES_ADDR[20]" LOC = P125;
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+NET "SNES_ADDR[21]" LOC = P123;
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+NET "SNES_ADDR[22]" LOC = P120;
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+NET "SNES_ADDR[23]" LOC = P117;
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+NET "SNES_ADDR[2]" LOC = P124;
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+NET "SNES_ADDR[3]" LOC = P126;
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+NET "SNES_ADDR[4]" LOC = P130;
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+NET "SNES_ADDR[5]" LOC = P132;
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+NET "SNES_ADDR[6]" LOC = P135;
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+NET "SNES_ADDR[7]" LOC = P138;
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+NET "SNES_ADDR[8]" LOC = P140;
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+NET "SNES_ADDR[9]" LOC = P143;
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+NET "SNES_DATA[0]" LOC = P107;
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+NET "SNES_DATA[1]" LOC = P102;
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+NET "SNES_DATA[2]" LOC = P100;
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+NET "SNES_DATA[3]" LOC = P96;
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+NET "SNES_DATA[4]" LOC = P108;
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+NET "SNES_DATA[5]" LOC = P106;
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+NET "SNES_DATA[6]" LOC = P101;
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+NET "SNES_DATA[7]" LOC = P97;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "CLKIN" LOC = P80;
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+NET "IRQ_DIR" LOC = P113;
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+NET "MCU_OVR" LOC = P92;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "MCU_OVR" IOSTANDARD = LVCMOS33;
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+NET "MCU_OVR" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[0]" LOC = P166;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[0]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[0]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[10]" LOC = P197;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[10]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[10]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[11]" LOC = P196;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[11]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[11]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[12]" LOC = P2;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[12]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[12]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[13]" LOC = P194;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[13]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[13]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[14]" LOC = P200;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[14]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[14]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[15]" LOC = P184;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[15]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[15]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[16]" LOC = P199;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[16]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[16]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[17]" LOC = P11;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[17]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[17]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[18]" LOC = P3;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[18]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[18]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[19]" LOC = P4;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[19]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[19]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[1]" LOC = P168;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[1]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[1]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[20]" LOC = P191;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[20]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[20]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[21]" LOC = P203;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[21]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[21]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[22]" LOC = P198;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[22]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[22]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[2]" LOC = P171;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[2]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[2]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[3]" LOC = P165;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[3]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[3]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[4]" LOC = P169;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[4]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[4]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[5]" LOC = P18;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[5]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[5]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[6]" LOC = P175;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[6]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[6]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[7]" LOC = P167;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[7]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[7]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[8]" LOC = P205;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[8]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[8]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_ADDR[9]" LOC = P204;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_ADDR[9]" IOSTANDARD = LVCMOS33;
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+NET "ROM_ADDR[9]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_BHE" LOC = P161;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_BHE" IOSTANDARD = LVCMOS33;
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+NET "ROM_BHE" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_BLE" LOC = P156;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_BLE" IOSTANDARD = LVCMOS33;
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+NET "ROM_BLE" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_CE" LOC = P172;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_CE" IOSTANDARD = LVCMOS33;
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+NET "ROM_CE" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[0]" LOC = P176;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[0]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[0]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[10]" LOC = P15;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[10]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[10]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[11]" LOC = P12;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[11]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[11]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[12]" LOC = P10;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[12]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[12]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[13]" LOC = P7;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[13]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[13]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[14]" LOC = P9;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[14]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[14]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[15]" LOC = P5;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[15]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[15]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[1]" LOC = P178;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[1]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[1]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[2]" LOC = P181;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[2]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[2]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[3]" LOC = P182;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[3]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[3]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[4]" LOC = P183;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[4]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[4]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[5]" LOC = P187;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[5]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[5]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "ROM_DATA[6]" LOC = P185;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "ROM_DATA[6]" IOSTANDARD = LVCMOS33;
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+NET "ROM_DATA[6]" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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|
|
+NET "ROM_DATA[7]" LOC = P189;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
+NET "ROM_DATA[7]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "ROM_DATA[7]" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "ROM_DATA[8]" LOC = P16;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
+NET "ROM_DATA[8]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "ROM_DATA[8]" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "ROM_DATA[9]" LOC = P13;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
+NET "ROM_DATA[9]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "ROM_DATA[9]" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "ROM_OE" LOC = P162;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
+NET "ROM_OE" IOSTANDARD = LVCMOS33;
|
|
|
+NET "ROM_OE" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "ROM_WE" LOC = P190;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
+NET "ROM_WE" IOSTANDARD = LVCMOS33;
|
|
|
+NET "ROM_WE" DRIVE = 8;
|
|
|
NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[0]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[10]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[11]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[12]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[12]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[13]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[13]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[14]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[14]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[15]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[15]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[16]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[16]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[17]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[17]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[18]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[18]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[19]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[19]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[1]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[1]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[20]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[20]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[21]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[21]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[22]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[22]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[23]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[23]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[2]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[2]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[3]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[3]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[4]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[4]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[5]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[5]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[6]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[6]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[7]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[8]" DRIVE = 8;
|
|
|
NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SNES_CS" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_ADDR[9]" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "SNES_CPU_CLK" LOC = P94;
|
|
|
+NET "SNES_CS" LOC = P116;
|
|
|
+NET "SNES_DATABUS_DIR" LOC = P111;
|
|
|
+NET "SNES_DATABUS_OE" LOC = P109;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_DATA[0]" DRIVE = 8;
|
|
|
NET "SNES_DATA[1]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_DATA[1]" DRIVE = 8;
|
|
|
NET "SNES_DATA[2]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_DATA[2]" DRIVE = 8;
|
|
|
NET "SNES_DATA[3]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_DATA[3]" DRIVE = 8;
|
|
|
NET "SNES_DATA[4]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_DATA[4]" DRIVE = 8;
|
|
|
NET "SNES_DATA[5]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_DATA[5]" DRIVE = 8;
|
|
|
NET "SNES_DATA[6]" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_DATA[6]" DRIVE = 8;
|
|
|
NET "SNES_DATA[7]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SNES_READ" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SNES_WRITE" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SNES_REFRESH" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SNES_DATA[7]" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "SNES_IRQ" LOC = P114;
|
|
|
+NET "SNES_READ" LOC = P115;
|
|
|
+NET "SNES_REFRESH" LOC = P155;
|
|
|
+NET "SNES_WRITE" LOC = P95;
|
|
|
+NET "SPI_DMA_CTRL" LOC = P83;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
+NET "SPI_DMA_CTRL" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SPI_DMA_CTRL" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "SPI_MISO" LOC = P72;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
NET "SPI_MISO" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SPI_MISO" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "SPI_MOSI" LOC = P74;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
|
|
|
-NET "AVR_ENA" LOC = P58;
|
|
|
-NET "CLKIN" LOC = P125;
|
|
|
-NET "IRQ_DIR" LOC = P40;
|
|
|
-NET "SNES_ADDR[0]" LOC = P7;
|
|
|
-NET "SNES_ADDR[10]" LOC = P32;
|
|
|
-NET "SNES_ADDR[11]" LOC = P35;
|
|
|
-NET "SNES_ADDR[12]" LOC = P33;
|
|
|
-NET "SNES_ADDR[13]" LOC = P31;
|
|
|
-NET "SNES_ADDR[14]" LOC = P28;
|
|
|
-NET "SNES_ADDR[15]" LOC = P26;
|
|
|
-NET "SNES_ADDR[16]" LOC = P24;
|
|
|
-NET "SNES_ADDR[17]" LOC = P21;
|
|
|
-NET "SNES_ADDR[18]" LOC = P18;
|
|
|
-NET "SNES_ADDR[19]" LOC = P15;
|
|
|
-NET "SNES_ADDR[1]" LOC = P10;
|
|
|
-NET "SNES_ADDR[20]" LOC = P13;
|
|
|
-NET "SNES_ADDR[21]" LOC = P11;
|
|
|
-NET "SNES_ADDR[22]" LOC = P8;
|
|
|
-NET "SNES_ADDR[23]" LOC = P6;
|
|
|
-NET "SNES_ADDR[2]" LOC = P12;
|
|
|
-NET "SNES_ADDR[3]" LOC = P14;
|
|
|
-NET "SNES_ADDR[4]" LOC = P17;
|
|
|
-NET "SNES_ADDR[5]" LOC = P20;
|
|
|
-NET "SNES_ADDR[6]" LOC = P23;
|
|
|
-NET "SNES_ADDR[7]" LOC = P25;
|
|
|
-NET "SNES_ADDR[8]" LOC = P27;
|
|
|
-NET "SNES_ADDR[9]" LOC = P30;
|
|
|
-NET "SNES_CPU_CLK" LOC = P1;
|
|
|
-NET "SNES_CS" LOC = P5;
|
|
|
-NET "SNES_READ" LOC = P2;
|
|
|
-NET "SNES_REFRESH" LOC = P36;
|
|
|
-NET "SNES_WRITE" LOC = P4;
|
|
|
-NET "SPI_SS" LOC = P65;
|
|
|
-NET "SRAM_ADDR[10]" LOC = P60;
|
|
|
-NET "SRAM_ADDR[11]" LOC = P59;
|
|
|
-NET "SRAM_ADDR[12]" LOC = P57;
|
|
|
-NET "SRAM_ADDR[13]" LOC = P56;
|
|
|
-NET "SRAM_ADDR[14]" LOC = P51;
|
|
|
-NET "SRAM_ADDR[15]" LOC = P50;
|
|
|
-NET "SRAM_ADDR[19]" LOC = P69;
|
|
|
-NET "SRAM_ADDR[8]" LOC = P68;
|
|
|
-NET "SRAM_ADDR[9]" LOC = P63;
|
|
|
-NET "SRAM_CE2[0]" LOC = P77;
|
|
|
-NET "SRAM_CE2[1]" LOC = P76;
|
|
|
-NET "SRAM_CE2[2]" LOC = P74;
|
|
|
-NET "SRAM_CE2[3]" LOC = P73;
|
|
|
-NET "SRAM_WE" LOC = P70;
|
|
|
-NET "SNES_DATABUS_DIR" LOC = P141;
|
|
|
-NET "SNES_DATABUS_OE" LOC = P140;
|
|
|
-NET "SNES_DATA[0]" LOC = P137;
|
|
|
-NET "SNES_DATA[1]" LOC = P132;
|
|
|
-NET "SNES_DATA[2]" LOC = P130;
|
|
|
-NET "SNES_DATA[3]" LOC = P128;
|
|
|
-NET "SNES_DATA[4]" LOC = P135;
|
|
|
-NET "SNES_DATA[5]" LOC = P131;
|
|
|
-NET "SNES_DATA[6]" LOC = P129;
|
|
|
-NET "SNES_DATA[7]" LOC = P127;
|
|
|
-NET "SNES_IRQ" LOC = P55;
|
|
|
-NET "SPI_MISO" LOC = P123;
|
|
|
-NET "SPI_MOSI" LOC = P122;
|
|
|
-NET "SPI_SCK" LOC = P124;
|
|
|
-NET "SRAM_ADDR[0]" LOC = P92;
|
|
|
-NET "SRAM_ADDR[16]" LOC = P119;
|
|
|
-NET "SRAM_ADDR[17]" LOC = P82;
|
|
|
-NET "SRAM_ADDR[18]" LOC = P80;
|
|
|
-NET "SRAM_ADDR[1]" LOC = P90;
|
|
|
-NET "SRAM_ADDR[2]" LOC = P89;
|
|
|
-NET "SRAM_ADDR[3]" LOC = P87;
|
|
|
-NET "SRAM_ADDR[4]" LOC = P86;
|
|
|
-NET "SRAM_ADDR[5]" LOC = P85;
|
|
|
-NET "SRAM_ADDR[6]" LOC = P84;
|
|
|
-NET "SRAM_ADDR[7]" LOC = P83;
|
|
|
-NET "SRAM_BHE" LOC = P78;
|
|
|
-NET "SRAM_BLE" LOC = P79;
|
|
|
-NET "SRAM_DATA[0]" LOC = P95;
|
|
|
-NET "SRAM_DATA[10]" LOC = P100;
|
|
|
-NET "SRAM_DATA[11]" LOC = P103;
|
|
|
-NET "SRAM_DATA[12]" LOC = P105;
|
|
|
-NET "SRAM_DATA[13]" LOC = P108;
|
|
|
-NET "SRAM_DATA[14]" LOC = P113;
|
|
|
-NET "SRAM_DATA[15]" LOC = P118;
|
|
|
-NET "SRAM_DATA[1]" LOC = P97;
|
|
|
-NET "SRAM_DATA[2]" LOC = P99;
|
|
|
-NET "SRAM_DATA[3]" LOC = P102;
|
|
|
-NET "SRAM_DATA[4]" LOC = P104;
|
|
|
-NET "SRAM_DATA[5]" LOC = P107;
|
|
|
-NET "SRAM_DATA[6]" LOC = P112;
|
|
|
-NET "SRAM_DATA[7]" LOC = P116;
|
|
|
-NET "SRAM_DATA[8]" LOC = P96;
|
|
|
-NET "SRAM_DATA[9]" LOC = P98;
|
|
|
-NET "SRAM_OE" LOC = P93;
|
|
|
+NET "SPI_MOSI" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "SPI_SCK" LOC = P71;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
|
|
|
-NET "CLKIN" IOSTANDARD = LVCMOS33;
|
|
|
-//NET "CLKIN" PULLUP;
|
|
|
-NET "SPI_SS" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SPI_SS" PULLUP;
|
|
|
-//NET "DCM_RST" LOC = P46;
|
|
|
-//NET "DCM_RST" IOSTANDARD = LVCMOS33;
|
|
|
-NET "IRQ_DIR" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SNES_IRQ" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[0]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[10]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[11]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[12]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[13]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[14]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[15]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[16]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[17]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[18]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[19]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[1]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[2]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[3]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[4]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[5]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[6]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[7]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[8]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_ADDR[9]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_BHE" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_BLE" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_CE2[0]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_CE2[1]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_CE2[2]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_CE2[3]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[0]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[10]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[11]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[12]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[13]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[14]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[15]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[1]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[2]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[3]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[4]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[5]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[6]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[7]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[8]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_DATA[9]" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_OE" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SRAM_WE" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SPI_DMA_CTRL" LOC = P41;
|
|
|
-NET "SPI_DMA_CTRL" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SPI_DMA_CTRL" PULLUP;
|
|
|
NET "SPI_SCK" IOSTANDARD = LVCMOS33;
|
|
|
-NET "SPI_SCK" DRIVE = 16;
|
|
|
+NET "SPI_SCK" DRIVE = 8;
|
|
|
NET "SPI_SCK" PULLUP;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "SPI_SS" LOC = P68;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
+NET "SPI_SS" IOSTANDARD = LVCMOS33;
|
|
|
+NET "SPI_SS" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "DAC_LRCK" LOC = P77;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
|
+
|
|
|
+NET "DAC_LRCK" IOSTANDARD = LVCMOS33;
|
|
|
+NET "DAC_LRCK" DRIVE = 8;
|
|
|
+
|
|
|
+# PlanAhead generated physical constraints
|
|
|
+
|
|
|
+NET "DAC_MCLK" LOC = P76;
|
|
|
+
|
|
|
+# PlanAhead generated IO constraints
|
|
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+
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+NET "DAC_MCLK" IOSTANDARD = LVCMOS33;
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+NET "DAC_MCLK" DRIVE = 8;
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+
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+# PlanAhead generated physical constraints
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+
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+NET "DAC_SDOUT" LOC = P78;
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+
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+# PlanAhead generated IO constraints
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+
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+NET "DAC_SDOUT" IOSTANDARD = LVCMOS33;
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+NET "DAC_SDOUT" DRIVE = 8;
|