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@@ -26,9 +26,9 @@ if { [info exists CPUTAPID ] } {
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}
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#delays on reset lines
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-#if your OpenOCD version rejects "jtag_nsrst_delay" replace it with:
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-#adapter_nsrst_delay 200
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-jtag_nsrst_delay 200
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+#if your OpenOCD version rejects "adapter_nsrst_delay" replace it with:
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+#jtag_nsrst_delay 200
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+adapter_nsrst_delay 200
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jtag_ntrst_delay 200
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# LPC2000 & LPC1700 -> SRST causes TRST
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@@ -39,7 +39,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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#jtag newtap x3s tap -irlen 6 -ircapture 0x11 -irmask 0x11 -expected-id 0x0141c093
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set _TARGETNAME $_CHIPNAME.cpu
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-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME -event reset-init 0
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+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME -event reset-init 0
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# LPC1754 has 16kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
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# and 16K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
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@@ -56,7 +56,7 @@ flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \
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# Run with *real slow* clock by default since the
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# boot rom could have been playing with the PLL, so
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# we have no idea what clock the target is running at.
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-jtag_khz 1000
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+adapter_khz 1000
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$_TARGETNAME configure -event reset-init {
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# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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