Browse Source

Adjust OpenOCD configuration for more recent versions

Maximilian Rehkopf 10 years ago
parent
commit
c380ce9503
1 changed files with 5 additions and 5 deletions
  1. 5 5
      src/lpc1754.cfg

+ 5 - 5
src/lpc1754.cfg

@@ -26,9 +26,9 @@ if { [info exists CPUTAPID ] } {
 }
 
 #delays on reset lines
-#if your OpenOCD version rejects "jtag_nsrst_delay" replace it with:
-#adapter_nsrst_delay 200
-jtag_nsrst_delay 200
+#if your OpenOCD version rejects "adapter_nsrst_delay" replace it with:
+#jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
 # LPC2000 & LPC1700 -> SRST causes TRST
@@ -39,7 +39,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 #jtag newtap x3s tap -irlen 6 -ircapture 0x11 -irmask 0x11 -expected-id 0x0141c093
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME -event reset-init 0
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME -event reset-init 0
 
 # LPC1754 has 16kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
 # and 16K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
@@ -56,7 +56,7 @@ flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-jtag_khz 1000
+adapter_khz 1000
 
 $_TARGETNAME configure -event reset-init {
 	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select