|
@@ -319,31 +319,35 @@ initial begin
|
|
|
SNES_WRITE_CYCLE = 1'b1;
|
|
|
AVR_READ_CYCLE = 1'b1;
|
|
|
AVR_WRITE_CYCLE = 1'b1;
|
|
|
- MODE_ARRAY = 13'b0000000111111;
|
|
|
+ MODE_ARRAY = 13'b0_000000_111111;
|
|
|
|
|
|
- SRAM_WE_ARRAY[2'b00] = 13'b1000000000000;
|
|
|
- SRAM_WE_ARRAY[2'b01] = 13'b1000000111111;
|
|
|
- SRAM_WE_ARRAY[2'b10] = 13'b1111111000000;
|
|
|
- SRAM_WE_ARRAY[2'b11] = 13'b1111111111111;
|
|
|
-
|
|
|
- SRAM_OE_ARRAY[2'b00] = 13'b1111111111111;
|
|
|
- SRAM_OE_ARRAY[2'b01] = 13'b1111111000000;
|
|
|
- SRAM_OE_ARRAY[2'b10] = 13'b0000000111111;
|
|
|
- SRAM_OE_ARRAY[2'b11] = 13'b0000000000000;
|
|
|
+ SRAM_WE_ARRAY[2'b00] = 13'b1_000000_000000;
|
|
|
+ SRAM_WE_ARRAY[2'b01] = 13'b1_000000_111111;
|
|
|
+ SRAM_WE_ARRAY[2'b10] = 13'b1_111111_000000;
|
|
|
+ SRAM_WE_ARRAY[2'b11] = 13'b1_111111_111111;
|
|
|
+
|
|
|
+ SRAM_OE_ARRAY[2'b00] = 13'b1_111111_111111;
|
|
|
+ SRAM_OE_ARRAY[2'b01] = 13'b1_111111_000000;
|
|
|
+ SRAM_OE_ARRAY[2'b10] = 13'b0_000000_111111;
|
|
|
+ SRAM_OE_ARRAY[2'b11] = 13'b0_000000_000000;
|
|
|
|
|
|
- SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0001000000000; // SNES write
|
|
|
+ SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_001000_000000; // SNES write
|
|
|
/* 13'b0001000000000 */
|
|
|
- SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000; // SNES read
|
|
|
+ SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // SNES read
|
|
|
|
|
|
- AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // AVR write
|
|
|
- AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000; // AVR read
|
|
|
+ AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111; // AVR write
|
|
|
+// AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // AVR write
|
|
|
+
|
|
|
+ AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // AVR read
|
|
|
|
|
|
- SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0000000000000; // SNES write
|
|
|
- SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0000100000000; // SNES read
|
|
|
+ SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0_000000_000000; // SNES write
|
|
|
+ SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0_000010_000000; // SNES read
|
|
|
/* 13'b0000100000000; */
|
|
|
|
|
|
- SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0000000000000; // AVR write
|
|
|
- SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001; // AVR read
|
|
|
+ SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0_000000_000000; // AVR write
|
|
|
+ SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0_000000_000001; // AVR read
|
|
|
+// SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001; // AVR read
|
|
|
+
|
|
|
end
|
|
|
|
|
|
// falling edge of SNES /RD or /WR marks the beginning of a new cycle
|
|
@@ -357,11 +361,11 @@ always @(posedge CLK2) begin
|
|
|
end
|
|
|
|
|
|
always @(posedge CLK2) begin
|
|
|
+ AVR_READ_CYCLE <= AVR_READ;
|
|
|
+ AVR_WRITE_CYCLE <= AVR_WRITE;
|
|
|
if (SNES_RW_start) begin
|
|
|
SNES_READ_CYCLE <= SNES_READ;
|
|
|
SNES_WRITE_CYCLE <= SNES_WRITE;
|
|
|
- AVR_READ_CYCLE <= AVR_READ;
|
|
|
- AVR_WRITE_CYCLE <= AVR_WRITE;
|
|
|
STATE <= STATE_0;
|
|
|
STATEIDX <= 11;
|
|
|
end else begin
|
|
@@ -472,6 +476,9 @@ assign SRAM_OE = !AVR_ENA ? AVR_READ
|
|
|
assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
|
|
|
assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
|
|
|
|
|
|
+//assign SRAM_BHE = SRAM_ADDR0;
|
|
|
+//assign SRAM_BLE = ~SRAM_ADDR0;
|
|
|
+
|
|
|
// dumb version
|
|
|
//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
|
|
|
//assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
|