Browse Source

FPGA/Cx4: WIP

ikari 12 years ago
parent
commit
8c76dfbeb6

+ 1 - 0
src/fpga_spi.h

@@ -50,6 +50,7 @@
 #define FPGA_SPI_FAST()    spi_set_speed(SPI_SPEED_FPGA_FAST)
 #define FPGA_SPI_SLOW()    spi_set_speed(SPI_SPEED_FPGA_SLOW)
 
+#define FEAT_CX4           (1 << 4)
 #define FEAT_MSU1          (1 << 3)
 #define FEAT_SRTC          (1 << 2)
 #define FEAT_ST0010        (1 << 1)

+ 21 - 16
src/memory.c

@@ -226,18 +226,16 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
     sram_writebyte(0xfc, rombase+0xd5);
     set_fpga_time(0x0220110301180530LL);
   }
-  if(romprops.has_dspx) {
-    printf("DSPx game. Loading firmware image %s...\n", romprops.necdsp_fw);
-    if(romprops.has_st0010) {
-      load_dspx(romprops.necdsp_fw, 1);
-    } else {
-      load_dspx(romprops.necdsp_fw, 0);
-      if(file_res && romprops.necdsp_fw == DSPFW_1) {
-        load_dspx(DSPFW_1B, 0);
-      }
+fpga_pgm((uint8_t*)"/sd2snes/cx4.bit");
+  if(romprops.has_dspx || romprops.has_cx4) {
+    printf("DSPx game. Loading firmware image %s...\n", romprops.dsp_fw);
+    load_dspx(romprops.dsp_fw, romprops.fpga_features);
+    /* fallback to DSP1B firmware if DSP1.bin is not present */
+    if(file_res && romprops.dsp_fw == DSPFW_1) {
+      load_dspx(DSPFW_1B, romprops.fpga_features);
     }
     if(file_res) {
-      snes_menu_errmsg(MENU_ERR_NODSP, (void*)romprops.necdsp_fw);
+      snes_menu_errmsg(MENU_ERR_NODSP, (void*)romprops.dsp_fw);
     }
   }
   uint32_t rammask;
@@ -494,22 +492,29 @@ uint64_t sram_gettime(uint32_t base_addr) {
   return result & 0x00ffffffffffffffLL;
 }
 
-void load_dspx(const uint8_t *filename, uint8_t st0010) {
+void load_dspx(const uint8_t *filename, uint8_t coretype) {
   UINT bytes_read;
   DWORD filesize;
   uint16_t word_cnt;
   uint8_t wordsize_cnt = 0;
   uint16_t sector_remaining = 0;
   uint16_t sector_cnt = 0;
-  uint16_t pgmsize = 2048;
-  uint16_t datsize;
+  uint16_t pgmsize = 0;
+  uint16_t datsize = 0;
   uint32_t pgmdata = 0;
   uint16_t datdata = 0;
 
-  if(st0010) {
+  if(coretype & FEAT_ST0010) {
     datsize = 1536;
-  } else {
+    pgmsize = 2048;
+  } else if (coretype & FEAT_DSPX) {
     datsize = 1024;
+    pgmsize = 2048;
+  } else if (coretype & FEAT_CX4) {
+    datsize = 0;
+    pgmsize = 1024; /* Cx4 data ROM */
+  } else {
+    printf("load_dspx: unknown core (%02x)!\n", coretype);
   }
 
   file_open((uint8_t*)filename, FA_READ);
@@ -539,7 +544,7 @@ void load_dspx(const uint8_t *filename, uint8_t st0010) {
   }
 
   wordsize_cnt = 0;
-  if(st0010) {
+  if(coretype & FEAT_ST0010) {
     file_seek(0xc000);
     sector_remaining = 0;
   }

+ 14 - 8
src/smc.c

@@ -83,6 +83,7 @@ void smc_id(snes_romprops_t* props) {
 
   props->has_dspx = 0;
   props->has_st0010 = 0;
+  props->has_cx4 = 0;
   props->fpga_features = 0;
   for(uint8_t num = 0; num < 6; num++) {
     if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t))
@@ -144,39 +145,44 @@ void smc_id(snes_romprops_t* props) {
       props->mapper_id = 0;
       if(header->map == 0x31 && (header->carttype == 0x03 || header->carttype == 0x05)) {
         props->has_dspx = 1;
-        props->necdsp_fw = DSPFW_1B;
+        props->dsp_fw = DSPFW_1B;
         props->fpga_features |= FEAT_DSPX;
       }
       break;
 
     case 0x20: /* LoROM */
       props->mapper_id = 1;
-      if ((header->map == 0x20 && header->carttype == 0x03) ||
+      if (header->map == 0x20 && header->carttype == 0xf3) {
+        props->has_cx4 = 1;
+        props->dsp_fw = CX4FW;
+        props->fpga_features |= FEAT_CX4;
+      }
+      else if ((header->map == 0x20 && header->carttype == 0x03) ||
           (header->map == 0x30 && header->carttype == 0x05 && header->licensee != 0xb2)) {
         props->has_dspx = 1;
         props->fpga_features |= FEAT_DSPX;
         // Pilotwings uses DSP1 instead of DSP1B
         if(!memcmp(header->name, "PILOTWINGS", 10)) {
-          props->necdsp_fw = DSPFW_1;
+          props->dsp_fw = DSPFW_1;
         } else {
-          props->necdsp_fw = DSPFW_1B;
+          props->dsp_fw = DSPFW_1B;
         }
       } else if (header->map == 0x20 && header->carttype == 0x05) {
         props->has_dspx = 1;
-        props->necdsp_fw = DSPFW_2;
+        props->dsp_fw = DSPFW_2;
         props->fpga_features |= FEAT_DSPX;
       } else if (header->map == 0x30 && header->carttype == 0x05 && header->licensee == 0xb2) {
         props->has_dspx = 1;
-        props->necdsp_fw = DSPFW_3;
+        props->dsp_fw = DSPFW_3;
         props->fpga_features |= FEAT_DSPX;
       } else if (header->map == 0x30 && header->carttype == 0x03) {
         props->has_dspx = 1;
-        props->necdsp_fw = DSPFW_4;
+        props->dsp_fw = DSPFW_4;
         props->fpga_features |= FEAT_DSPX;
       } else if (header->map == 0x30 && header->carttype == 0xf6 && header->romsize >= 0xa) {
         props->has_dspx = 1;
         props->has_st0010 = 1;
-        props->necdsp_fw = DSPFW_ST0010;
+        props->dsp_fw = DSPFW_ST0010;
         props->fpga_features |= FEAT_ST0010;
         header->ramsize = 2;
       }

+ 3 - 1
src/smc.h

@@ -33,6 +33,7 @@
 #define DSPFW_4 ((const uint8_t*)"/sd2snes/dsp4.bin")
 #define DSPFW_1B ((const uint8_t*)"/sd2snes/dsp1b.bin")
 #define DSPFW_ST0010 ((const uint8_t*)"/sd2snes/st0010.bin")
+#define CX4FW ((const uint8_t*)"/sd2snes/cx4.bin")
 
 typedef struct _snes_header {
   uint8_t maker[2];     /* 0xB0 */
@@ -60,10 +61,11 @@ typedef struct _snes_romprops {
   uint32_t expramsize_bytes;  /* ExpRAM size in bytes */
   uint32_t ramsize_bytes;     /* CartRAM size in bytes */
   uint32_t romsize_bytes;     /* ROM size in bytes (rounded up) */
-  const uint8_t* necdsp_fw;   /* NEC DSP ROM filename */
+  const uint8_t* dsp_fw;      /* DSP (NEC / Hitachi) ROM filename */
   uint8_t has_dspx;           /* DSP[1-4] presence flag */
   uint8_t has_st0010;         /* st0010 presence flag (additional to dspx)*/
   uint8_t has_msu1;           /* MSU1 presence flag */
+  uint8_t has_cx4;            /* CX4 presence flag */
   uint8_t fpga_features;      /* feature/peripheral enable bits*/
   snes_header_t header;       /* original header from ROM image */
 } snes_romprops_t;

+ 19 - 19
verilog/sd2snes/sd2snes.xise

@@ -16,55 +16,55 @@
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
@@ -72,7 +72,7 @@
     </file>
     <file xil_pn:name="main_tf.v" xil_pn:type="FILE_VERILOG"/>
     <file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/>
@@ -90,11 +90,11 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
@@ -377,8 +377,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="12" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="12" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="8" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="8" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -433,7 +433,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|updtest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

+ 264 - 102
verilog/sd2snes_cx4/cx4.v

@@ -42,11 +42,12 @@ parameter BUSY_DMA   = 2'b01;
 parameter BUSY_CPU   = 2'b10;
 
 wire datram_enable = CS & (ADDR[11:0] < 12'hc00);
-wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11000);
-wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11000);
+wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11001);
+wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11001);
 wire vector_enable = CS & (ADDR[12:5] == 8'b11111011);
 wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11);
 wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000);
+wire debug_enable = CS & (&(ADDR[12:7]) && &(ADDR[5:4]));
 
 wire [7:0] DATRAM_DO;
 reg [7:0] MMIO_DOr;
@@ -54,12 +55,15 @@ wire [7:0] MMIO_DO;
 wire [7:0] STATUS_DO;
 wire [7:0] VECTOR_DO;
 wire [7:0] GPR_DO;
+wire [7:0] DEBUG_DO;
+reg [7:0] DEBUG_DOr;
 
 assign DO = datram_enable ? DATRAM_DO
             : mmio_enable ? MMIO_DO
             : status_enable ? STATUS_DO
             : vector_enable ? VECTOR_DO
             : gpr_enable ? GPR_DO
+            : debug_enable ? DEBUG_DO
             : 8'h00;
 
 /* 0x1f40 - 0x1f52: MMIO
@@ -87,7 +91,20 @@ wire [47:0] cpu_mul_result;
 reg [23:0] const [15:0];
 
 reg [15:0] cachetag [1:0]; // 15: valid; 14-0: bank number
+reg [14:0] cache_pgmpage;
+reg [14:0] cpu_cache_pgmpage;
+reg cache_cachepage;
+reg cpu_cache_cachepage;
+reg cpu_cache_done;
+reg [7:0] cpu_pc_stack [7:0];
+reg [7:0] cpu_page_stack;
+
 initial begin
+  cache_pgmpage = 15'b0;
+  cpu_cache_pgmpage = 15'b0;
+  cache_cachepage = 1'b0;
+  cpu_cache_cachepage = 1'b0;
+  cpu_cache_done = 1'b0;
   cachetag[0] = 16'h0000;
   cachetag[1] = 16'h0000;  
   cx4_busy = 3'b000;
@@ -112,12 +129,22 @@ initial begin
   const[13] = 24'hfeffff;
   const[14] = 24'h000100;
   const[15] = 24'h00feff;
+  cpu_pc_stack[0] = 8'b0;
+  cpu_pc_stack[1] = 8'b0;
+  cpu_pc_stack[2] = 8'b0;
+  cpu_pc_stack[3] = 8'b0;
+  cpu_pc_stack[4] = 8'b0;
+  cpu_pc_stack[5] = 8'b0;
+  cpu_pc_stack[6] = 8'b0;
+  cpu_pc_stack[7] = 8'b0;
+  cpu_page_stack = 8'b0;
 end
 
 assign MMIO_DO = MMIO_DOr;
 assign VECTOR_DO = vector [ADDR[4:0]];
 assign GPR_DO = gpr [ADDR[5:0]];
 assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0};
+assign DEBUG_DO = DEBUG_DOr;
 
 reg [7:0] DIr;
 always @(posedge CLK) DIr <= DI;
@@ -143,9 +170,11 @@ reg [23:0] cpu_idb; // tmp register for reg file read
 */
 reg CACHE_TRIG_ENr;
 reg CACHE_TRIG_EN2r;
+reg cpu_cache_en;
 initial begin
   CACHE_TRIG_ENr = 1'b0;
   CACHE_TRIG_EN2r = 1'b0;
+  cpu_cache_en = 1'b0;
 end
 always @(posedge CLK) CACHE_TRIG_EN2r <= CACHE_TRIG_ENr;
 wire CACHE_TRIG_EN = CACHE_TRIG_EN2r;
@@ -156,11 +185,19 @@ wire DMA_TRIG_EN = DMA_TRIG_ENr;
 
 reg CACHE_BUS_RRQr;
 reg DMA_BUS_RRQr;
+reg cpu_bus_rq;
+
 initial begin
   CACHE_BUS_RRQr = 1'b0;
   DMA_BUS_RRQr = 1'b0;
+  cpu_bus_rq = 1'b0;
 end
-assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr;
+
+assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr | cpu_bus_rq;
+
+reg cpu_page;
+reg [14:0] cpu_p;
+reg [7:0] cpu_pc;
 
 reg cpu_go_en_r;
 initial cpu_go_en_r = 1'b0;
@@ -192,23 +229,31 @@ always @(posedge CLK) begin
     5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50
     5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51};      // 1f51
     5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52};      // 1f52    
-
-    5'h13: MMIO_DOr <= cpu_mul_result[47:40];   // 1f40
-    5'h14: MMIO_DOr <= cpu_mul_result[39:32];   // 1f40
-    5'h15: MMIO_DOr <= cpu_mul_result[31:24];   // 1f40
-    5'h16: MMIO_DOr <= cpu_mul_result[23:16];   // 1f40
-    5'h17: MMIO_DOr <= cpu_mul_result[15:8];   // 1f40
-    5'h18: MMIO_DOr <= cpu_mul_result[7:0];   // 1f40
-
-   
-//   5'h14: MMIO_DOr <= cachetag[0][15:8];   // 1f40
-//   5'h15: MMIO_DOr <= cachetag[0][7:0];  // 1f41
-//   5'h16: MMIO_DOr <= cachetag[1][15:8]; // 1f42
-//   5'h17: MMIO_DOr <= cachetag[1][7:0];   // 1f43
     default: MMIO_DOr <= 8'hff;
   endcase
 end
 
+always @(posedge CLK) begin
+  case(ADDR[3:0])
+    4'h0: DEBUG_DOr <= cachetag[0][15:8];   // 1f40
+    4'h1: DEBUG_DOr <= cachetag[0][7:0];  // 1f41
+    4'h2: DEBUG_DOr <= cachetag[1][15:8]; // 1f42
+    4'h3: DEBUG_DOr <= cachetag[1][7:0];   // 1f43
+    4'h4: DEBUG_DOr <= cpu_page;
+    4'h5: DEBUG_DOr <= cpu_p;
+    4'h6: DEBUG_DOr <= cpu_pc;
+    4'h7: DEBUG_DOr <= cx4_busy;
+    4'h8: DEBUG_DOr <= cpu_page_stack[0];
+    4'h9: DEBUG_DOr <= cpu_pc_stack[0];
+    4'ha: DEBUG_DOr <= cpu_page_stack[1];
+    4'hb: DEBUG_DOr <= cpu_pc_stack[1];
+    4'hc: DEBUG_DOr <= cpu_page_stack[2];
+    4'hd: DEBUG_DOr <= cpu_pc_stack[2];
+    4'he: DEBUG_DOr <= cpu_page_stack[3];
+    4'hf: DEBUG_DOr <= cpu_pc_stack[3];
+  endcase
+end
+
 always @(posedge CLK) begin
   if(MMIO_WR_EN) begin
     case(ADDR[4:0])
@@ -272,10 +317,11 @@ reg [23:0] CACHE_SRC_ADDRr;
 wire [22:0] MAPPED_CACHE_SRC_ADDR = {CACHE_SRC_ADDRr[23:16],CACHE_SRC_ADDRr[14:0]};
 reg [23:0] DMA_SRC_ADDRr;
 wire [22:0] MAPPED_DMA_SRC_ADDR = {DMA_SRC_ADDRr[23:16],DMA_SRC_ADDRr[14:0]};
+wire [22:0] MAPPED_CPU_BUS_ADDR;
 
 assign BUS_ADDR =  cx4_busy[BUSY_CACHE] ? MAPPED_CACHE_SRC_ADDR
                  : cx4_busy[BUSY_DMA] ? MAPPED_DMA_SRC_ADDR
-                 : 24'h800000 /* XXX cx4_bus_addr */;
+                 : MAPPED_CPU_BUS_ADDR;
 
 reg cx4_pgmrom_we;
 initial cx4_pgmrom_we = 1'b0;
@@ -288,15 +334,24 @@ always @(posedge CLK) begin
     ST_CACHE_IDLE: begin
       if(CACHE_TRIG_EN 
          & (~cachetag[cx4_mmio_cachepage][15]
-            | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage)))
-      begin
+            | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) begin
         CACHE_ST <= ST_CACHE_START;
-      end else CACHE_ST <= ST_CACHE_IDLE;
+        cache_pgmpage <= cx4_mmio_pgmpage;
+        cache_cachepage <= cx4_mmio_cachepage;
+      end else if(cpu_cache_en
+         & (~cachetag[~cpu_page][15]
+            | |(cachetag[~cpu_page][14:0] ^ cpu_p))) begin
+        CACHE_ST <= ST_CACHE_START;
+        cache_pgmpage <= cpu_p;
+        cache_cachepage <= ~cpu_page;
+        cx4_busy[BUSY_CACHE] <= 1'b1;
+      end
+      else CACHE_ST <= ST_CACHE_IDLE;
     end
     ST_CACHE_START: begin
       cx4_busy[BUSY_CACHE] <= 1'b1;
-      CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cx4_mmio_pgmpage, 9'b0};
-      cx4_pgmrom_addr <= {cx4_mmio_cachepage, 9'b0};
+      CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cache_pgmpage, 9'b0};
+      cx4_pgmrom_addr <= {cache_cachepage, 9'b0};
       CACHE_ST <= ST_CACHE_WAIT;
       cache_count <= 10'b0;
       CACHE_BUS_RRQr <= 1'b1;
@@ -315,7 +370,7 @@ always @(posedge CLK) begin
       cx4_pgmrom_addr <= cx4_pgmrom_addr + 1;
       if(cache_count == 9'h1ff) begin
         cx4_busy[BUSY_CACHE] <= 1'b0;
-        cachetag[cx4_mmio_cachepage] <= {1'b1,cx4_mmio_pgmpage};
+        cachetag[cache_cachepage] <= {1'b1,cache_pgmpage};
         CACHE_ST <= ST_CACHE_IDLE;
       end else begin
         CACHE_BUS_RRQr <= 1'b1;
@@ -334,7 +389,7 @@ reg [11:0] cx4_dma_datram_addr;
 reg [11:0] cx4_cpu_datram_addr;
 wire [11:0] cx4_datram_addr = cx4_busy[BUSY_DMA] ? cx4_dma_datram_addr : cx4_cpu_datram_addr;
 reg [23:0] cx4_cpu_datram_di;
-wire [23:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di;
+wire [7:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di;
 reg [15:0] dma_count;
 initial dma_count = 16'b0;
 
@@ -380,10 +435,8 @@ end
  =========== CPU ===========
  ***************************/
 reg [4:0] CPU_STATE;
-reg cpu_page;
-reg [7:0] cpu_pc;
-reg [8:0] cpu_stack [7:0];
 reg [2:0] cpu_sp;
+initial cpu_sp = 3'b000;
 wire [15:0] cpu_op_w;
 reg [15:0] cpu_op;
 reg [23:0] cpu_a;
@@ -391,17 +444,20 @@ reg [23:0] cpu_busdata;
 reg [23:0] cpu_romdata;
 reg [23:0] cpu_ramdata;
 reg [23:0] cpu_busaddr;
+assign MAPPED_CPU_BUS_ADDR = {cpu_busaddr[23:16], cpu_busaddr[14:0]};
 reg [23:0] cpu_romaddr;
 reg [23:0] cpu_ramaddr;
 reg [23:0] cpu_acch;
 reg [23:0] cpu_accl;
 reg [23:0] cpu_mul_src;
+reg [24:0] cpu_alu_res;
+reg [23:0] cpu_dummy;
+reg [23:0] cpu_tmp;
 
 reg [23:0] cpu_sa;  // tmp register for shifted accumulator
 reg fl_n;
 reg fl_z;
 reg fl_c;
-reg [15:0] cpu_p;
 
 wire [9:0] cx4_datrom_addr = cpu_a[9:0];
 wire [23:0] cx4_datrom_do;
@@ -413,49 +469,63 @@ parameter ST_CPU_1    = 5'b00100;
 parameter ST_CPU_2    = 5'b01000;
 parameter ST_CPU_3    = 5'b10000;
 
-initial CPU_STATE <= ST_CPU_IDLE;
-
-parameter OP_NOP   = 4'b0000;
-parameter OP_JP    = 4'b0001;
-parameter OP_SKIP  = 4'b0010;
-parameter OP_RT    = 4'b0011;
-parameter OP_LD    = 4'b0100;
-parameter OP_ST    = 4'b0101;
-parameter OP_SWP   = 4'b0110;
-parameter OP_RDROM = 4'b0111;
-parameter OP_RDRAM = 4'b1000;
-parameter OP_WRRAM = 4'b1001;
-parameter OP_ALU   = 4'b1010;
-parameter OP_MUL   = 4'b1011;
-parameter OP_WAI   = 4'b1100;
-parameter OP_BUS   = 4'b1101;
-parameter OP_HLT   = 4'b1110;
+initial CPU_STATE = ST_CPU_IDLE;
+
+parameter OP_NOP   = 5'b00000;
+parameter OP_JP    = 5'b00001;
+parameter OP_SKIP  = 5'b00010;
+parameter OP_RT    = 5'b00011;
+parameter OP_LD    = 5'b00100;
+parameter OP_ST    = 5'b00101;
+parameter OP_SWP   = 5'b00110;
+parameter OP_RDROM = 5'b00111;
+parameter OP_RDRAM = 5'b01000;
+parameter OP_WRRAM = 5'b01001;
+parameter OP_ALU   = 5'b01010;
+parameter OP_MUL   = 5'b01011;
+parameter OP_WAI   = 5'b01100;
+parameter OP_BUS   = 5'b01101;
+parameter OP_CMP   = 5'b01110;
+parameter OP_SEX   = 5'b01111;
+parameter OP_HLT   = 5'b10000;
 
 wire [6:0] op_id = cpu_op_w[15:10];
 reg [7:0] op_param;
-reg [3:0] op;
+reg [4:0] op;
 reg [1:0] op_sa;
 reg op_imm;
 reg op_p;
 reg op_call;
 reg op_jump;
 reg condtrue;
-reg cpu_bus_rq;
+
+/* XXX DEBUG */
+reg [23:0] dbg_cnt;
+initial dbg_cnt = 24'b0;
+always @(posedge CLK) dbg_cnt <= dbg_cnt + 1;
+wire step_enable = 1'b1;
 
 always @(posedge CLK) begin
+  if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1;
+  else if((op == OP_HLT) && step_enable) cx4_busy[BUSY_CPU] <= 1'b0;
+end
+
+always @(posedge CLK) begin
+if(step_enable | cpu_go_en_r) begin
   case(CPU_STATE)
     ST_CPU_IDLE: begin
       if(cpu_go_en_r) begin
         cpu_pc <= cx4_mmio_pc;
+        cpu_page <= cx4_mmio_cachepage;
+        cpu_p <= cx4_mmio_pgmpage;
         op <= OP_NOP;
         CPU_STATE <= ST_CPU_2;
-        cx4_busy[BUSY_CPU] <= 1'b1;
       end
       else CPU_STATE <= ST_CPU_IDLE;
     end
     ST_CPU_0: begin // Phase 0: 
+      cpu_cache_en <= 1'b0;
       if(op == OP_HLT) begin
-        cx4_busy[BUSY_CPU] <= 1'b0;
         CPU_STATE <= ST_CPU_IDLE;
       end
       else CPU_STATE <= ST_CPU_1;
@@ -475,7 +545,7 @@ always @(posedge CLK) begin
             2'b11: condtrue <= (fl_n == cpu_op[0]);
           endcase
         end
-        OP_LD, OP_SWP, OP_ALU, OP_MUL: begin
+        OP_LD, OP_ALU, OP_MUL, OP_CMP, OP_SEX: begin
           if(op_imm) cpu_idb <= {16'b0, op_param};
           else casex(op_param)
             8'h00: cpu_idb <= cpu_a;
@@ -492,7 +562,7 @@ always @(posedge CLK) begin
                                gpr[op_param[3:0]*3]};
             default: cpu_idb <= 24'b0;
           endcase
-          if(op==OP_ALU) begin
+          if(op==OP_ALU || op==OP_CMP) begin
             case(op_sa)
               2'b00: cpu_sa <= cpu_a;
               2'b01: cpu_sa <= cpu_a << 1;
@@ -504,8 +574,26 @@ always @(posedge CLK) begin
         OP_ST: begin
           cpu_idb <= cpu_a;
         end
+        OP_SWP: begin
+          cpu_idb <= cpu_a;
+          casex(op_param)
+            8'h00: cpu_tmp <= cpu_a;
+            8'h01: cpu_tmp <= cpu_acch;
+            8'h02: cpu_tmp <= cpu_accl;
+            8'h03: cpu_tmp <= cpu_busdata;
+            8'h08: cpu_tmp <= cpu_romdata;
+            8'h0c: cpu_tmp <= cpu_ramdata;
+            8'h13: cpu_tmp <= cpu_busaddr;
+            8'h1c: cpu_tmp <= cpu_ramaddr;
+            8'h5x: cpu_tmp <= const[op_param[3:0]];
+            8'h6x: cpu_tmp <= {gpr[op_param[3:0]*3+2],
+                               gpr[op_param[3:0]*3+1],
+                               gpr[op_param[3:0]*3]};
+            default: cpu_tmp <= 24'b0;
+          endcase
+        end
         OP_RDRAM, OP_WRRAM: begin
-          if(op_imm) cpu_ramaddr <= {16'b0, op_param};
+          if(op_imm) cx4_cpu_datram_addr <= {16'b0, op_param} + cpu_ramaddr;
           else casex(op_param)
             8'h00: cx4_cpu_datram_addr <= cpu_a;
             8'h01: cx4_cpu_datram_addr <= cpu_acch;
@@ -522,32 +610,39 @@ always @(posedge CLK) begin
             default: cx4_cpu_datram_addr <= 24'b0;
           endcase
         end
+        OP_BUS: cpu_bus_rq <= 1'b1;
       endcase
     end
     ST_CPU_1: begin
       CPU_STATE <= ST_CPU_2;
       case(op)
         OP_JP: begin
-          if(condtrue) begin
-            if(op_call) begin
-              cpu_stack[cpu_sp] <= cpu_pc + 1;
-              cpu_sp <= cpu_sp + 1;
-            end
-            cpu_pc <= op_param;
+          if(!cx4_busy[BUSY_CACHE]) begin
+            if(condtrue) begin
+              if(op_call) begin
+                cpu_page_stack[cpu_sp] <= cpu_page;
+                cpu_pc_stack[cpu_sp] <= cpu_pc + 1;
+                cpu_sp <= cpu_sp + 1;
+              end
+              cpu_pc <= op_param;
+              cpu_page <= cpu_page ^ op_p;
+            end else cpu_pc <= cpu_pc + 1;
           end
         end
         OP_SKIP: begin
-          if(condtrue) begin
-            cpu_pc <= cpu_pc + 2;
-          end
+          if(condtrue) cpu_pc <= cpu_pc + 2;
+          else cpu_pc <= cpu_pc + 1;
         end
         OP_RT: begin
-          cpu_pc <= cpu_stack[cpu_sp - 1];
+          cpu_page <= cpu_page_stack[cpu_sp - 1];
+          cpu_pc <= cpu_pc_stack[cpu_sp - 1];
           cpu_sp <= cpu_sp - 1;
         end
-        OP_LD, OP_ST, OP_SWP, OP_RDROM, OP_RDRAM, OP_WRRAM, OP_ALU, OP_MUL, OP_BUS:
-          cpu_pc <= cpu_pc + 1;
         OP_WAI: if(BUS_RDY) cpu_pc <= cpu_pc + 1;
+        OP_BUS: begin 
+          cpu_bus_rq <= 1'b0;
+          cpu_pc <= cpu_pc + 1;
+        end
         default: cpu_pc <= cpu_pc + 1;
       endcase
     end
@@ -559,56 +654,101 @@ always @(posedge CLK) begin
             4'b0x00: cpu_a <= cpu_idb;
             4'b0x11: cpu_p <= cpu_idb;
             4'b1100: cpu_p[7:0] <= op_param;
-            4'b1101: cpu_p[15:8] <= op_param;
+            4'b1101: cpu_p[14:8] <= op_param;
           endcase
         end
-        OP_ST: begin
-          casex(op_param)
-            8'h00: cpu_a <= cpu_idb;
+        OP_ST, OP_SWP: begin
+          casex(op_param)                                    
+//            8'h00: cpu_a <= cpu_idb;
             8'h01: cpu_acch <= cpu_idb;
             8'h02: cpu_accl <= cpu_idb;
-            8'h03: cpu_busdata <= cpu_idb;
+//            8'h03: cpu_busdata <= cpu_idb;
             8'h08: cpu_romdata <= cpu_idb;
             8'h0c: cpu_ramdata <= cpu_idb;
             8'h13: cpu_busaddr <= cpu_idb;
             8'h1c: cpu_ramaddr <= cpu_idb;
           endcase
+          if(op==OP_SWP) cpu_a <= cpu_tmp;
         end
-        OP_SWP: begin
-          casex(op_param)
-            8'h00: cpu_a <= cpu_a;
-            8'h01: cpu_acch <= cpu_a;
-            8'h02: cpu_accl <= cpu_a;
-            8'h03: cpu_busdata <= cpu_a;
-            8'h08: cpu_romdata <= cpu_a;
-            8'h0c: cpu_ramdata <= cpu_a;
-            8'h13: cpu_busaddr <= cpu_a;
-            8'h1c: cpu_ramaddr <= cpu_a;
+        OP_RDROM: cpu_romdata <= cx4_datrom_do;
+        OP_RDRAM: begin
+          case(cpu_op[9:8])
+            2'b00: cpu_ramdata[7:0] <= cx4_datram_do;
+            2'b01: cpu_ramdata[15:8] <= cx4_datram_do;
+            2'b10: cpu_ramdata[23:16] <= cx4_datram_do;
           endcase
         end
-        OP_RDROM: cpu_romdata <= cx4_datrom_do;
-        OP_RDRAM: cpu_ramdata <= cx4_datram_do;
         OP_WRRAM: begin
           case(cpu_op[9:8])
-            2'b00: cx4_cpu_datram_di[7:0] <= cpu_ramdata[7:0];
-            2'b01: cx4_cpu_datram_di[15:8] <= cpu_ramdata[15:8];
-            2'b10: cx4_cpu_datram_di[23:16] <= cpu_ramdata[23:16];
+            2'b00: cx4_cpu_datram_di <= cpu_ramdata[7:0];
+            2'b01: cx4_cpu_datram_di <= cpu_ramdata[15:8];
+            2'b10: cx4_cpu_datram_di <= cpu_ramdata[23:16];
           endcase
           cx4_cpu_datram_we <= 1'b1;
         end
+        OP_CMP: begin
+          case(cpu_op[15:11])
+            5'b01001: cpu_alu_res <= cpu_idb - cpu_sa;
+            5'b01010: cpu_alu_res <= cpu_sa - cpu_idb;
+          endcase
+        end
+        OP_SEX: begin
+          case(cpu_op[9:8])
+            2'b01: cpu_alu_res <= {{16{cpu_idb[7]}}, cpu_idb[7:0]};
+            2'b10: cpu_alu_res <= {{8{cpu_idb[15]}}, cpu_idb[15:0]};
+          endcase
+        end
         OP_ALU: begin
-        /* XXX TODO FUCK YEAH ALU */
+          case(cpu_op[15:11])
+            5'b10000: cpu_alu_res <= cpu_sa + cpu_idb;
+            5'b10001: cpu_alu_res <= cpu_idb - cpu_sa;
+            5'b10010: cpu_alu_res <= cpu_sa - cpu_idb;
+            5'b10101: cpu_alu_res <= cpu_sa ^ cpu_idb;
+            5'b10110: cpu_alu_res <= cpu_sa & cpu_idb;
+            5'b10111: cpu_alu_res <= cpu_sa | cpu_idb;
+            5'b11000: cpu_alu_res <= cpu_a >> cpu_idb;
+            5'b11001: cpu_alu_res <= $signed(cpu_a) >>> cpu_idb;
+            5'b11010: {cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb;
+            5'b11011: cpu_alu_res <= cpu_a << cpu_idb;
+          endcase
         end
-        OP_BUS: cpu_bus_rq <= 1'b1;
       endcase
     end
     ST_CPU_3: begin
       CPU_STATE <= ST_CPU_0;
       case(op)
-        OP_SWP: cpu_a <= cpu_idb;
+        OP_LD: begin
+          casex(cpu_op[11:8])
+            4'b0x11: cpu_cache_en <= 1'b1;
+            4'b1100: cpu_cache_en <= 1'b1;
+          endcase
+        end
+        OP_BUS: cpu_busaddr <= cpu_busaddr + 1;
         OP_WRRAM: cx4_cpu_datram_we <= 1'b0;
+        OP_CMP: begin
+          fl_n <= cpu_alu_res[23];
+          fl_z <= cpu_alu_res[23:0] == 24'b0;
+          fl_c <= ~cpu_alu_res[24];
+        end
+        OP_SEX: cpu_a <= cpu_alu_res[23:0];
         OP_ALU: begin
-        /* XXX TODO FUCKING FLAGS */
+          cpu_a <= cpu_alu_res[23:0];
+          case(cpu_op[15:11])
+            5'b10000: begin
+              fl_n <= cpu_alu_res[23];
+              fl_z <= cpu_alu_res[23:0] == 24'b0;
+              fl_c <= cpu_alu_res[24];
+            end
+            5'b10001, 5'b10010: begin
+              fl_n <= cpu_alu_res[23];
+              fl_z <= cpu_alu_res[23:0] == 24'b0;
+              fl_c <= ~cpu_alu_res[24];
+            end
+            default: begin
+              fl_n <= cpu_alu_res[23];
+              fl_z <= cpu_alu_res[23:0] == 24'b0;
+            end
+          endcase
         end
         OP_MUL: begin
           cpu_acch <= cpu_mul_result[47:24];
@@ -616,7 +756,6 @@ always @(posedge CLK) begin
           fl_z <= (cpu_mul_result == 48'b0);
           fl_n <= cpu_mul_result[47];
         end
-        OP_BUS: cpu_bus_rq <= 1'b0;
       endcase
       cpu_op <= cpu_op_w;
       casex(cpu_op_w[15:11])
@@ -636,9 +775,9 @@ always @(posedge CLK) begin
         5'b01101: op <= OP_RDRAM;
         5'b11101: op <= OP_WRRAM;
 
-        5'b01001: op <= OP_ALU;
-        5'b01010: op <= OP_ALU;
-        5'b01011: op <= OP_ALU;
+        5'b01001: op <= OP_CMP;
+        5'b01010: op <= OP_CMP;
+        5'b01011: op <= OP_SEX;
         5'b10000: op <= OP_ALU;
         5'b10001: op <= OP_ALU;
         5'b10010: op <= OP_ALU;
@@ -659,22 +798,45 @@ always @(posedge CLK) begin
       op_imm <= cpu_op_w[10];
       op_p <= cpu_op_w[9];
       op_call <= cpu_op_w[13];
+      op_param <= cpu_op_w[7:0];
+      op_sa <= cpu_op_w[9:8];
     end
   endcase
 end
+end
+
+reg[2:0] BUSRD_STATE;
+parameter ST_BUSRD_IDLE = 2'b01;
+parameter ST_BUSRD_WAIT = 2'b10;
+initial BUSRD_STATE = ST_BUSRD_IDLE;
 
-// gpr write, either by CPU or by MMIO
 always @(posedge CLK) begin
   if(CPU_STATE == ST_CPU_2
-     && (op == OP_SWP)
-     && (op_param[7:4] == 8'h6)) begin
-    gpr[op_param[3:0]*3+2] <= cpu_a[23:16];
-    gpr[op_param[3:0]*3+1] <= cpu_a[15:8];
-    gpr[op_param[3:0]*3] <= cpu_a[7:0];
+     && (op == OP_ST || op == OP_SWP)
+     && op_param == 8'h03)
+    cpu_busdata <= cpu_idb;
+  else begin
+    case(BUSRD_STATE)
+      ST_BUSRD_IDLE: begin
+        if(cpu_bus_rq) begin
+         BUSRD_STATE <= ST_BUSRD_WAIT;
+        end
+      end
+      ST_BUSRD_WAIT: begin
+        if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_IDLE;
+        else BUSRD_STATE <= ST_BUSRD_WAIT;
+        if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI;
+        else cpu_busdata <= 8'h00;
+      end
+    endcase
   end
-  else if(CPU_STATE == ST_CPU_2
-          && (op == OP_ST)
-          && (op_param[7:4] == 8'h6)) begin
+end
+
+// gpr write, either by CPU or by MMIO
+always @(posedge CLK) begin
+  if(CPU_STATE == ST_CPU_2
+          && (op == OP_ST || op == OP_SWP)
+          && (op_param[7:4] == 4'h6)) begin
     gpr[op_param[3:0]*3+2] <= cpu_idb[23:16];
     gpr[op_param[3:0]*3+1] <= cpu_idb[15:8];
     gpr[op_param[3:0]*3] <= cpu_idb[7:0];
@@ -714,7 +876,7 @@ cx4_pgmrom cx4_pgmrom (
   .addra(cx4_pgmrom_addr), // input [9 : 0] addra
   .dina(BUS_DI), // input [7 : 0] dina
   .clkb(CLK), // input clkb
-  .addrb(cpu_pc), // input [8 : 0] addrb
+  .addrb({cpu_page,cpu_pc}), // input [8 : 0] addrb
   .doutb(cpu_op_w) // output [15 : 0] doutb
 );
 

+ 1409 - 957
verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v

@@ -7,7 +7,7 @@
 // \   \   \/     Version: O.61xd
 //  \   \         Application: netgen
 //  /   /         Filename: cx4_mul.v
-// /___/   /\     Timestamp: Fri Oct 21 22:38:27 2011
+// /___/   /\     Timestamp: Tue Oct 25 00:04:23 2011
 // \   \  /  \ 
 //  \___\/\___\
 //             
@@ -399,6 +399,54 @@ module cx4_mul (
   wire sig00000162;
   wire sig00000163;
   wire sig00000164;
+  wire sig00000165;
+  wire sig00000166;
+  wire sig00000167;
+  wire sig00000168;
+  wire sig00000169;
+  wire sig0000016a;
+  wire sig0000016b;
+  wire sig0000016c;
+  wire sig0000016d;
+  wire sig0000016e;
+  wire sig0000016f;
+  wire sig00000170;
+  wire sig00000171;
+  wire sig00000172;
+  wire sig00000173;
+  wire sig00000174;
+  wire sig00000175;
+  wire sig00000176;
+  wire sig00000177;
+  wire sig00000178;
+  wire sig00000179;
+  wire sig0000017a;
+  wire sig0000017b;
+  wire sig0000017c;
+  wire sig0000017d;
+  wire sig0000017e;
+  wire sig0000017f;
+  wire sig00000180;
+  wire sig00000181;
+  wire sig00000182;
+  wire sig00000183;
+  wire sig00000184;
+  wire sig00000185;
+  wire sig00000186;
+  wire sig00000187;
+  wire sig00000188;
+  wire sig00000189;
+  wire sig0000018a;
+  wire sig0000018b;
+  wire sig0000018c;
+  wire sig0000018d;
+  wire sig0000018e;
+  wire sig0000018f;
+  wire sig00000190;
+  wire sig00000191;
+  wire sig00000192;
+  wire sig00000193;
+  wire sig00000194;
   wire \NLW_blk00000003_P<35>_UNCONNECTED ;
   wire \NLW_blk00000003_P<34>_UNCONNECTED ;
   wire \NLW_blk00000003_P<33>_UNCONNECTED ;
@@ -447,15 +495,15 @@ module cx4_mul (
   wire \NLW_blk00000005_P<24>_UNCONNECTED ;
   wire \NLW_blk00000006_P<35>_UNCONNECTED ;
   GND   blk00000001 (
-    .G(sig00000001)
+    .G(sig00000012)
   );
   VCC   blk00000002 (
-    .P(sig00000002)
+    .P(sig00000013)
   );
   MULT18X18S   blk00000003 (
     .C(clk),
-    .CE(sig00000002),
-    .R(sig00000001),
+    .CE(sig00000013),
+    .R(sig00000012),
     .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
     .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
     .P({\NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED , 
@@ -463,1973 +511,2377 @@ module cx4_mul (
 \NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED , 
 \NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED , 
 \NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED , 
-\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000e5, sig000000e4, sig000000e3, 
-sig000000e2, sig000000ee, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e1})
+\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000f6, sig000000f5, sig000000f4, 
+sig000000f3, sig000000ff, sig000000fe, sig000000fd, sig000000fc, sig000000fb, sig000000fa, sig000000f9, sig000000f8, sig000000f7, sig000000f2})
   );
   MULT18X18S   blk00000004 (
     .C(clk),
-    .CE(sig00000002),
-    .R(sig00000001),
+    .CE(sig00000013),
+    .R(sig00000012),
     .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
-    .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+    .B({sig00000012, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
     .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , 
 \NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , 
 \NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , 
-\NLW_blk00000004_P<24>_UNCONNECTED , sig000000d8, sig000000d7, sig000000d6, sig000000d5, sig000000d3, sig000000d2, sig000000d1, sig000000d0, 
-sig000000cf, sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, 
-sig000000db, sig000000da, sig000000d9, sig000000d4, sig000000c9})
+\NLW_blk00000004_P<24>_UNCONNECTED , sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e4, sig000000e3, sig000000e2, sig000000e1, 
+sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, sig000000db, sig000000f1, sig000000f0, sig000000ef, sig000000ee, sig000000ed, 
+sig000000ec, sig000000eb, sig000000ea, sig000000e5, sig000000da})
   );
   MULT18X18S   blk00000005 (
     .C(clk),
-    .CE(sig00000002),
-    .R(sig00000001),
-    .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
+    .CE(sig00000013),
+    .R(sig00000012),
+    .A({sig00000012, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
     .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
     .P({\NLW_blk00000005_P<35>_UNCONNECTED , \NLW_blk00000005_P<34>_UNCONNECTED , \NLW_blk00000005_P<33>_UNCONNECTED , 
 \NLW_blk00000005_P<32>_UNCONNECTED , \NLW_blk00000005_P<31>_UNCONNECTED , \NLW_blk00000005_P<30>_UNCONNECTED , \NLW_blk00000005_P<29>_UNCONNECTED , 
 \NLW_blk00000005_P<28>_UNCONNECTED , \NLW_blk00000005_P<27>_UNCONNECTED , \NLW_blk00000005_P<26>_UNCONNECTED , \NLW_blk00000005_P<25>_UNCONNECTED , 
-\NLW_blk00000005_P<24>_UNCONNECTED , sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bb, sig000000ba, sig000000b9, sig000000b8, 
-sig000000b7, sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, 
-sig000000c3, sig000000c2, sig000000c1, sig000000bc, sig000000b1})
+\NLW_blk00000005_P<24>_UNCONNECTED , sig000000d1, sig000000d0, sig000000cf, sig000000ce, sig000000cc, sig000000cb, sig000000ca, sig000000c9, 
+sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, sig000000c3, sig000000d9, sig000000d8, sig000000d7, sig000000d6, sig000000d5, 
+sig000000d4, sig000000d3, sig000000d2, sig000000cd, sig000000c2})
   );
   MULT18X18S   blk00000006 (
     .C(clk),
-    .CE(sig00000002),
-    .R(sig00000001),
-    .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
-    .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
-    .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000a9, sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a3, sig000000a2, sig000000a1, 
-sig000000a0, sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000098, sig00000097, sig00000096, sig00000095, 
-sig00000094, sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, 
-sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
+    .CE(sig00000013),
+    .R(sig00000012),
+    .A({sig00000012, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
+    .B({sig00000012, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+    .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000ba, sig000000b9, sig000000b8, sig000000b7, sig000000b6, sig000000b4, sig000000b3, sig000000b2, 
+sig000000b1, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, sig000000ab, sig000000a9, sig000000a8, sig000000a7, sig000000a6, 
+sig000000a5, sig000000a4, sig000000a3, sig000000a2, sig000000a1, sig000000a0, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, 
+sig000000bc, sig000000bb, sig000000b5, sig000000aa, sig0000009f})
   );
   XORCY   blk00000007 (
-    .CI(sig00000065),
-    .LI(sig00000086),
-    .O(p[47])
+    .CI(sig00000076),
+    .LI(sig00000097),
+    .O(sig0000018f)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000008 (
-    .I0(sig0000014e),
-    .I1(sig0000015b),
-    .O(sig00000086)
+    .I0(sig0000016c),
+    .I1(sig0000015f),
+    .O(sig00000097)
   );
   MUXCY   blk00000009 (
-    .CI(sig00000064),
-    .DI(sig0000014e),
-    .S(sig00000085),
-    .O(sig00000065)
+    .CI(sig00000075),
+    .DI(sig0000015f),
+    .S(sig00000096),
+    .O(sig00000076)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000000a (
-    .I0(sig0000014e),
-    .I1(sig0000015b),
-    .O(sig00000085)
+    .I0(sig0000016c),
+    .I1(sig0000015f),
+    .O(sig00000096)
   );
   MUXCY   blk0000000b (
-    .CI(sig00000062),
-    .DI(sig0000014e),
-    .S(sig00000084),
-    .O(sig00000064)
+    .CI(sig00000073),
+    .DI(sig0000015f),
+    .S(sig00000095),
+    .O(sig00000075)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000000c (
-    .I0(sig0000014e),
-    .I1(sig0000015b),
-    .O(sig00000084)
+    .I0(sig0000016c),
+    .I1(sig0000015f),
+    .O(sig00000095)
   );
   XORCY   blk0000000d (
-    .CI(sig00000061),
-    .LI(sig00000082),
-    .O(p[46])
+    .CI(sig00000072),
+    .LI(sig00000093),
+    .O(sig0000018b)
   );
   MUXCY   blk0000000e (
-    .CI(sig00000061),
-    .DI(sig0000014e),
-    .S(sig00000082),
-    .O(sig00000062)
+    .CI(sig00000072),
+    .DI(sig0000015f),
+    .S(sig00000093),
+    .O(sig00000073)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000000f (
-    .I0(sig0000014e),
-    .I1(sig0000015a),
-    .O(sig00000082)
+    .I0(sig0000016b),
+    .I1(sig0000015f),
+    .O(sig00000093)
   );
   XORCY   blk00000010 (
-    .CI(sig00000060),
-    .LI(sig00000081),
-    .O(p[45])
+    .CI(sig00000071),
+    .LI(sig00000092),
+    .O(sig0000018a)
   );
   MUXCY   blk00000011 (
-    .CI(sig00000060),
-    .DI(sig0000014e),
-    .S(sig00000081),
-    .O(sig00000061)
+    .CI(sig00000071),
+    .DI(sig0000015f),
+    .S(sig00000092),
+    .O(sig00000072)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000012 (
-    .I0(sig0000014e),
-    .I1(sig00000159),
-    .O(sig00000081)
+    .I0(sig0000016a),
+    .I1(sig0000015f),
+    .O(sig00000092)
   );
   XORCY   blk00000013 (
-    .CI(sig0000005f),
-    .LI(sig00000080),
-    .O(p[44])
+    .CI(sig00000070),
+    .LI(sig00000091),
+    .O(sig00000189)
   );
   MUXCY   blk00000014 (
-    .CI(sig0000005f),
-    .DI(sig0000014e),
-    .S(sig00000080),
-    .O(sig00000060)
+    .CI(sig00000070),
+    .DI(sig0000015f),
+    .S(sig00000091),
+    .O(sig00000071)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000015 (
-    .I0(sig0000014e),
-    .I1(sig00000158),
-    .O(sig00000080)
+    .I0(sig00000169),
+    .I1(sig0000015f),
+    .O(sig00000091)
   );
   XORCY   blk00000016 (
-    .CI(sig0000005e),
-    .LI(sig0000007f),
-    .O(p[43])
+    .CI(sig0000006f),
+    .LI(sig00000090),
+    .O(sig00000188)
   );
   MUXCY   blk00000017 (
-    .CI(sig0000005e),
-    .DI(sig0000014e),
-    .S(sig0000007f),
-    .O(sig0000005f)
+    .CI(sig0000006f),
+    .DI(sig0000015f),
+    .S(sig00000090),
+    .O(sig00000070)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000018 (
-    .I0(sig0000014e),
-    .I1(sig00000164),
-    .O(sig0000007f)
+    .I0(sig00000175),
+    .I1(sig0000015f),
+    .O(sig00000090)
   );
   XORCY   blk00000019 (
-    .CI(sig0000005d),
-    .LI(sig0000007e),
-    .O(p[42])
+    .CI(sig0000006e),
+    .LI(sig0000008f),
+    .O(sig00000187)
   );
   MUXCY   blk0000001a (
-    .CI(sig0000005d),
-    .DI(sig0000014e),
-    .S(sig0000007e),
-    .O(sig0000005e)
+    .CI(sig0000006e),
+    .DI(sig0000015f),
+    .S(sig0000008f),
+    .O(sig0000006f)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000001b (
-    .I0(sig0000014e),
-    .I1(sig00000163),
-    .O(sig0000007e)
+    .I0(sig00000174),
+    .I1(sig0000015f),
+    .O(sig0000008f)
   );
   XORCY   blk0000001c (
-    .CI(sig0000005c),
-    .LI(sig0000007d),
-    .O(p[41])
+    .CI(sig0000006d),
+    .LI(sig0000008e),
+    .O(sig00000186)
   );
   MUXCY   blk0000001d (
-    .CI(sig0000005c),
-    .DI(sig0000014e),
-    .S(sig0000007d),
-    .O(sig0000005d)
+    .CI(sig0000006d),
+    .DI(sig0000015f),
+    .S(sig0000008e),
+    .O(sig0000006e)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000001e (
-    .I0(sig0000014e),
-    .I1(sig00000162),
-    .O(sig0000007d)
+    .I0(sig00000173),
+    .I1(sig0000015f),
+    .O(sig0000008e)
   );
   XORCY   blk0000001f (
-    .CI(sig0000005b),
-    .LI(sig0000007c),
-    .O(p[40])
+    .CI(sig0000006c),
+    .LI(sig0000008d),
+    .O(sig00000185)
   );
   MUXCY   blk00000020 (
-    .CI(sig0000005b),
-    .DI(sig0000014e),
-    .S(sig0000007c),
-    .O(sig0000005c)
+    .CI(sig0000006c),
+    .DI(sig0000015f),
+    .S(sig0000008d),
+    .O(sig0000006d)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000021 (
-    .I0(sig0000014e),
-    .I1(sig00000161),
-    .O(sig0000007c)
+    .I0(sig00000172),
+    .I1(sig0000015f),
+    .O(sig0000008d)
   );
   XORCY   blk00000022 (
-    .CI(sig0000005a),
-    .LI(sig0000007b),
-    .O(p[39])
+    .CI(sig0000006b),
+    .LI(sig0000008c),
+    .O(sig00000184)
   );
   MUXCY   blk00000023 (
-    .CI(sig0000005a),
-    .DI(sig0000014d),
-    .S(sig0000007b),
-    .O(sig0000005b)
+    .CI(sig0000006b),
+    .DI(sig0000015e),
+    .S(sig0000008c),
+    .O(sig0000006c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000024 (
-    .I0(sig0000014d),
-    .I1(sig00000160),
-    .O(sig0000007b)
+    .I0(sig00000171),
+    .I1(sig0000015e),
+    .O(sig0000008c)
   );
   XORCY   blk00000025 (
-    .CI(sig00000059),
-    .LI(sig0000007a),
-    .O(p[38])
+    .CI(sig0000006a),
+    .LI(sig0000008b),
+    .O(sig00000183)
   );
   MUXCY   blk00000026 (
-    .CI(sig00000059),
-    .DI(sig0000014c),
-    .S(sig0000007a),
-    .O(sig0000005a)
+    .CI(sig0000006a),
+    .DI(sig0000015d),
+    .S(sig0000008b),
+    .O(sig0000006b)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000027 (
-    .I0(sig0000014c),
-    .I1(sig0000015f),
-    .O(sig0000007a)
+    .I0(sig00000170),
+    .I1(sig0000015d),
+    .O(sig0000008b)
   );
   XORCY   blk00000028 (
-    .CI(sig00000057),
-    .LI(sig00000079),
-    .O(p[37])
+    .CI(sig00000068),
+    .LI(sig0000008a),
+    .O(sig00000182)
   );
   MUXCY   blk00000029 (
-    .CI(sig00000057),
-    .DI(sig0000014b),
-    .S(sig00000079),
-    .O(sig00000059)
+    .CI(sig00000068),
+    .DI(sig0000015c),
+    .S(sig0000008a),
+    .O(sig0000006a)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000002a (
-    .I0(sig0000014b),
-    .I1(sig0000015e),
-    .O(sig00000079)
+    .I0(sig0000016f),
+    .I1(sig0000015c),
+    .O(sig0000008a)
   );
   XORCY   blk0000002b (
-    .CI(sig00000056),
-    .LI(sig00000077),
-    .O(p[36])
+    .CI(sig00000067),
+    .LI(sig00000088),
+    .O(sig00000180)
   );
   MUXCY   blk0000002c (
-    .CI(sig00000056),
-    .DI(sig00000149),
-    .S(sig00000077),
-    .O(sig00000057)
+    .CI(sig00000067),
+    .DI(sig0000015a),
+    .S(sig00000088),
+    .O(sig00000068)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000002d (
-    .I0(sig00000149),
-    .I1(sig0000015d),
-    .O(sig00000077)
+    .I0(sig0000016e),
+    .I1(sig0000015a),
+    .O(sig00000088)
   );
   XORCY   blk0000002e (
-    .CI(sig00000055),
-    .LI(sig00000076),
-    .O(p[35])
+    .CI(sig00000066),
+    .LI(sig00000087),
+    .O(sig0000017f)
   );
   MUXCY   blk0000002f (
-    .CI(sig00000055),
-    .DI(sig00000148),
-    .S(sig00000076),
-    .O(sig00000056)
+    .CI(sig00000066),
+    .DI(sig00000159),
+    .S(sig00000087),
+    .O(sig00000067)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000030 (
-    .I0(sig00000148),
-    .I1(sig0000015c),
-    .O(sig00000076)
+    .I0(sig0000016d),
+    .I1(sig00000159),
+    .O(sig00000087)
   );
   XORCY   blk00000031 (
-    .CI(sig00000054),
-    .LI(sig00000075),
-    .O(p[34])
+    .CI(sig00000065),
+    .LI(sig00000086),
+    .O(sig0000017e)
   );
   MUXCY   blk00000032 (
-    .CI(sig00000054),
-    .DI(sig00000147),
-    .S(sig00000075),
-    .O(sig00000055)
+    .CI(sig00000065),
+    .DI(sig00000158),
+    .S(sig00000086),
+    .O(sig00000066)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000033 (
-    .I0(sig00000147),
-    .I1(sig00000157),
-    .O(sig00000075)
+    .I0(sig00000168),
+    .I1(sig00000158),
+    .O(sig00000086)
   );
   XORCY   blk00000034 (
-    .CI(sig00000053),
-    .LI(sig00000074),
-    .O(p[33])
+    .CI(sig00000064),
+    .LI(sig00000085),
+    .O(sig0000017d)
   );
   MUXCY   blk00000035 (
-    .CI(sig00000053),
-    .DI(sig00000146),
-    .S(sig00000074),
-    .O(sig00000054)
+    .CI(sig00000064),
+    .DI(sig00000157),
+    .S(sig00000085),
+    .O(sig00000065)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000036 (
-    .I0(sig00000146),
-    .I1(sig00000121),
-    .O(sig00000074)
+    .I0(sig00000132),
+    .I1(sig00000157),
+    .O(sig00000085)
   );
   XORCY   blk00000037 (
-    .CI(sig00000052),
-    .LI(sig00000073),
-    .O(p[32])
+    .CI(sig00000063),
+    .LI(sig00000084),
+    .O(sig0000017c)
   );
   MUXCY   blk00000038 (
-    .CI(sig00000052),
-    .DI(sig00000145),
-    .S(sig00000073),
-    .O(sig00000053)
+    .CI(sig00000063),
+    .DI(sig00000156),
+    .S(sig00000084),
+    .O(sig00000064)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000039 (
-    .I0(sig00000145),
-    .I1(sig00000120),
-    .O(sig00000073)
+    .I0(sig00000131),
+    .I1(sig00000156),
+    .O(sig00000084)
   );
   XORCY   blk0000003a (
-    .CI(sig00000051),
-    .LI(sig00000072),
-    .O(p[31])
+    .CI(sig00000062),
+    .LI(sig00000083),
+    .O(sig0000017b)
   );
   MUXCY   blk0000003b (
-    .CI(sig00000051),
-    .DI(sig00000144),
-    .S(sig00000072),
-    .O(sig00000052)
+    .CI(sig00000062),
+    .DI(sig00000155),
+    .S(sig00000083),
+    .O(sig00000063)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000003c (
-    .I0(sig00000144),
-    .I1(sig0000011f),
-    .O(sig00000072)
+    .I0(sig00000130),
+    .I1(sig00000155),
+    .O(sig00000083)
   );
   XORCY   blk0000003d (
-    .CI(sig00000050),
-    .LI(sig00000071),
-    .O(p[30])
+    .CI(sig00000061),
+    .LI(sig00000082),
+    .O(sig0000017a)
   );
   MUXCY   blk0000003e (
-    .CI(sig00000050),
-    .DI(sig00000143),
-    .S(sig00000071),
-    .O(sig00000051)
+    .CI(sig00000061),
+    .DI(sig00000154),
+    .S(sig00000082),
+    .O(sig00000062)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000003f (
-    .I0(sig00000143),
-    .I1(sig0000011e),
-    .O(sig00000071)
+    .I0(sig0000012f),
+    .I1(sig00000154),
+    .O(sig00000082)
   );
   XORCY   blk00000040 (
-    .CI(sig0000004f),
-    .LI(sig00000070),
-    .O(p[29])
+    .CI(sig00000060),
+    .LI(sig00000081),
+    .O(sig00000179)
   );
   MUXCY   blk00000041 (
-    .CI(sig0000004f),
-    .DI(sig00000142),
-    .S(sig00000070),
-    .O(sig00000050)
+    .CI(sig00000060),
+    .DI(sig00000153),
+    .S(sig00000081),
+    .O(sig00000061)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000042 (
-    .I0(sig00000142),
-    .I1(sig0000011d),
-    .O(sig00000070)
+    .I0(sig0000012e),
+    .I1(sig00000153),
+    .O(sig00000081)
   );
   XORCY   blk00000043 (
-    .CI(sig0000004e),
-    .LI(sig0000006f),
-    .O(p[28])
+    .CI(sig0000005f),
+    .LI(sig00000080),
+    .O(sig00000178)
   );
   MUXCY   blk00000044 (
-    .CI(sig0000004e),
-    .DI(sig00000141),
-    .S(sig0000006f),
-    .O(sig0000004f)
+    .CI(sig0000005f),
+    .DI(sig00000152),
+    .S(sig00000080),
+    .O(sig00000060)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000045 (
-    .I0(sig00000141),
-    .I1(sig0000011c),
-    .O(sig0000006f)
+    .I0(sig0000012d),
+    .I1(sig00000152),
+    .O(sig00000080)
   );
   XORCY   blk00000046 (
-    .CI(sig0000006c),
-    .LI(sig0000006e),
-    .O(p[27])
+    .CI(sig0000007d),
+    .LI(sig0000007f),
+    .O(sig00000177)
   );
   MUXCY   blk00000047 (
-    .CI(sig0000006c),
-    .DI(sig00000140),
-    .S(sig0000006e),
-    .O(sig0000004e)
+    .CI(sig0000007d),
+    .DI(sig00000151),
+    .S(sig0000007f),
+    .O(sig0000005f)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000048 (
-    .I0(sig00000140),
-    .I1(sig0000011b),
-    .O(sig0000006e)
+    .I0(sig0000012c),
+    .I1(sig00000151),
+    .O(sig0000007f)
   );
   XORCY   blk00000049 (
-    .CI(sig0000006b),
-    .LI(sig0000008d),
-    .O(p[26])
+    .CI(sig0000007c),
+    .LI(sig0000009e),
+    .O(sig00000194)
   );
   MUXCY   blk0000004a (
-    .CI(sig0000006b),
-    .DI(sig00000156),
-    .S(sig0000008d),
-    .O(sig0000006c)
+    .CI(sig0000007c),
+    .DI(sig00000167),
+    .S(sig0000009e),
+    .O(sig0000007d)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000004b (
-    .I0(sig00000156),
-    .I1(sig00000130),
-    .O(sig0000008d)
+    .I0(sig00000141),
+    .I1(sig00000167),
+    .O(sig0000009e)
   );
   XORCY   blk0000004c (
-    .CI(sig0000006a),
-    .LI(sig0000008c),
-    .O(p[25])
+    .CI(sig0000007b),
+    .LI(sig0000009d),
+    .O(sig00000193)
   );
   MUXCY   blk0000004d (
-    .CI(sig0000006a),
-    .DI(sig00000155),
-    .S(sig0000008c),
-    .O(sig0000006b)
+    .CI(sig0000007b),
+    .DI(sig00000166),
+    .S(sig0000009d),
+    .O(sig0000007c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000004e (
-    .I0(sig00000155),
-    .I1(sig0000012f),
-    .O(sig0000008c)
+    .I0(sig00000140),
+    .I1(sig00000166),
+    .O(sig0000009d)
   );
   XORCY   blk0000004f (
-    .CI(sig00000069),
-    .LI(sig0000008b),
-    .O(p[24])
+    .CI(sig0000007a),
+    .LI(sig0000009c),
+    .O(sig00000192)
   );
   MUXCY   blk00000050 (
-    .CI(sig00000069),
-    .DI(sig00000154),
-    .S(sig0000008b),
-    .O(sig0000006a)
+    .CI(sig0000007a),
+    .DI(sig00000165),
+    .S(sig0000009c),
+    .O(sig0000007b)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000051 (
-    .I0(sig00000154),
-    .I1(sig0000012e),
-    .O(sig0000008b)
+    .I0(sig0000013f),
+    .I1(sig00000165),
+    .O(sig0000009c)
   );
   XORCY   blk00000052 (
-    .CI(sig00000068),
-    .LI(sig0000008a),
-    .O(p[23])
+    .CI(sig00000079),
+    .LI(sig0000009b),
+    .O(sig00000191)
   );
   MUXCY   blk00000053 (
-    .CI(sig00000068),
-    .DI(sig00000153),
-    .S(sig0000008a),
-    .O(sig00000069)
+    .CI(sig00000079),
+    .DI(sig00000164),
+    .S(sig0000009b),
+    .O(sig0000007a)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000054 (
-    .I0(sig00000153),
-    .I1(sig0000012d),
-    .O(sig0000008a)
+    .I0(sig0000013e),
+    .I1(sig00000164),
+    .O(sig0000009b)
   );
   XORCY   blk00000055 (
-    .CI(sig00000067),
-    .LI(sig00000089),
-    .O(p[22])
+    .CI(sig00000078),
+    .LI(sig0000009a),
+    .O(sig00000190)
   );
   MUXCY   blk00000056 (
-    .CI(sig00000067),
-    .DI(sig00000152),
-    .S(sig00000089),
-    .O(sig00000068)
+    .CI(sig00000078),
+    .DI(sig00000163),
+    .S(sig0000009a),
+    .O(sig00000079)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000057 (
-    .I0(sig00000152),
-    .I1(sig0000012c),
-    .O(sig00000089)
+    .I0(sig0000013d),
+    .I1(sig00000163),
+    .O(sig0000009a)
   );
   XORCY   blk00000058 (
-    .CI(sig00000066),
-    .LI(sig00000088),
-    .O(p[21])
+    .CI(sig00000077),
+    .LI(sig00000099),
+    .O(sig0000018e)
   );
   MUXCY   blk00000059 (
-    .CI(sig00000066),
-    .DI(sig00000151),
-    .S(sig00000088),
-    .O(sig00000067)
+    .CI(sig00000077),
+    .DI(sig00000162),
+    .S(sig00000099),
+    .O(sig00000078)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000005a (
-    .I0(sig00000151),
-    .I1(sig0000012b),
-    .O(sig00000088)
+    .I0(sig0000013c),
+    .I1(sig00000162),
+    .O(sig00000099)
   );
   XORCY   blk0000005b (
-    .CI(sig00000063),
-    .LI(sig00000087),
-    .O(p[20])
+    .CI(sig00000074),
+    .LI(sig00000098),
+    .O(sig0000018d)
   );
   MUXCY   blk0000005c (
-    .CI(sig00000063),
-    .DI(sig00000150),
-    .S(sig00000087),
-    .O(sig00000066)
+    .CI(sig00000074),
+    .DI(sig00000161),
+    .S(sig00000098),
+    .O(sig00000077)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000005d (
-    .I0(sig00000150),
-    .I1(sig0000012a),
-    .O(sig00000087)
+    .I0(sig0000013b),
+    .I1(sig00000161),
+    .O(sig00000098)
   );
   XORCY   blk0000005e (
-    .CI(sig00000058),
-    .LI(sig00000083),
-    .O(p[19])
+    .CI(sig00000069),
+    .LI(sig00000094),
+    .O(sig0000018c)
   );
   MUXCY   blk0000005f (
-    .CI(sig00000058),
-    .DI(sig0000014f),
-    .S(sig00000083),
-    .O(sig00000063)
+    .CI(sig00000069),
+    .DI(sig00000160),
+    .S(sig00000094),
+    .O(sig00000074)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000060 (
-    .I0(sig0000014f),
-    .I1(sig00000125),
-    .O(sig00000083)
+    .I0(sig00000136),
+    .I1(sig00000160),
+    .O(sig00000094)
   );
   XORCY   blk00000061 (
-    .CI(sig0000004d),
-    .LI(sig00000078),
-    .O(p[18])
+    .CI(sig0000005e),
+    .LI(sig00000089),
+    .O(sig00000181)
   );
   MUXCY   blk00000062 (
-    .CI(sig0000004d),
-    .DI(sig0000014a),
-    .S(sig00000078),
-    .O(sig00000058)
+    .CI(sig0000005e),
+    .DI(sig0000015b),
+    .S(sig00000089),
+    .O(sig00000069)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000063 (
-    .I0(sig0000014a),
-    .I1(sig0000011a),
-    .O(sig00000078)
+    .I0(sig0000012b),
+    .I1(sig0000015b),
+    .O(sig00000089)
   );
   XORCY   blk00000064 (
-    .CI(sig00000001),
-    .LI(sig0000006d),
-    .O(p[17])
+    .CI(sig00000012),
+    .LI(sig0000007e),
+    .O(sig00000176)
   );
   MUXCY   blk00000065 (
-    .CI(sig00000001),
-    .DI(sig0000013f),
-    .S(sig0000006d),
-    .O(sig0000004d)
+    .CI(sig00000012),
+    .DI(sig00000150),
+    .S(sig0000007e),
+    .O(sig0000005e)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000066 (
-    .I0(sig0000013f),
-    .I1(sig00000119),
-    .O(sig0000006d)
+    .I0(sig0000012a),
+    .I1(sig00000150),
+    .O(sig0000007e)
   );
   XORCY   blk00000067 (
-    .CI(sig00000011),
-    .LI(sig00000029),
-    .O(sig0000014e)
+    .CI(sig00000022),
+    .LI(sig0000003a),
+    .O(sig0000015f)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000068 (
-    .I0(sig00000100),
-    .I1(sig00000111),
-    .O(sig00000029)
+    .I0(sig00000111),
+    .I1(sig00000122),
+    .O(sig0000003a)
   );
   XORCY   blk00000069 (
-    .CI(sig00000010),
-    .LI(sig00000028),
-    .O(sig0000014d)
+    .CI(sig00000021),
+    .LI(sig00000039),
+    .O(sig0000015e)
   );
   MUXCY   blk0000006a (
-    .CI(sig00000010),
-    .DI(sig00000100),
-    .S(sig00000028),
-    .O(sig00000011)
+    .CI(sig00000021),
+    .DI(sig00000111),
+    .S(sig00000039),
+    .O(sig00000022)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000006b (
-    .I0(sig00000100),
-    .I1(sig00000110),
-    .O(sig00000028)
+    .I0(sig00000121),
+    .I1(sig00000111),
+    .O(sig00000039)
   );
   XORCY   blk0000006c (
-    .CI(sig0000000f),
-    .LI(sig00000027),
-    .O(sig0000014c)
+    .CI(sig00000020),
+    .LI(sig00000038),
+    .O(sig0000015d)
   );
   MUXCY   blk0000006d (
-    .CI(sig0000000f),
-    .DI(sig00000100),
-    .S(sig00000027),
-    .O(sig00000010)
+    .CI(sig00000020),
+    .DI(sig00000111),
+    .S(sig00000038),
+    .O(sig00000021)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000006e (
-    .I0(sig00000100),
-    .I1(sig0000010f),
-    .O(sig00000027)
+    .I0(sig00000120),
+    .I1(sig00000111),
+    .O(sig00000038)
   );
   XORCY   blk0000006f (
-    .CI(sig0000000d),
-    .LI(sig00000026),
-    .O(sig0000014b)
+    .CI(sig0000001e),
+    .LI(sig00000037),
+    .O(sig0000015c)
   );
   MUXCY   blk00000070 (
-    .CI(sig0000000d),
-    .DI(sig00000100),
-    .S(sig00000026),
-    .O(sig0000000f)
+    .CI(sig0000001e),
+    .DI(sig00000111),
+    .S(sig00000037),
+    .O(sig00000020)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000071 (
-    .I0(sig00000100),
-    .I1(sig0000010e),
-    .O(sig00000026)
+    .I0(sig0000011f),
+    .I1(sig00000111),
+    .O(sig00000037)
   );
   XORCY   blk00000072 (
-    .CI(sig0000000c),
-    .LI(sig00000024),
-    .O(sig00000149)
+    .CI(sig0000001d),
+    .LI(sig00000035),
+    .O(sig0000015a)
   );
   MUXCY   blk00000073 (
-    .CI(sig0000000c),
-    .DI(sig00000100),
-    .S(sig00000024),
-    .O(sig0000000d)
+    .CI(sig0000001d),
+    .DI(sig00000111),
+    .S(sig00000035),
+    .O(sig0000001e)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000074 (
-    .I0(sig00000100),
-    .I1(sig0000010c),
-    .O(sig00000024)
+    .I0(sig0000011d),
+    .I1(sig00000111),
+    .O(sig00000035)
   );
   XORCY   blk00000075 (
-    .CI(sig0000000b),
-    .LI(sig00000023),
-    .O(sig00000148)
+    .CI(sig0000001c),
+    .LI(sig00000034),
+    .O(sig00000159)
   );
   MUXCY   blk00000076 (
-    .CI(sig0000000b),
-    .DI(sig00000100),
-    .S(sig00000023),
-    .O(sig0000000c)
+    .CI(sig0000001c),
+    .DI(sig00000111),
+    .S(sig00000034),
+    .O(sig0000001d)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000077 (
-    .I0(sig00000100),
-    .I1(sig0000010b),
-    .O(sig00000023)
+    .I0(sig0000011c),
+    .I1(sig00000111),
+    .O(sig00000034)
   );
   XORCY   blk00000078 (
-    .CI(sig0000000a),
-    .LI(sig00000022),
-    .O(sig00000147)
+    .CI(sig0000001b),
+    .LI(sig00000033),
+    .O(sig00000158)
   );
   MUXCY   blk00000079 (
-    .CI(sig0000000a),
-    .DI(sig00000100),
-    .S(sig00000022),
-    .O(sig0000000b)
+    .CI(sig0000001b),
+    .DI(sig00000111),
+    .S(sig00000033),
+    .O(sig0000001c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000007a (
-    .I0(sig00000100),
-    .I1(sig0000010a),
-    .O(sig00000022)
+    .I0(sig0000011b),
+    .I1(sig00000111),
+    .O(sig00000033)
   );
   XORCY   blk0000007b (
-    .CI(sig00000009),
-    .LI(sig00000021),
-    .O(sig00000146)
+    .CI(sig0000001a),
+    .LI(sig00000032),
+    .O(sig00000157)
   );
   MUXCY   blk0000007c (
-    .CI(sig00000009),
-    .DI(sig000000ff),
-    .S(sig00000021),
-    .O(sig0000000a)
+    .CI(sig0000001a),
+    .DI(sig00000110),
+    .S(sig00000032),
+    .O(sig0000001b)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000007d (
-    .I0(sig000000ff),
-    .I1(sig00000109),
-    .O(sig00000021)
+    .I0(sig00000110),
+    .I1(sig0000011a),
+    .O(sig00000032)
   );
   XORCY   blk0000007e (
-    .CI(sig00000008),
-    .LI(sig00000020),
-    .O(sig00000145)
+    .CI(sig00000019),
+    .LI(sig00000031),
+    .O(sig00000156)
   );
   MUXCY   blk0000007f (
-    .CI(sig00000008),
-    .DI(sig000000fe),
-    .S(sig00000020),
-    .O(sig00000009)
+    .CI(sig00000019),
+    .DI(sig0000010f),
+    .S(sig00000031),
+    .O(sig0000001a)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000080 (
-    .I0(sig000000fe),
-    .I1(sig00000108),
-    .O(sig00000020)
+    .I0(sig0000010f),
+    .I1(sig00000119),
+    .O(sig00000031)
   );
   XORCY   blk00000081 (
-    .CI(sig00000007),
-    .LI(sig0000001f),
-    .O(sig00000144)
+    .CI(sig00000018),
+    .LI(sig00000030),
+    .O(sig00000155)
   );
   MUXCY   blk00000082 (
-    .CI(sig00000007),
-    .DI(sig000000fd),
-    .S(sig0000001f),
-    .O(sig00000008)
+    .CI(sig00000018),
+    .DI(sig0000010e),
+    .S(sig00000030),
+    .O(sig00000019)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000083 (
-    .I0(sig000000fd),
-    .I1(sig00000107),
-    .O(sig0000001f)
+    .I0(sig0000010e),
+    .I1(sig00000118),
+    .O(sig00000030)
   );
   XORCY   blk00000084 (
-    .CI(sig00000006),
-    .LI(sig0000001e),
-    .O(sig00000143)
+    .CI(sig00000017),
+    .LI(sig0000002f),
+    .O(sig00000154)
   );
   MUXCY   blk00000085 (
-    .CI(sig00000006),
-    .DI(sig000000fc),
-    .S(sig0000001e),
-    .O(sig00000007)
+    .CI(sig00000017),
+    .DI(sig0000010d),
+    .S(sig0000002f),
+    .O(sig00000018)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000086 (
-    .I0(sig000000fc),
-    .I1(sig00000106),
-    .O(sig0000001e)
+    .I0(sig0000010d),
+    .I1(sig00000117),
+    .O(sig0000002f)
   );
   XORCY   blk00000087 (
-    .CI(sig00000005),
-    .LI(sig0000001d),
-    .O(sig00000142)
+    .CI(sig00000016),
+    .LI(sig0000002e),
+    .O(sig00000153)
   );
   MUXCY   blk00000088 (
-    .CI(sig00000005),
-    .DI(sig000000fb),
-    .S(sig0000001d),
-    .O(sig00000006)
+    .CI(sig00000016),
+    .DI(sig0000010c),
+    .S(sig0000002e),
+    .O(sig00000017)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000089 (
-    .I0(sig000000fb),
-    .I1(sig00000105),
-    .O(sig0000001d)
+    .I0(sig0000010c),
+    .I1(sig00000116),
+    .O(sig0000002e)
   );
   XORCY   blk0000008a (
-    .CI(sig00000004),
-    .LI(sig0000001c),
-    .O(sig00000141)
+    .CI(sig00000015),
+    .LI(sig0000002d),
+    .O(sig00000152)
   );
   MUXCY   blk0000008b (
-    .CI(sig00000004),
-    .DI(sig000000fa),
-    .S(sig0000001c),
-    .O(sig00000005)
+    .CI(sig00000015),
+    .DI(sig0000010b),
+    .S(sig0000002d),
+    .O(sig00000016)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000008c (
-    .I0(sig000000fa),
-    .I1(sig00000104),
-    .O(sig0000001c)
+    .I0(sig0000010b),
+    .I1(sig00000115),
+    .O(sig0000002d)
   );
   XORCY   blk0000008d (
-    .CI(sig00000019),
-    .LI(sig0000001b),
-    .O(sig00000140)
+    .CI(sig0000002a),
+    .LI(sig0000002c),
+    .O(sig00000151)
   );
   MUXCY   blk0000008e (
-    .CI(sig00000019),
-    .DI(sig000000f9),
-    .S(sig0000001b),
-    .O(sig00000004)
+    .CI(sig0000002a),
+    .DI(sig0000010a),
+    .S(sig0000002c),
+    .O(sig00000015)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000008f (
-    .I0(sig000000f9),
-    .I1(sig00000103),
-    .O(sig0000001b)
+    .I0(sig0000010a),
+    .I1(sig00000114),
+    .O(sig0000002c)
   );
   XORCY   blk00000090 (
-    .CI(sig00000018),
-    .LI(sig00000031),
-    .O(sig00000156)
+    .CI(sig00000029),
+    .LI(sig00000042),
+    .O(sig00000167)
   );
   MUXCY   blk00000091 (
-    .CI(sig00000018),
-    .DI(sig000000f8),
-    .S(sig00000031),
-    .O(sig00000019)
+    .CI(sig00000029),
+    .DI(sig00000109),
+    .S(sig00000042),
+    .O(sig0000002a)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000092 (
-    .I0(sig000000f8),
-    .I1(sig00000118),
-    .O(sig00000031)
+    .I0(sig00000109),
+    .I1(sig00000129),
+    .O(sig00000042)
   );
   XORCY   blk00000093 (
-    .CI(sig00000017),
-    .LI(sig00000030),
-    .O(sig00000155)
+    .CI(sig00000028),
+    .LI(sig00000041),
+    .O(sig00000166)
   );
   MUXCY   blk00000094 (
-    .CI(sig00000017),
-    .DI(sig000000f7),
-    .S(sig00000030),
-    .O(sig00000018)
+    .CI(sig00000028),
+    .DI(sig00000108),
+    .S(sig00000041),
+    .O(sig00000029)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000095 (
-    .I0(sig000000f7),
-    .I1(sig00000117),
-    .O(sig00000030)
+    .I0(sig00000108),
+    .I1(sig00000128),
+    .O(sig00000041)
   );
   XORCY   blk00000096 (
-    .CI(sig00000016),
-    .LI(sig0000002f),
-    .O(sig00000154)
+    .CI(sig00000027),
+    .LI(sig00000040),
+    .O(sig00000165)
   );
   MUXCY   blk00000097 (
-    .CI(sig00000016),
-    .DI(sig000000f6),
-    .S(sig0000002f),
-    .O(sig00000017)
+    .CI(sig00000027),
+    .DI(sig00000107),
+    .S(sig00000040),
+    .O(sig00000028)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk00000098 (
-    .I0(sig000000f6),
-    .I1(sig00000116),
-    .O(sig0000002f)
+    .I0(sig00000107),
+    .I1(sig00000127),
+    .O(sig00000040)
   );
   XORCY   blk00000099 (
-    .CI(sig00000015),
-    .LI(sig0000002e),
-    .O(sig00000153)
+    .CI(sig00000026),
+    .LI(sig0000003f),
+    .O(sig00000164)
   );
   MUXCY   blk0000009a (
-    .CI(sig00000015),
-    .DI(sig000000f5),
-    .S(sig0000002e),
-    .O(sig00000016)
+    .CI(sig00000026),
+    .DI(sig00000106),
+    .S(sig0000003f),
+    .O(sig00000027)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000009b (
-    .I0(sig000000f5),
-    .I1(sig00000115),
-    .O(sig0000002e)
+    .I0(sig00000106),
+    .I1(sig00000126),
+    .O(sig0000003f)
   );
   XORCY   blk0000009c (
-    .CI(sig00000014),
-    .LI(sig0000002d),
-    .O(sig00000152)
+    .CI(sig00000025),
+    .LI(sig0000003e),
+    .O(sig00000163)
   );
   MUXCY   blk0000009d (
-    .CI(sig00000014),
-    .DI(sig000000f4),
-    .S(sig0000002d),
-    .O(sig00000015)
+    .CI(sig00000025),
+    .DI(sig00000105),
+    .S(sig0000003e),
+    .O(sig00000026)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk0000009e (
-    .I0(sig000000f4),
-    .I1(sig00000114),
-    .O(sig0000002d)
+    .I0(sig00000105),
+    .I1(sig00000125),
+    .O(sig0000003e)
   );
   XORCY   blk0000009f (
-    .CI(sig00000013),
-    .LI(sig0000002c),
-    .O(sig00000151)
+    .CI(sig00000024),
+    .LI(sig0000003d),
+    .O(sig00000162)
   );
   MUXCY   blk000000a0 (
-    .CI(sig00000013),
-    .DI(sig000000f3),
-    .S(sig0000002c),
-    .O(sig00000014)
+    .CI(sig00000024),
+    .DI(sig00000104),
+    .S(sig0000003d),
+    .O(sig00000025)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000a1 (
-    .I0(sig000000f3),
-    .I1(sig00000113),
-    .O(sig0000002c)
+    .I0(sig00000104),
+    .I1(sig00000124),
+    .O(sig0000003d)
   );
   XORCY   blk000000a2 (
-    .CI(sig00000012),
-    .LI(sig0000002b),
-    .O(sig00000150)
+    .CI(sig00000023),
+    .LI(sig0000003c),
+    .O(sig00000161)
   );
   MUXCY   blk000000a3 (
-    .CI(sig00000012),
-    .DI(sig000000f2),
-    .S(sig0000002b),
-    .O(sig00000013)
+    .CI(sig00000023),
+    .DI(sig00000103),
+    .S(sig0000003c),
+    .O(sig00000024)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000a4 (
-    .I0(sig000000f2),
-    .I1(sig00000112),
-    .O(sig0000002b)
+    .I0(sig00000103),
+    .I1(sig00000123),
+    .O(sig0000003c)
   );
   XORCY   blk000000a5 (
-    .CI(sig0000000e),
-    .LI(sig0000002a),
-    .O(sig0000014f)
+    .CI(sig0000001f),
+    .LI(sig0000003b),
+    .O(sig00000160)
   );
   MUXCY   blk000000a6 (
-    .CI(sig0000000e),
-    .DI(sig000000f1),
-    .S(sig0000002a),
-    .O(sig00000012)
+    .CI(sig0000001f),
+    .DI(sig00000102),
+    .S(sig0000003b),
+    .O(sig00000023)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000a7 (
-    .I0(sig000000f1),
-    .I1(sig0000010d),
-    .O(sig0000002a)
+    .I0(sig00000102),
+    .I1(sig0000011e),
+    .O(sig0000003b)
   );
   XORCY   blk000000a8 (
-    .CI(sig00000003),
-    .LI(sig00000025),
-    .O(sig0000014a)
+    .CI(sig00000014),
+    .LI(sig00000036),
+    .O(sig0000015b)
   );
   MUXCY   blk000000a9 (
-    .CI(sig00000003),
-    .DI(sig000000f0),
-    .S(sig00000025),
-    .O(sig0000000e)
+    .CI(sig00000014),
+    .DI(sig00000101),
+    .S(sig00000036),
+    .O(sig0000001f)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000aa (
-    .I0(sig000000f0),
-    .I1(sig00000102),
-    .O(sig00000025)
-  );
+    .I0(sig00000101),
+    .I1(sig00000113),
+    .O(sig00000036)
+  );
   XORCY   blk000000ab (
-    .CI(sig00000001),
-    .LI(sig0000001a),
-    .O(sig0000013f)
+    .CI(sig00000012),
+    .LI(sig0000002b),
+    .O(sig00000150)
   );
   MUXCY   blk000000ac (
-    .CI(sig00000001),
-    .DI(sig000000ef),
-    .S(sig0000001a),
-    .O(sig00000003)
+    .CI(sig00000012),
+    .DI(sig00000100),
+    .S(sig0000002b),
+    .O(sig00000014)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000ad (
-    .I0(sig000000ef),
-    .I1(sig00000101),
-    .O(sig0000001a)
+    .I0(sig00000100),
+    .I1(sig00000112),
+    .O(sig0000002b)
   );
   XORCY   blk000000ae (
-    .CI(sig00000035),
-    .LI(sig00000043),
-    .O(sig0000015b)
+    .CI(sig00000046),
+    .LI(sig00000054),
+    .O(sig0000016c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000af (
-    .I0(sig00000129),
-    .I1(sig00000136),
-    .O(sig00000043)
+    .I0(sig0000013a),
+    .I1(sig00000147),
+    .O(sig00000054)
   );
   XORCY   blk000000b0 (
-    .CI(sig00000034),
-    .LI(sig00000042),
-    .O(sig0000015a)
+    .CI(sig00000045),
+    .LI(sig00000053),
+    .O(sig0000016b)
   );
   MUXCY   blk000000b1 (
-    .CI(sig00000034),
-    .DI(sig00000129),
-    .S(sig00000042),
-    .O(sig00000035)
+    .CI(sig00000045),
+    .DI(sig0000013a),
+    .S(sig00000053),
+    .O(sig00000046)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000b2 (
-    .I0(sig00000129),
-    .I1(sig00000135),
-    .O(sig00000042)
+    .I0(sig00000146),
+    .I1(sig0000013a),
+    .O(sig00000053)
   );
   XORCY   blk000000b3 (
-    .CI(sig00000033),
-    .LI(sig00000041),
-    .O(sig00000159)
+    .CI(sig00000044),
+    .LI(sig00000052),
+    .O(sig0000016a)
   );
   MUXCY   blk000000b4 (
-    .CI(sig00000033),
-    .DI(sig00000129),
-    .S(sig00000041),
-    .O(sig00000034)
+    .CI(sig00000044),
+    .DI(sig0000013a),
+    .S(sig00000052),
+    .O(sig00000045)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000b5 (
-    .I0(sig00000129),
-    .I1(sig00000134),
-    .O(sig00000041)
+    .I0(sig00000145),
+    .I1(sig0000013a),
+    .O(sig00000052)
   );
   XORCY   blk000000b6 (
-    .CI(sig0000003e),
-    .LI(sig00000040),
-    .O(sig00000158)
+    .CI(sig0000004f),
+    .LI(sig00000051),
+    .O(sig00000169)
   );
   MUXCY   blk000000b7 (
-    .CI(sig0000003e),
-    .DI(sig00000129),
-    .S(sig00000040),
-    .O(sig00000033)
+    .CI(sig0000004f),
+    .DI(sig0000013a),
+    .S(sig00000051),
+    .O(sig00000044)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000b8 (
-    .I0(sig00000129),
-    .I1(sig00000133),
-    .O(sig00000040)
+    .I0(sig00000144),
+    .I1(sig0000013a),
+    .O(sig00000051)
   );
   XORCY   blk000000b9 (
-    .CI(sig0000003d),
-    .LI(sig0000004c),
-    .O(sig00000164)
+    .CI(sig0000004e),
+    .LI(sig0000005d),
+    .O(sig00000175)
   );
   MUXCY   blk000000ba (
-    .CI(sig0000003d),
-    .DI(sig00000129),
-    .S(sig0000004c),
-    .O(sig0000003e)
+    .CI(sig0000004e),
+    .DI(sig0000013a),
+    .S(sig0000005d),
+    .O(sig0000004f)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000bb (
-    .I0(sig00000129),
-    .I1(sig0000013e),
-    .O(sig0000004c)
+    .I0(sig0000014f),
+    .I1(sig0000013a),
+    .O(sig0000005d)
   );
   XORCY   blk000000bc (
-    .CI(sig0000003c),
-    .LI(sig0000004b),
-    .O(sig00000163)
+    .CI(sig0000004d),
+    .LI(sig0000005c),
+    .O(sig00000174)
   );
   MUXCY   blk000000bd (
-    .CI(sig0000003c),
-    .DI(sig00000129),
-    .S(sig0000004b),
-    .O(sig0000003d)
+    .CI(sig0000004d),
+    .DI(sig0000013a),
+    .S(sig0000005c),
+    .O(sig0000004e)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000be (
-    .I0(sig00000129),
-    .I1(sig0000013d),
-    .O(sig0000004b)
+    .I0(sig0000014e),
+    .I1(sig0000013a),
+    .O(sig0000005c)
   );
   XORCY   blk000000bf (
-    .CI(sig0000003b),
-    .LI(sig0000004a),
-    .O(sig00000162)
+    .CI(sig0000004c),
+    .LI(sig0000005b),
+    .O(sig00000173)
   );
   MUXCY   blk000000c0 (
-    .CI(sig0000003b),
-    .DI(sig00000129),
-    .S(sig0000004a),
-    .O(sig0000003c)
+    .CI(sig0000004c),
+    .DI(sig0000013a),
+    .S(sig0000005b),
+    .O(sig0000004d)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000c1 (
-    .I0(sig00000129),
-    .I1(sig0000013c),
-    .O(sig0000004a)
+    .I0(sig0000014d),
+    .I1(sig0000013a),
+    .O(sig0000005b)
   );
   XORCY   blk000000c2 (
-    .CI(sig0000003a),
-    .LI(sig00000049),
-    .O(sig00000161)
+    .CI(sig0000004b),
+    .LI(sig0000005a),
+    .O(sig00000172)
   );
   MUXCY   blk000000c3 (
-    .CI(sig0000003a),
-    .DI(sig00000129),
-    .S(sig00000049),
-    .O(sig0000003b)
+    .CI(sig0000004b),
+    .DI(sig0000013a),
+    .S(sig0000005a),
+    .O(sig0000004c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000c4 (
-    .I0(sig00000129),
-    .I1(sig0000013b),
-    .O(sig00000049)
+    .I0(sig0000014c),
+    .I1(sig0000013a),
+    .O(sig0000005a)
   );
   XORCY   blk000000c5 (
-    .CI(sig00000039),
-    .LI(sig00000048),
-    .O(sig00000160)
+    .CI(sig0000004a),
+    .LI(sig00000059),
+    .O(sig00000171)
   );
   MUXCY   blk000000c6 (
-    .CI(sig00000039),
-    .DI(sig00000128),
-    .S(sig00000048),
-    .O(sig0000003a)
+    .CI(sig0000004a),
+    .DI(sig00000139),
+    .S(sig00000059),
+    .O(sig0000004b)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000c7 (
-    .I0(sig00000128),
-    .I1(sig0000013a),
-    .O(sig00000048)
+    .I0(sig00000139),
+    .I1(sig0000014b),
+    .O(sig00000059)
   );
   XORCY   blk000000c8 (
-    .CI(sig00000038),
-    .LI(sig00000047),
-    .O(sig0000015f)
+    .CI(sig00000049),
+    .LI(sig00000058),
+    .O(sig00000170)
   );
   MUXCY   blk000000c9 (
-    .CI(sig00000038),
-    .DI(sig00000127),
-    .S(sig00000047),
-    .O(sig00000039)
+    .CI(sig00000049),
+    .DI(sig00000138),
+    .S(sig00000058),
+    .O(sig0000004a)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000ca (
-    .I0(sig00000127),
-    .I1(sig00000139),
-    .O(sig00000047)
+    .I0(sig00000138),
+    .I1(sig0000014a),
+    .O(sig00000058)
   );
   XORCY   blk000000cb (
-    .CI(sig00000037),
-    .LI(sig00000046),
-    .O(sig0000015e)
+    .CI(sig00000048),
+    .LI(sig00000057),
+    .O(sig0000016f)
   );
   MUXCY   blk000000cc (
-    .CI(sig00000037),
-    .DI(sig00000126),
-    .S(sig00000046),
-    .O(sig00000038)
+    .CI(sig00000048),
+    .DI(sig00000137),
+    .S(sig00000057),
+    .O(sig00000049)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000cd (
-    .I0(sig00000126),
-    .I1(sig00000138),
-    .O(sig00000046)
+    .I0(sig00000137),
+    .I1(sig00000149),
+    .O(sig00000057)
   );
   XORCY   blk000000ce (
-    .CI(sig00000036),
-    .LI(sig00000045),
-    .O(sig0000015d)
+    .CI(sig00000047),
+    .LI(sig00000056),
+    .O(sig0000016e)
   );
   MUXCY   blk000000cf (
-    .CI(sig00000036),
-    .DI(sig00000124),
-    .S(sig00000045),
-    .O(sig00000037)
+    .CI(sig00000047),
+    .DI(sig00000135),
+    .S(sig00000056),
+    .O(sig00000048)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000d0 (
-    .I0(sig00000124),
-    .I1(sig00000137),
-    .O(sig00000045)
+    .I0(sig00000135),
+    .I1(sig00000148),
+    .O(sig00000056)
   );
   XORCY   blk000000d1 (
-    .CI(sig00000032),
-    .LI(sig00000044),
-    .O(sig0000015c)
+    .CI(sig00000043),
+    .LI(sig00000055),
+    .O(sig0000016d)
   );
   MUXCY   blk000000d2 (
-    .CI(sig00000032),
-    .DI(sig00000123),
-    .S(sig00000044),
-    .O(sig00000036)
+    .CI(sig00000043),
+    .DI(sig00000134),
+    .S(sig00000055),
+    .O(sig00000047)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000d3 (
-    .I0(sig00000123),
-    .I1(sig00000132),
-    .O(sig00000044)
+    .I0(sig00000134),
+    .I1(sig00000143),
+    .O(sig00000055)
   );
   XORCY   blk000000d4 (
-    .CI(sig00000001),
-    .LI(sig0000003f),
-    .O(sig00000157)
+    .CI(sig00000012),
+    .LI(sig00000050),
+    .O(sig00000168)
   );
   MUXCY   blk000000d5 (
-    .CI(sig00000001),
-    .DI(sig00000122),
-    .S(sig0000003f),
-    .O(sig00000032)
+    .CI(sig00000012),
+    .DI(sig00000133),
+    .S(sig00000050),
+    .O(sig00000043)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
   blk000000d6 (
-    .I0(sig00000122),
-    .I1(sig00000131),
-    .O(sig0000003f)
+    .I0(sig00000133),
+    .I1(sig00000142),
+    .O(sig00000050)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000d7 (
     .C(clk),
-    .D(sig000000d8),
-    .Q(sig00000129)
+    .D(sig0000018f),
+    .Q(p[47])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000d8 (
     .C(clk),
-    .D(sig000000d7),
-    .Q(sig00000128)
+    .D(sig0000018b),
+    .Q(p[46])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000d9 (
     .C(clk),
-    .D(sig000000d6),
-    .Q(sig00000127)
+    .D(sig0000018a),
+    .Q(p[45])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000da (
     .C(clk),
-    .D(sig000000d5),
-    .Q(sig00000126)
+    .D(sig00000189),
+    .Q(p[44])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000db (
     .C(clk),
-    .D(sig000000d3),
-    .Q(sig00000124)
+    .D(sig00000188),
+    .Q(p[43])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000dc (
     .C(clk),
-    .D(sig000000d2),
-    .Q(sig00000123)
+    .D(sig00000187),
+    .Q(p[42])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000dd (
     .C(clk),
-    .D(sig000000d1),
-    .Q(sig00000122)
+    .D(sig00000186),
+    .Q(p[41])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000de (
     .C(clk),
-    .D(sig000000d0),
-    .Q(sig00000121)
+    .D(sig00000185),
+    .Q(p[40])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000df (
     .C(clk),
-    .D(sig000000cf),
-    .Q(sig00000120)
+    .D(sig00000184),
+    .Q(p[39])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e0 (
     .C(clk),
-    .D(sig000000ce),
-    .Q(sig0000011f)
+    .D(sig00000183),
+    .Q(p[38])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e1 (
     .C(clk),
-    .D(sig000000cd),
-    .Q(sig0000011e)
+    .D(sig00000182),
+    .Q(p[37])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e2 (
     .C(clk),
-    .D(sig000000cc),
-    .Q(sig0000011d)
+    .D(sig00000180),
+    .Q(p[36])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e3 (
     .C(clk),
-    .D(sig000000cb),
-    .Q(sig0000011c)
+    .D(sig0000017f),
+    .Q(p[35])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e4 (
     .C(clk),
-    .D(sig000000ca),
-    .Q(sig0000011b)
+    .D(sig0000017e),
+    .Q(p[34])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e5 (
     .C(clk),
-    .D(sig000000e0),
-    .Q(sig00000130)
+    .D(sig0000017d),
+    .Q(p[33])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e6 (
     .C(clk),
-    .D(sig000000df),
-    .Q(sig0000012f)
+    .D(sig0000017c),
+    .Q(p[32])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e7 (
     .C(clk),
-    .D(sig000000de),
-    .Q(sig0000012e)
+    .D(sig0000017b),
+    .Q(p[31])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e8 (
     .C(clk),
-    .D(sig000000dd),
-    .Q(sig0000012d)
+    .D(sig0000017a),
+    .Q(p[30])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000e9 (
     .C(clk),
-    .D(sig000000dc),
-    .Q(sig0000012c)
+    .D(sig00000179),
+    .Q(p[29])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000ea (
     .C(clk),
-    .D(sig000000db),
-    .Q(sig0000012b)
+    .D(sig00000178),
+    .Q(p[28])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000eb (
     .C(clk),
-    .D(sig000000da),
-    .Q(sig0000012a)
+    .D(sig00000177),
+    .Q(p[27])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000ec (
     .C(clk),
-    .D(sig000000d9),
-    .Q(sig00000125)
+    .D(sig00000194),
+    .Q(p[26])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000ed (
     .C(clk),
-    .D(sig000000d4),
-    .Q(sig0000011a)
+    .D(sig00000193),
+    .Q(p[25])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000ee (
     .C(clk),
-    .D(sig000000c9),
-    .Q(sig00000119)
+    .D(sig00000192),
+    .Q(p[24])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000ef (
     .C(clk),
-    .D(sig000000c0),
-    .Q(sig00000111)
+    .D(sig00000191),
+    .Q(p[23])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f0 (
     .C(clk),
-    .D(sig000000bf),
-    .Q(sig00000110)
+    .D(sig00000190),
+    .Q(p[22])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f1 (
     .C(clk),
-    .D(sig000000be),
-    .Q(sig0000010f)
+    .D(sig0000018e),
+    .Q(p[21])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f2 (
     .C(clk),
-    .D(sig000000bd),
-    .Q(sig0000010e)
+    .D(sig0000018d),
+    .Q(p[20])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f3 (
     .C(clk),
-    .D(sig000000bb),
-    .Q(sig0000010c)
+    .D(sig0000018c),
+    .Q(p[19])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f4 (
     .C(clk),
-    .D(sig000000ba),
-    .Q(sig0000010b)
+    .D(sig00000181),
+    .Q(p[18])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f5 (
     .C(clk),
-    .D(sig000000b9),
-    .Q(sig0000010a)
+    .D(sig00000176),
+    .Q(p[17])
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f6 (
     .C(clk),
-    .D(sig000000b8),
-    .Q(sig00000109)
+    .D(sig000000f6),
+    .Q(sig00000147)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f7 (
     .C(clk),
-    .D(sig000000b7),
-    .Q(sig00000108)
+    .D(sig000000f5),
+    .Q(sig00000146)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f8 (
     .C(clk),
-    .D(sig000000b6),
-    .Q(sig00000107)
+    .D(sig000000f4),
+    .Q(sig00000145)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000f9 (
     .C(clk),
-    .D(sig000000b5),
-    .Q(sig00000106)
+    .D(sig000000f3),
+    .Q(sig00000144)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000fa (
     .C(clk),
-    .D(sig000000b4),
-    .Q(sig00000105)
+    .D(sig000000ff),
+    .Q(sig0000014f)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000fb (
     .C(clk),
-    .D(sig000000b3),
-    .Q(sig00000104)
+    .D(sig000000fe),
+    .Q(sig0000014e)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000fc (
     .C(clk),
-    .D(sig000000b2),
-    .Q(sig00000103)
+    .D(sig000000fd),
+    .Q(sig0000014d)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000fd (
     .C(clk),
-    .D(sig000000c8),
-    .Q(sig00000118)
+    .D(sig000000fc),
+    .Q(sig0000014c)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000fe (
     .C(clk),
-    .D(sig000000c7),
-    .Q(sig00000117)
+    .D(sig000000fb),
+    .Q(sig0000014b)
   );
   FD #(
     .INIT ( 1'b0 ))
   blk000000ff (
     .C(clk),
-    .D(sig000000c6),
-    .Q(sig00000116)
+    .D(sig000000fa),
+    .Q(sig0000014a)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000100 (
+    .C(clk),
+    .D(sig000000f9),
+    .Q(sig00000149)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000101 (
+    .C(clk),
+    .D(sig000000f8),
+    .Q(sig00000148)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000102 (
+    .C(clk),
+    .D(sig000000f7),
+    .Q(sig00000143)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000103 (
+    .C(clk),
+    .D(sig000000f2),
+    .Q(sig00000142)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000104 (
+    .C(clk),
+    .D(sig000000e9),
+    .Q(sig0000013a)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000105 (
+    .C(clk),
+    .D(sig000000e8),
+    .Q(sig00000139)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000106 (
+    .C(clk),
+    .D(sig000000e7),
+    .Q(sig00000138)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000107 (
+    .C(clk),
+    .D(sig000000e6),
+    .Q(sig00000137)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000108 (
+    .C(clk),
+    .D(sig000000e4),
+    .Q(sig00000135)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000109 (
+    .C(clk),
+    .D(sig000000e3),
+    .Q(sig00000134)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000010a (
+    .C(clk),
+    .D(sig000000e2),
+    .Q(sig00000133)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000010b (
+    .C(clk),
+    .D(sig000000e1),
+    .Q(sig00000132)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000010c (
+    .C(clk),
+    .D(sig000000e0),
+    .Q(sig00000131)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000010d (
+    .C(clk),
+    .D(sig000000df),
+    .Q(sig00000130)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000010e (
+    .C(clk),
+    .D(sig000000de),
+    .Q(sig0000012f)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000010f (
+    .C(clk),
+    .D(sig000000dd),
+    .Q(sig0000012e)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000110 (
+    .C(clk),
+    .D(sig000000dc),
+    .Q(sig0000012d)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000111 (
+    .C(clk),
+    .D(sig000000db),
+    .Q(sig0000012c)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000112 (
+    .C(clk),
+    .D(sig000000f1),
+    .Q(sig00000141)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000113 (
+    .C(clk),
+    .D(sig000000f0),
+    .Q(sig00000140)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000114 (
+    .C(clk),
+    .D(sig000000ef),
+    .Q(sig0000013f)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000115 (
+    .C(clk),
+    .D(sig000000ee),
+    .Q(sig0000013e)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000116 (
+    .C(clk),
+    .D(sig000000ed),
+    .Q(sig0000013d)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000117 (
+    .C(clk),
+    .D(sig000000ec),
+    .Q(sig0000013c)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000118 (
+    .C(clk),
+    .D(sig000000eb),
+    .Q(sig0000013b)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk00000119 (
+    .C(clk),
+    .D(sig000000ea),
+    .Q(sig00000136)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000011a (
+    .C(clk),
+    .D(sig000000e5),
+    .Q(sig0000012b)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000011b (
+    .C(clk),
+    .D(sig000000da),
+    .Q(sig0000012a)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000011c (
+    .C(clk),
+    .D(sig000000d1),
+    .Q(sig00000122)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000011d (
+    .C(clk),
+    .D(sig000000d0),
+    .Q(sig00000121)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000011e (
+    .C(clk),
+    .D(sig000000cf),
+    .Q(sig00000120)
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  blk0000011f (
+    .C(clk),
+    .D(sig000000ce),
+    .Q(sig0000011f)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000100 (
+  blk00000120 (
     .C(clk),
-    .D(sig000000c5),
-    .Q(sig00000115)
+    .D(sig000000cc),
+    .Q(sig0000011d)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000101 (
+  blk00000121 (
     .C(clk),
-    .D(sig000000c4),
-    .Q(sig00000114)
+    .D(sig000000cb),
+    .Q(sig0000011c)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000102 (
+  blk00000122 (
     .C(clk),
-    .D(sig000000c3),
-    .Q(sig00000113)
+    .D(sig000000ca),
+    .Q(sig0000011b)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000103 (
+  blk00000123 (
     .C(clk),
-    .D(sig000000c2),
-    .Q(sig00000112)
+    .D(sig000000c9),
+    .Q(sig0000011a)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000104 (
+  blk00000124 (
     .C(clk),
-    .D(sig000000c1),
-    .Q(sig0000010d)
+    .D(sig000000c8),
+    .Q(sig00000119)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000105 (
+  blk00000125 (
     .C(clk),
-    .D(sig000000bc),
-    .Q(sig00000102)
+    .D(sig000000c7),
+    .Q(sig00000118)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000106 (
+  blk00000126 (
     .C(clk),
-    .D(sig000000b1),
-    .Q(sig00000101)
+    .D(sig000000c6),
+    .Q(sig00000117)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000107 (
+  blk00000127 (
     .C(clk),
-    .D(sig000000e5),
-    .Q(sig00000136)
+    .D(sig000000c5),
+    .Q(sig00000116)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000108 (
+  blk00000128 (
     .C(clk),
-    .D(sig000000e4),
-    .Q(sig00000135)
+    .D(sig000000c4),
+    .Q(sig00000115)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000109 (
+  blk00000129 (
     .C(clk),
-    .D(sig000000e3),
-    .Q(sig00000134)
+    .D(sig000000c3),
+    .Q(sig00000114)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000010a (
+  blk0000012a (
     .C(clk),
-    .D(sig000000e2),
-    .Q(sig00000133)
+    .D(sig000000d9),
+    .Q(sig00000129)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000010b (
+  blk0000012b (
     .C(clk),
-    .D(sig000000ee),
-    .Q(sig0000013e)
+    .D(sig000000d8),
+    .Q(sig00000128)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000010c (
+  blk0000012c (
     .C(clk),
-    .D(sig000000ed),
-    .Q(sig0000013d)
+    .D(sig000000d7),
+    .Q(sig00000127)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000010d (
+  blk0000012d (
     .C(clk),
-    .D(sig000000ec),
-    .Q(sig0000013c)
+    .D(sig000000d6),
+    .Q(sig00000126)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000010e (
+  blk0000012e (
     .C(clk),
-    .D(sig000000eb),
-    .Q(sig0000013b)
+    .D(sig000000d5),
+    .Q(sig00000125)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000010f (
+  blk0000012f (
     .C(clk),
-    .D(sig000000ea),
-    .Q(sig0000013a)
+    .D(sig000000d4),
+    .Q(sig00000124)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000110 (
+  blk00000130 (
     .C(clk),
-    .D(sig000000e9),
-    .Q(sig00000139)
+    .D(sig000000d3),
+    .Q(sig00000123)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000111 (
+  blk00000131 (
     .C(clk),
-    .D(sig000000e8),
-    .Q(sig00000138)
+    .D(sig000000d2),
+    .Q(sig0000011e)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000112 (
+  blk00000132 (
     .C(clk),
-    .D(sig000000e7),
-    .Q(sig00000137)
+    .D(sig000000cd),
+    .Q(sig00000113)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000113 (
+  blk00000133 (
     .C(clk),
-    .D(sig000000e6),
-    .Q(sig00000132)
+    .D(sig000000c2),
+    .Q(sig00000112)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000114 (
+  blk00000134 (
     .C(clk),
-    .D(sig000000e1),
-    .Q(sig00000131)
+    .D(sig000000ba),
+    .Q(sig00000111)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000115 (
+  blk00000135 (
     .C(clk),
-    .D(sig000000a9),
-    .Q(sig00000100)
+    .D(sig000000b9),
+    .Q(sig00000110)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000116 (
+  blk00000136 (
     .C(clk),
-    .D(sig000000a8),
-    .Q(sig000000ff)
+    .D(sig000000b8),
+    .Q(sig0000010f)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000117 (
+  blk00000137 (
     .C(clk),
-    .D(sig000000a7),
-    .Q(sig000000fe)
+    .D(sig000000b7),
+    .Q(sig0000010e)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000118 (
+  blk00000138 (
     .C(clk),
-    .D(sig000000a6),
-    .Q(sig000000fd)
+    .D(sig000000b6),
+    .Q(sig0000010d)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000119 (
+  blk00000139 (
     .C(clk),
-    .D(sig000000a5),
-    .Q(sig000000fc)
+    .D(sig000000b4),
+    .Q(sig0000010c)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000011a (
+  blk0000013a (
     .C(clk),
-    .D(sig000000a3),
-    .Q(sig000000fb)
+    .D(sig000000b3),
+    .Q(sig0000010b)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000011b (
+  blk0000013b (
     .C(clk),
-    .D(sig000000a2),
-    .Q(sig000000fa)
+    .D(sig000000b2),
+    .Q(sig0000010a)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000011c (
+  blk0000013c (
     .C(clk),
-    .D(sig000000a1),
-    .Q(sig000000f9)
+    .D(sig000000b1),
+    .Q(sig00000109)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000011d (
+  blk0000013d (
     .C(clk),
-    .D(sig000000a0),
-    .Q(sig000000f8)
+    .D(sig000000b0),
+    .Q(sig00000108)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000011e (
+  blk0000013e (
     .C(clk),
-    .D(sig0000009f),
-    .Q(sig000000f7)
+    .D(sig000000af),
+    .Q(sig00000107)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000011f (
+  blk0000013f (
     .C(clk),
-    .D(sig0000009e),
-    .Q(sig000000f6)
+    .D(sig000000ae),
+    .Q(sig00000106)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000120 (
+  blk00000140 (
     .C(clk),
-    .D(sig0000009d),
-    .Q(sig000000f5)
+    .D(sig000000ad),
+    .Q(sig00000105)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000121 (
+  blk00000141 (
     .C(clk),
-    .D(sig0000009c),
-    .Q(sig000000f4)
+    .D(sig000000ac),
+    .Q(sig00000104)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000122 (
+  blk00000142 (
     .C(clk),
-    .D(sig0000009b),
-    .Q(sig000000f3)
+    .D(sig000000ab),
+    .Q(sig00000103)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000123 (
+  blk00000143 (
     .C(clk),
-    .D(sig0000009a),
-    .Q(sig000000f2)
+    .D(sig000000a9),
+    .Q(sig00000102)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000124 (
+  blk00000144 (
     .C(clk),
-    .D(sig00000098),
-    .Q(sig000000f1)
+    .D(sig000000a8),
+    .Q(sig00000101)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000125 (
+  blk00000145 (
     .C(clk),
-    .D(sig00000097),
-    .Q(sig000000f0)
+    .D(sig000000a7),
+    .Q(sig00000100)
+  );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000146 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000a4),
+    .Q(sig00000007)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000126 (
+  blk00000147 (
     .C(clk),
-    .D(sig00000096),
-    .Q(sig000000ef)
+    .D(sig00000007),
+    .Q(p[14])
+  );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000148 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000a6),
+    .Q(sig00000009)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000127 (
+  blk00000149 (
     .C(clk),
-    .D(sig00000095),
+    .D(sig00000009),
     .Q(p[16])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk0000014a (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000a5),
+    .Q(sig00000008)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000128 (
+  blk0000014b (
     .C(clk),
-    .D(sig00000094),
+    .D(sig00000008),
     .Q(p[15])
   );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk00000129 (
-    .C(clk),
-    .D(sig00000093),
-    .Q(p[14])
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk0000014c (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000a3),
+    .Q(sig00000006)
   );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000012a (
+  blk0000014d (
     .C(clk),
-    .D(sig00000092),
+    .D(sig00000006),
     .Q(p[13])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk0000014e (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000a2),
+    .Q(sig00000005)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000012b (
+  blk0000014f (
     .C(clk),
-    .D(sig00000091),
+    .D(sig00000005),
     .Q(p[12])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000150 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000a1),
+    .Q(sig00000004)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000012c (
+  blk00000151 (
     .C(clk),
-    .D(sig00000090),
+    .D(sig00000004),
     .Q(p[11])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000152 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000a0),
+    .Q(sig00000003)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000012d (
+  blk00000153 (
     .C(clk),
-    .D(sig0000008f),
+    .D(sig00000003),
     .Q(p[10])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000154 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000c1),
+    .Q(sig00000011)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000012e (
+  blk00000155 (
     .C(clk),
-    .D(sig000000b0),
+    .D(sig00000011),
     .Q(p[9])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000156 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000c0),
+    .Q(sig00000010)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk0000012f (
+  blk00000157 (
     .C(clk),
-    .D(sig000000af),
+    .D(sig00000010),
     .Q(p[8])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000158 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000bf),
+    .Q(sig0000000f)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000130 (
+  blk00000159 (
     .C(clk),
-    .D(sig000000ae),
+    .D(sig0000000f),
     .Q(p[7])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk0000015a (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000be),
+    .Q(sig0000000e)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000131 (
+  blk0000015b (
     .C(clk),
-    .D(sig000000ad),
+    .D(sig0000000e),
     .Q(p[6])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk0000015c (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000bd),
+    .Q(sig0000000d)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000132 (
+  blk0000015d (
     .C(clk),
-    .D(sig000000ac),
+    .D(sig0000000d),
     .Q(p[5])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk0000015e (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000bc),
+    .Q(sig0000000c)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000133 (
+  blk0000015f (
     .C(clk),
-    .D(sig000000ab),
+    .D(sig0000000c),
     .Q(p[4])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000160 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000bb),
+    .Q(sig0000000b)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000134 (
+  blk00000161 (
     .C(clk),
-    .D(sig000000aa),
+    .D(sig0000000b),
     .Q(p[3])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000162 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000b5),
+    .Q(sig0000000a)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000135 (
+  blk00000163 (
     .C(clk),
-    .D(sig000000a4),
+    .D(sig0000000a),
     .Q(p[2])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000164 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig000000aa),
+    .Q(sig00000002)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000136 (
+  blk00000165 (
     .C(clk),
-    .D(sig00000099),
+    .D(sig00000002),
     .Q(p[1])
   );
+  SRL16 #(
+    .INIT ( 16'h0000 ))
+  blk00000166 (
+    .A0(sig00000012),
+    .A1(sig00000012),
+    .A2(sig00000012),
+    .A3(sig00000012),
+    .CLK(clk),
+    .D(sig0000009f),
+    .Q(sig00000001)
+  );
   FD #(
     .INIT ( 1'b0 ))
-  blk00000137 (
+  blk00000167 (
     .C(clk),
-    .D(sig0000008e),
+    .D(sig00000001),
     .Q(p[0])
   );
 

+ 3 - 3
verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.2
-# Date: Fri Oct 21 20:38:07 2011
+# Date: Mon Oct 24 22:04:01 2011
 #
 ##############################################################
 #
@@ -49,7 +49,7 @@ CSET multtype=Parallel_Multiplier
 CSET optgoal=Speed
 CSET outputwidthhigh=47
 CSET outputwidthlow=0
-CSET pipestages=2
+CSET pipestages=3
 CSET portatype=Signed
 CSET portawidth=24
 CSET portbtype=Signed
@@ -65,4 +65,4 @@ CSET zerodetect=false
 MISC pkg_timestamp=2011-06-21T06:26:54.000Z
 # END Extra information
 GENERATE
-# CRC: efe4d30e
+# CRC: fd22ef14

+ 4 - 310
verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise

@@ -29,335 +29,29 @@
   </files>
 
   <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|cx4_mul" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="cx4_mul.ngc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cx4_mul" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="cx4_mul" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="cx4_mul_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="cx4_mul_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="cx4_mul_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="cx4_mul_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_mul" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-21T22:38:29" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BA4F9A4C077E07CDE90A18AE4A7F1BA5" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-25T00:04:25" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="384E11781B113D7487AFCF863F4DA087" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>

+ 2 - 2
verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v

@@ -83,11 +83,11 @@ output [15 : 0] doutb;
     .C_HAS_RSTB(0),
     .C_HAS_SOFTECC_INPUT_REGS_A(0),
     .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-    .C_INIT_FILE_NAME("no_coe_file_loaded"),
+    .C_INIT_FILE_NAME("cx4_pgmrom.mif"),
     .C_INITA_VAL("0"),
     .C_INITB_VAL("0"),
     .C_INTERFACE_TYPE(0),
-    .C_LOAD_INIT_FILE(0),
+    .C_LOAD_INIT_FILE(1),
     .C_MEM_TYPE(1),
     .C_MUX_PIPELINE_STAGES(0),
     .C_PRIM_TYPE(1),

+ 4 - 4
verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.2
-# Date: Tue Oct 18 18:45:53 2011
+# Date: Sun Oct 23 22:07:47 2011
 #
 ##############################################################
 #
@@ -46,7 +46,7 @@ CSET axi_id_width=4
 CSET axi_slave_type=Memory_Slave
 CSET axi_type=AXI4_Full
 CSET byte_size=9
-CSET coe_file=no_coe_file_loaded
+CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes_cx4/cx4_e.coe
 CSET collision_warnings=ALL
 CSET component_name=cx4_pgmrom
 CSET disable_collision_warnings=false
@@ -58,7 +58,7 @@ CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
 CSET fill_remaining_memory_locations=false
 CSET interface_type=Native
-CSET load_init_file=false
+CSET load_init_file=true
 CSET memory_type=Simple_Dual_Port_RAM
 CSET operating_mode_a=WRITE_FIRST
 CSET operating_mode_b=WRITE_FIRST
@@ -102,4 +102,4 @@ CSET write_width_b=16
 MISC pkg_timestamp=2011-03-11T08:24:14.000Z
 # END Extra information
 GENERATE
-# CRC: 30264765
+# CRC: a9280b11

+ 2 - 2
verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise

@@ -50,8 +50,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_pgmrom" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-18T20:46:37" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="794C12953A9C2D6BA0C9CD2CFBCA719F" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-24T00:08:31" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C14775871011A35EE55463DDAA37D8AF" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>

+ 12 - 4
verilog/sd2snes_cx4/main.v

@@ -106,6 +106,10 @@ wire [7:0] CX4_SNES_DATA_OUT;
 wire [23:0] MAPPED_SNES_ADDR;
 wire ROM_ADDR0;
 
+wire [23:0] cx4_datrom_data;
+wire [9:0] cx4_datrom_addr;
+wire cx4_datrom_we;
+
 sd_dma snes_sd_dma(
   .CLK(CLK2),
   .SD_DAT(SD_DAT),
@@ -226,7 +230,11 @@ mcu_cmd snes_mcu_cmd(
   .mcu_rrq(MCU_RRQ),
   .mcu_wrq(MCU_WRQ),
   .mcu_rq_rdy(MCU_RDY),
-  .use_msu1(use_msu1)
+  .use_msu1(use_msu1),
+  .cx4_datrom_addr_out(cx4_datrom_addr), 
+  .cx4_datrom_data_out(cx4_datrom_data), 
+  .cx4_datrom_we_out(cx4_datrom_we), 
+  .cx4_reset_out(cx4_reset)
 );
 
 wire [7:0] DCM_STATUS;
@@ -285,9 +293,9 @@ cx4 snes_cx4 (
     .nRD(SNES_READ), 
     .nWR(SNES_WRITE), 
     .CLK(CLK2), 
-    .DATROM_DI(DATROM_DI), 
-    .DATROM_WE(DATROM_WE), 
-    .DATROM_ADDR(DATROM_ADDR), 
+    .DATROM_DI(cx4_datrom_data), 
+    .DATROM_WE(cx4_datrom_we), 
+    .DATROM_ADDR(cx4_datrom_addr), 
     .BUS_DI(CX4_DINr), 
     .BUS_ADDR(CX4_ADDR), 
     .BUS_RRQ(CX4_RRQ), 

+ 11 - 11
verilog/sd2snes_cx4/sd2snes_cx4.xise

@@ -283,14 +283,14 @@
     <property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
@@ -311,7 +311,7 @@
     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
@@ -330,7 +330,7 @@
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -338,8 +338,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.main" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main/snes_cx4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.cx4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
@@ -361,13 +361,13 @@
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Search Directories for 'Include" xil_pn:value="../sd2snes" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.main" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.cx4" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="3" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -405,7 +405,7 @@
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/ikari/prj/sd2snes/verilog/sd2snes_cx4/smartxplorer_results/run4/currentprojectnavigatorsettingsct4.xds" xil_pn:valueState="non-default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>