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@@ -66,7 +66,7 @@ reg byte_received; // high when a byte has been received
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reg [7:0] byte_data_received;
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assign bit_cnt = bitcnt;
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-
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+/*
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always @(posedge clk)
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begin
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if(~SSEL_active) begin
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@@ -78,21 +78,36 @@ begin
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byte_data_received <= {byte_data_received[6:0], MOSI_data};
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end
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end
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+*/
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-always @(posedge clk)
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- byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);
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+always @(posedge SCK) begin
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+ if(SSEL) bitcnt <= 3'b000;
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+ else begin
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+ bitcnt <= bitcnt + 3'b001;
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+ byte_data_received <= {byte_data_received[6:0], MOSI};
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+ end
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+ if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1;
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+ else byte_received <= 1'b0;
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+end
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+
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+//always @(posedge clk)
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+// byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);
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+
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+reg [1:0] byte_received_r;
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+always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received};
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+wire byte_received_sync = (byte_received_r == 2'b01);
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always @(posedge clk) begin
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if(~SSEL_active)
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byte_cnt_r <= 16'h0000;
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- else if(byte_received) begin
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+ else if(byte_received_sync) begin
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byte_cnt_r <= byte_cnt_r + 16'h0001;
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end
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end
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reg [7:0] byte_data_sent;
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-always @(posedge clk) begin
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+/*always @(posedge clk) begin
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if(SSEL_active) begin
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if(SSEL_startmessage)
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byte_data_sent <= 8'h5A; // dummy byte
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@@ -105,8 +120,17 @@ always @(posedge clk) begin
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end
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end
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end
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+*/
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+always @(negedge SCK) begin
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+ if(~SSEL) begin
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+ if(bitcnt==3'b000)
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+ byte_data_sent <= input_data;
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+ else
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+ byte_data_sent <= {byte_data_sent[6:0], 1'b0};
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+ end
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+end
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-assign MISO = SSEL_active ? byte_data_sent[7] : 1'bZ; // send MSB first
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+assign MISO = ~SSEL ? input_data[7-bitcnt] /*byte_data_sent[7]*/ : 1'bZ; // send MSB first
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reg cmd_ready_r;
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reg param_ready_r;
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@@ -118,8 +142,8 @@ assign cmd_data = cmd_data_r;
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assign param_data = param_data_r;
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assign byte_cnt = byte_cnt_r;
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-always @(posedge clk) cmd_ready_r2 = byte_received && byte_cnt_r == 32'h0;
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-always @(posedge clk) param_ready_r2 = byte_received && byte_cnt_r > 32'h0;
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+always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
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+always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
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// fill registers
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always @(posedge clk) begin
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