Просмотр исходного кода

firmware, FPGA: fix for some SD cards

ikari 12 лет назад
Родитель
Сommit
68f255d75b
3 измененных файлов с 9 добавлено и 6 удалено
  1. 3 0
      src/sdnative.c
  2. 3 3
      verilog/sd2snes/sd_dma.v
  3. 3 3
      verilog/sd2snes_cx4/sd_dma.v

+ 3 - 0
src/sdnative.c

@@ -867,6 +867,9 @@ DRESULT sdn_initialize(BYTE drv) {
     if(rsp[1]&0x80) break;
   }
 
+  BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0;
+  BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1;
+
   ccs = (rsp[1]>>6) & 1; /* SDHC/XC */
 
   cmd_slow(ALL_SEND_CID, 0, 0x4d, NULL, rsp);

+ 3 - 3
verilog/sd2snes/sd_dma.v

@@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
 // we have 4 internal cycles per SD clock, 8 per RAM byte write
 reg [2:0] clkcnt;
 initial clkcnt = 3'b000;
-reg SD_CLKr;
-always @(posedge CLK) SD_CLKr <= clkcnt[1];
-assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ;
+reg [1:0] SD_CLKr;
+always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
+assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
 
 always @(posedge CLK) begin
   if(SD_DMA_EN_rising) begin

+ 3 - 3
verilog/sd2snes_cx4/sd_dma.v

@@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
 // we have 4 internal cycles per SD clock, 8 per RAM byte write
 reg [2:0] clkcnt;
 initial clkcnt = 3'b000;
-reg SD_CLKr;
-always @(posedge CLK) SD_CLKr <= clkcnt[1];
-assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ;
+reg [1:0] SD_CLKr;
+always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
+assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
 
 always @(posedge CLK) begin
   if(SD_DMA_EN_rising) begin