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@@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
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// we have 4 internal cycles per SD clock, 8 per RAM byte write
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reg [2:0] clkcnt;
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initial clkcnt = 3'b000;
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-reg SD_CLKr;
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-always @(posedge CLK) SD_CLKr <= clkcnt[1];
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-assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ;
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+reg [1:0] SD_CLKr;
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+always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
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+assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
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always @(posedge CLK) begin
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if(SD_DMA_EN_rising) begin
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