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@@ -31,9 +31,11 @@
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CCLK PD4 OUT
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INIT_B PD7 IN
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DIN PC7 OUT
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+ DONE PA3 IN
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*/
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#include <avr/pgmspace.h>
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+#include <util/delay.h>
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#include "fpga.h"
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#include "config.h"
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#include "uart.h"
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@@ -89,11 +91,13 @@ void fpga_init() {
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DDRC = _BV(PC7); // for FPGA config, PC7 is output
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DDRD |= _BV(PD3) | _BV(PD4); // PD3, PD4 are outputs
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+
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+ DDRA = ~_BV(PA3); // PA3 is input <- DONE
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set_cclk(0); // initial clk=0
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}
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int fpga_get_done(void) {
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- return 0;
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+ return PINA & _BV(PA3);
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}
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void fpga_postinit() {
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@@ -103,43 +107,45 @@ void fpga_postinit() {
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}
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void fpga_pgm(char* filename) {
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- set_prog_b(0);
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- uart_putc('P');
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- set_prog_b(1);
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- loop_until_bit_is_set(PIND, PD7);
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- uart_putc('p');
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+ int MAXRETRIES = 10;
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+// int retries = MAXRETRIES;
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+ do {
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+ set_prog_b(0);
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+ uart_putc('P');
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+ set_prog_b(1);
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+ loop_until_bit_is_set(PIND, PD7);
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+ uart_putc('p');
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+
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+ UINT bytes_read;
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+
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+ // open configware file
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+ file_open(filename, FA_READ);
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+ if(file_res) {
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+ uart_putc('?');
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+ uart_putc(0x30+file_res);
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+ return;
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+ }
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+ // file open successful
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+ set_cs_b(0);
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+ set_rdwr_b(0);
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-// FIL in;
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-// FRESULT res;
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- UINT bytes_read;
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-
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- // open configware file
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-// res=f_open(&in, filename, FA_READ);
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- file_open(filename, FA_READ);
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- if(file_res) {
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- uart_putc('?');
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- uart_putc(0x30+file_res);
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- return;
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- }
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- // file open successful
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- set_cs_b(0);
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- set_rdwr_b(0);
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-
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- for (;;) {
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-// res = f_read(&in, file_buf, sizeof(file_buf), &bytes_read);
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- bytes_read = file_read();
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- if (file_res || bytes_read == 0) break; // error or eof
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- for(int i=0; i<bytes_read; i++) {
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- //FPGA_SEND_BYTE(file_buf[i]);
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- FPGA_SEND_BYTE_SERIAL(file_buf[i]);
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+ for (;;) {
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+ bytes_read = file_read();
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+ if (file_res || bytes_read == 0) break; // error or eof
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+ for(int i=0; i<bytes_read; i++) {
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+ FPGA_SEND_BYTE_SERIAL(file_buf[i]);
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+ }
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}
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- }
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-
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- file_close();
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+ file_close();
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+ _delay_ms(10);
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+ } while (0); //(!fpga_get_done() && retries--);
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+ if(!fpga_get_done()) {
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+ dprintf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
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+ _delay_ms(50);
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+ }
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fpga_postinit();
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}
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-
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void set_avr_read(uint8_t val) {
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if(val) {
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PORTB |= _BV(PB3);
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@@ -210,3 +216,4 @@ void set_avr_bank(uint8_t val) {
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FPGA_SS_HIGH();
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SPI_SS_LOW();
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}
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+
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