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+/*******************************************************************************
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+* This file is owned and controlled by Xilinx and must be used *
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+* solely for design, simulation, implementation and creation of *
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+* design files limited to Xilinx devices or technologies. Use *
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+* with non-Xilinx devices or technologies is expressly prohibited *
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+* and immediately terminates your license. *
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+* *
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+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
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+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
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+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
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+* FOR A PARTICULAR PURPOSE. *
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+* *
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+* Xilinx products are not intended for use in life support *
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+* appliances, devices, or systems. Use in such applications are *
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+* expressly prohibited. *
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+* *
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+* (c) Copyright 1995-2009 Xilinx, Inc. *
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+* All rights reserved. *
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+*******************************************************************************/
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+// The synthesis directives "translate_off/translate_on" specified below are
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+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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+// tools. Ensure they are correct for your synthesis tool(s).
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+
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+// You must compile the wrapper file upd77c25_datrom.v when simulating
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+// the core, upd77c25_datrom. When compiling the wrapper file, be sure to
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+// reference the XilinxCoreLib Verilog simulation library. For detailed
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+// instructions, please refer to the "CORE Generator Help".
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+
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+`timescale 1ns/1ps
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+
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+module upd77c25_datrom(
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+ clka,
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+ wea,
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+ addra,
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+ dina,
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+ clkb,
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+ addrb,
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+ doutb);
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+
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+
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+input clka;
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+input [0 : 0] wea;
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+input [9 : 0] addra;
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+input [15 : 0] dina;
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+input clkb;
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+input [9 : 0] addrb;
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+output [15 : 0] doutb;
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+
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+// synthesis translate_off
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+
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+ BLK_MEM_GEN_V4_3 #(
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+ .C_ADDRA_WIDTH(10),
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+ .C_ADDRB_WIDTH(10),
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+ .C_ALGORITHM(1),
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+ .C_BYTE_SIZE(9),
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+ .C_COMMON_CLK(1),
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+ .C_DEFAULT_DATA("0"),
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+ .C_DISABLE_WARN_BHV_COLL(0),
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+ .C_DISABLE_WARN_BHV_RANGE(0),
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+ .C_FAMILY("spartan3"),
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+ .C_HAS_ENA(0),
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+ .C_HAS_ENB(0),
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+ .C_HAS_INJECTERR(0),
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+ .C_HAS_MEM_OUTPUT_REGS_A(0),
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+ .C_HAS_MEM_OUTPUT_REGS_B(0),
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+ .C_HAS_MUX_OUTPUT_REGS_A(0),
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+ .C_HAS_MUX_OUTPUT_REGS_B(0),
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+ .C_HAS_REGCEA(0),
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+ .C_HAS_REGCEB(0),
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+ .C_HAS_RSTA(0),
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+ .C_HAS_RSTB(0),
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+ .C_HAS_SOFTECC_INPUT_REGS_A(0),
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+ .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
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+ .C_INITA_VAL("0"),
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+ .C_INITB_VAL("0"),
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+ .C_INIT_FILE_NAME("upd77c25_datrom.mif"),
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+ .C_LOAD_INIT_FILE(1),
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+ .C_MEM_TYPE(1),
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+ .C_MUX_PIPELINE_STAGES(0),
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+ .C_PRIM_TYPE(1),
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+ .C_READ_DEPTH_A(1024),
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+ .C_READ_DEPTH_B(1024),
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+ .C_READ_WIDTH_A(16),
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+ .C_READ_WIDTH_B(16),
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+ .C_RSTRAM_A(0),
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+ .C_RSTRAM_B(0),
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+ .C_RST_PRIORITY_A("CE"),
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+ .C_RST_PRIORITY_B("CE"),
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+ .C_RST_TYPE("SYNC"),
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+ .C_SIM_COLLISION_CHECK("ALL"),
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+ .C_USE_BYTE_WEA(0),
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+ .C_USE_BYTE_WEB(0),
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+ .C_USE_DEFAULT_DATA(0),
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+ .C_USE_ECC(0),
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+ .C_USE_SOFTECC(0),
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+ .C_WEA_WIDTH(1),
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+ .C_WEB_WIDTH(1),
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+ .C_WRITE_DEPTH_A(1024),
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+ .C_WRITE_DEPTH_B(1024),
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+ .C_WRITE_MODE_A("WRITE_FIRST"),
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+ .C_WRITE_MODE_B("WRITE_FIRST"),
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+ .C_WRITE_WIDTH_A(16),
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+ .C_WRITE_WIDTH_B(16),
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+ .C_XDEVICEFAMILY("spartan3"))
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+ inst (
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+ .CLKA(clka),
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+ .WEA(wea),
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+ .ADDRA(addra),
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+ .DINA(dina),
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+ .CLKB(clkb),
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+ .ADDRB(addrb),
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+ .DOUTB(doutb),
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+ .RSTA(),
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+ .ENA(),
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+ .REGCEA(),
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+ .DOUTA(),
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+ .RSTB(),
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+ .ENB(),
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+ .REGCEB(),
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+ .WEB(),
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+ .DINB(),
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+ .INJECTSBITERR(),
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+ .INJECTDBITERR(),
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+ .SBITERR(),
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+ .DBITERR(),
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+ .RDADDRECC());
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+
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+
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+// synthesis translate_on
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+
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+// XST black box declaration
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+// box_type "black_box"
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+// synthesis attribute box_type of upd77c25_datrom is "black_box"
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+
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+endmodule
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+
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