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FPGA: Fix upd77c25 for 1chip consoles

ikari 13 yıl önce
ebeveyn
işleme
29f427821b

+ 7 - 2
verilog/sd2snes/address.v

@@ -163,17 +163,22 @@ assign srtc_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h280
 // DSP1 LoROM: DR=30-3f:8000-bfff; SR=30-3f:c000-ffff
 //          or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
 // DSP1 HiROM: DR=00-0f:6000-6fff; SR=00-0f:7000-7fff
-assign dspx_enable =
+wire dspx_enable_w =
   (MAPPER == 3'b101) ? 
     (ROM_MASK[20] ? 
       (SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
      :(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
     )
   :(MAPPER == 3'b100) ? 
-   (~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & &SNES_ADDR[14:13]/* & CS */)
+   (~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15] & &SNES_ADDR[14:13]/* & CS */)
   :1'b0;
 assign dspx_a0 = (MAPPER == 3'b101) ? SNES_ADDR[14]
                 :(MAPPER == 3'b100) ? SNES_ADDR[12]
                 :1'b1;
 
+reg [7:0] dspx_enable_r;
+initial dspx_enable_r = 8'b00000000;
+always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[6:0], dspx_enable_w};
+assign dspx_enable = &dspx_enable_r[5:2];
+
 endmodule

+ 1 - 1
verilog/sd2snes/ipcore_dir/dac_buf.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.1
-# Date: Thu Jun  2 00:39:53 2011
+# Date: Mon Jun 13 22:11:22 2011
 #
 ##############################################################
 #

+ 8 - 8
verilog/sd2snes/ipcore_dir/dac_buf.xise

@@ -16,19 +16,19 @@
 
   <files>
     <file xil_pn:name="dac_buf.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="dac_buf.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="dac_buf.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
@@ -57,8 +57,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="dac_buf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-02T02:40:57" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F04021A68581059F84CB48D6F91F3293" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-14T00:12:56" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="014920D0A865D4E8840F795EDFB8F8B9" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>

+ 1 - 1
verilog/sd2snes/ipcore_dir/msu_databuf.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.1
-# Date: Thu Jun  2 00:41:09 2011
+# Date: Mon Jun 13 22:13:20 2011
 #
 ##############################################################
 #

+ 2 - 2
verilog/sd2snes/ipcore_dir/msu_databuf.xise

@@ -57,8 +57,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="msu_databuf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-02T02:42:25" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5C4DFF8128BF7CCC1509FF9031261DA2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-14T00:14:59" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7648B026E1C3D2C8277D0047EFC3229D" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>

+ 1 - 1
verilog/sd2snes/ipcore_dir/upd77c25_datram.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.1
-# Date: Thu Jun  2 00:43:50 2011
+# Date: Mon Jun 13 22:15:19 2011
 #
 ##############################################################
 #

+ 8 - 8
verilog/sd2snes/ipcore_dir/upd77c25_datram.xise

@@ -16,19 +16,19 @@
 
   <files>
     <file xil_pn:name="upd77c25_datram.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="upd77c25_datram.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="upd77c25_datram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
@@ -57,8 +57,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="upd77c25_datram" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-02T02:44:44" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5247F245DC669D55BA9C67DF111B1080" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-12T12:22:04" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E74E33E1C0D35CC1635D07CFA337E6AE" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>

+ 3 - 3
verilog/sd2snes/ipcore_dir/upd77c25_datrom.v

@@ -65,7 +65,7 @@ output [15 : 0] doutb;
     .C_AXI_SLAVE_TYPE(0),
     .C_AXI_TYPE(1),
     .C_BYTE_SIZE(9),
-    .C_COMMON_CLK(1),
+    .C_COMMON_CLK(0),
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
@@ -84,11 +84,11 @@ output [15 : 0] doutb;
     .C_HAS_RSTB(0),
     .C_HAS_SOFTECC_INPUT_REGS_A(0),
     .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-    .C_INIT_FILE_NAME("upd77c25_datrom.mif"),
+    .C_INIT_FILE_NAME("no_coe_file_loaded"),
     .C_INITA_VAL("0"),
     .C_INITB_VAL("0"),
     .C_INTERFACE_TYPE(0),
-    .C_LOAD_INIT_FILE(1),
+    .C_LOAD_INIT_FILE(0),
     .C_MEM_TYPE(1),
     .C_MUX_PIPELINE_STAGES(0),
     .C_PRIM_TYPE(1),

+ 5 - 5
verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.1
-# Date: Thu Jun  9 10:19:40 2011
+# Date: Sun Jun 12 01:42:55 2011
 #
 ##############################################################
 #
@@ -37,12 +37,12 @@ SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
 CSET algorithm=Minimum_Area
-CSET assume_synchronous_clk=true
+CSET assume_synchronous_clk=false
 CSET axi_id_width=4
 CSET axi_slave_type=Memory_Slave
 CSET axi_type=AXI4_Full
 CSET byte_size=9
-CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp4_dat.coe
+CSET coe_file=no_coe_file_loaded
 CSET collision_warnings=ALL
 CSET component_name=upd77c25_datrom
 CSET disable_collision_warnings=false
@@ -54,7 +54,7 @@ CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
 CSET fill_remaining_memory_locations=false
 CSET interface_type=Native
-CSET load_init_file=true
+CSET load_init_file=false
 CSET memory_type=Simple_Dual_Port_RAM
 CSET operating_mode_a=WRITE_FIRST
 CSET operating_mode_b=WRITE_FIRST
@@ -98,4 +98,4 @@ CSET write_width_b=16
 MISC pkg_timestamp=2011-02-03T22:20:43.000Z
 # END Extra information
 GENERATE
-# CRC: 9cef39ed
+# CRC: 9692711f

+ 13 - 12
verilog/sd2snes/ipcore_dir/upd77c25_datrom.xise

@@ -20,23 +20,24 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="upd77c25_datrom.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="upd77c25_datrom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
     </file>
   </files>
 
   <properties>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
@@ -57,8 +58,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="upd77c25_datrom" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-09T12:20:38" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B24E105884805347406B2EAE26162387" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-12T03:44:29" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3B4D9B384A04055DA28D8E0A79BA07B6" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>

+ 2 - 2
verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v

@@ -84,11 +84,11 @@ output [23 : 0] doutb;
     .C_HAS_RSTB(0),
     .C_HAS_SOFTECC_INPUT_REGS_A(0),
     .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-    .C_INIT_FILE_NAME("upd77c25_pgmrom.mif"),
+    .C_INIT_FILE_NAME("no_coe_file_loaded"),
     .C_INITA_VAL("0"),
     .C_INITB_VAL("0"),
     .C_INTERFACE_TYPE(0),
-    .C_LOAD_INIT_FILE(1),
+    .C_LOAD_INIT_FILE(0),
     .C_MEM_TYPE(1),
     .C_MUX_PIPELINE_STAGES(0),
     .C_PRIM_TYPE(1),

+ 4 - 4
verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.1
-# Date: Thu Jun  9 08:57:56 2011
+# Date: Sun Jun 12 01:39:49 2011
 #
 ##############################################################
 #
@@ -42,7 +42,7 @@ CSET axi_id_width=4
 CSET axi_slave_type=Memory_Slave
 CSET axi_type=AXI4_Full
 CSET byte_size=9
-CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp4_pgm.coe
+CSET coe_file=no_coe_file_loaded
 CSET collision_warnings=ALL
 CSET component_name=upd77c25_pgmrom
 CSET disable_collision_warnings=false
@@ -54,7 +54,7 @@ CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
 CSET fill_remaining_memory_locations=false
 CSET interface_type=Native
-CSET load_init_file=true
+CSET load_init_file=false
 CSET memory_type=Simple_Dual_Port_RAM
 CSET operating_mode_a=WRITE_FIRST
 CSET operating_mode_b=WRITE_FIRST
@@ -98,4 +98,4 @@ CSET write_width_b=24
 MISC pkg_timestamp=2011-02-03T22:20:43.000Z
 # END Extra information
 GENERATE
-# CRC: 85a39b6f
+# CRC: b11006ad

+ 13 - 12
verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xise

@@ -20,23 +20,24 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="upd77c25_pgmrom.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="upd77c25_pgmrom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
     </file>
   </files>
 
   <properties>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
@@ -57,8 +58,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="upd77c25_pgmrom" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-09T10:59:21" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="92401B0F8DC628848EF92C534EB4C9BB" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-12T03:41:45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="174C0CDBB7F0BC979B3FC6BEF1530C97" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>

+ 5 - 4
verilog/sd2snes/main.ucf

@@ -1,6 +1,11 @@
 NET "CLKIN" TNM_NET = "CLKIN";
 TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
 //TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
+
+NET "p113_out" IOSTANDARD = LVCMOS33;
+NET "p113_out" LOC = P113;
+
+
 NET "SNES_CS" IOSTANDARD = LVCMOS33;
 NET "SNES_READ" IOSTANDARD = LVCMOS33;
 NET "SNES_WRITE" IOSTANDARD = LVCMOS33;
@@ -237,10 +242,6 @@ NET "ROM_BLE" LOC = P156;
 NET "ROM_BLE" IOSTANDARD = LVCMOS33;
 NET "ROM_BLE" DRIVE = 8;
 
-NET "IRQ_DIR" LOC = P113;
-NET "IRQ_DIR" IOSTANDARD = LVCMOS33;
-NET "IRQ_DIR" DRIVE = 8;
-
 
 NET "ROM_DATA[0]" LOC = P176;
 

+ 4 - 47
verilog/sd2snes/main.v

@@ -70,10 +70,14 @@ module main(
 	 inout SD_CLK
 	 
    /* debug */
+   ,
+   output p113_out
    //output DCM_IN_STOPPED,
    //output DCM_FX_STOPPED
    //input DCM_RST
     );
+assign p113_out = SNES_READ;
+
 wire [7:0] spi_cmd_data;
 wire [7:0] spi_param_data;
 wire [7:0] spi_input_data;
@@ -633,54 +637,7 @@ always @(posedge CLK2) begin
            endcase
        end
 end
-/*
-always @(posedge CLK2) begin
 
-   case (STATE)   
-      STATE_9: begin
-         STATEIDX <= 9;
-      end
-      
-      STATE_0: begin
-         STATEIDX <= 8;
-      end
-      
-      STATE_1: begin
-         STATEIDX <= 7;
-      end
-      
-      STATE_2: begin
-         STATEIDX <= 6;
-      end
-      
-      STATE_3: begin
-         STATEIDX <= 5;
-      end
-      
-      STATE_4: begin
-         STATEIDX <= 4;
-      end
-      
-      STATE_5: begin
-         STATEIDX <= 3;
-      end
-      
-      STATE_6: begin
-         STATEIDX <= 2;
-      end
-
-      STATE_7: begin
-         STATEIDX <= 1;
-      end
-
-      STATE_8: begin
-         STATEIDX <= 0;
-      end
-      default:
-         STATEIDX <= 9;
-   endcase      
-end
-*/
 // When in MCU mode, enable SRAM_WE according to MCU programming
 // else enable SRAM_WE according to state&cycle
 assign ROM_WE = !MCU_OVR ? MCU_WRITE

+ 23 - 39
verilog/sd2snes/sd2snes.xise

@@ -27,10 +27,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
-    <file xil_pn:name="dac_dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
@@ -75,61 +71,49 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
-    <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-    </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="main_tf.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="0"/>
-    </file>
+    <file xil_pn:name="main_tf.v" xil_pn:type="FILE_VERILOG"/>
     <file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_datrom.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="ipcore_dir/upd77c25_datram.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
-    <file xil_pn:name="ipcore_dir/pgmrom.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="ipcore_dir/upd77c25_datrom.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
-    <file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="ipcore_dir/msu_databuf.xise" xil_pn:type="FILE_COREGENISE">
+    <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="ipcore_dir/upd77c25_datrom.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
+    <file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="ipcore_dir/pgmrom.xise" xil_pn:type="FILE_COREGENISE">
+    <file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xise" xil_pn:type="FILE_COREGENISE">
+    <file xil_pn:name="ipcore_dir/msu_databuf.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
@@ -369,8 +353,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/updtest" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/updtest/uut/pgmrom" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.upd77c25_pgmrom" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
@@ -392,13 +376,13 @@
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Search Directories for 'Include" xil_pn:value="../sd2snes" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.upd77c25_pgmrom" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>

+ 78 - 89
verilog/sd2snes/upd77c25.v

@@ -18,7 +18,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 module upd77c25(
   input [7:0] DI,
-  output reg [7:0] DO,
+  output [7:0] DO,
   input A0,
   input nCS,
   input nRD,
@@ -44,6 +44,14 @@ module upd77c25(
   output [5:0] FL_B
 );
 	 
+parameter STATE_FETCH = 8'b00000001;
+parameter STATE_LOAD = 8'b00000010;
+parameter STATE_ALU1 = 8'b00000100;
+parameter STATE_ALU2 = 8'b00001000;
+parameter STATE_STORE = 8'b00010000;
+parameter STATE_NEXT = 8'b00100000;
+parameter STATE_IDLE1 = 8'b01000000;
+parameter STATE_IDLE2 = 8'b10000000;
 
 parameter I_OP = 2'b00;
 parameter I_RT = 2'b01;
@@ -63,7 +71,7 @@ reg [1:0] flags_s1;
 
 reg [10:0] pc;        // program counter
 
-reg [2:0] insn_state; // execute state
+reg [7:0] insn_state; // execute state
 
 reg [3:0] regs_dph;
 reg [3:0] regs_dpl;
@@ -123,8 +131,8 @@ upd77c25_datram datram (
 	.dina(ram_dina), // Bus [15 : 0] 
 	.douta(ram_douta)); // Bus [15 : 0] 
 
-assign ram_wea = ((op != I_JP) && op_dst == 4'b1111 && insn_state == 3'b100);
-assign ram_addra = {regs_dph | ((insn_state == 3'b101 && op_dst == 4'b1100) ? 4'b0100 : 4'b0000), regs_dpl};
+assign ram_wea = ((op != I_JP) && op_dst == 4'b1111 && insn_state == STATE_NEXT);
+assign ram_addra = {regs_dph | ((insn_state == STATE_ALU2 && op_dst == 4'b1100) ? 4'b0100 : 4'b0000), regs_dpl};
 reg signed [15:0] regs_k;
 reg signed [15:0] regs_l;
 reg [15:0] regs_trb;
@@ -170,11 +178,11 @@ assign FL_B = {flags_s1[1],flags_s0[1],flags_c[1],flags_z[1],flags_ov1[1],flags_
 
 initial begin
   alu_store = 2'b11;
-  insn_state = 3'b110;
+  insn_state = STATE_IDLE1;
   regs_sp = 4'b0000;
   pc = 11'b0;
   regs_sr = 16'b0;
-  regs_rp = 16'b0;
+  regs_rp = 16'h03ff;
   regs_dph = 4'b0;
   regs_dpl = 4'b0;
   regs_k = 16'b0;
@@ -196,25 +204,31 @@ always @(posedge CLK) begin
 
 end
 
-reg [5:0] reg_nCS_sreg;
-initial reg_nCS_sreg = 6'b111111;
-always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[4:0], nCS};
+reg [7:0] reg_nCS_sreg;
+initial reg_nCS_sreg = 8'b11111111;
+always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[6:0], nCS};
 
 reg [5:0] reg_oe_sreg;
 initial reg_oe_sreg = 6'b111111;
 always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD};
-wire reg_oe_falling = !nCS && (reg_oe_sreg[3:0] == 4'b1000);
+wire reg_oe_rising = !reg_nCS_sreg[2] && (reg_oe_sreg[5:0] == 6'b000001);
 
 reg [5:0] reg_we_sreg;
 initial reg_we_sreg = 6'b111111;
 always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR};
-wire reg_we_rising = !nCS && (reg_we_sreg[5:0] == 6'b000001);
+wire reg_we_rising = !reg_nCS_sreg[2] && (reg_we_sreg[5:0] == 6'b000001);
 
+reg [7:0] A0r;
+initial A0r = 8'b11111111;
+always @(posedge CLK) A0r <= {A0r[6:0], A0};
+
+reg [7:0] last_op;
+initial last_op = 8'h00;
 always @(posedge CLK) begin
   if(RST) begin
-    if((op_src == 4'b1000 && op[1] == 1'b0 && insn_state == 3'b011)
-    || (op_dst == 4'b0110 && op != 2'b10 && insn_state == 3'b011)) regs_sr[SR_RQM] <= 1'b1;
-    if((reg_we_rising) && (A0 == 1'b0)) begin
+    if((op_src == 4'b1000 && op[1] == 1'b0 && insn_state == STATE_STORE)
+    || (op_dst == 4'b0110 && op != 2'b10 && insn_state == STATE_STORE)) regs_sr[SR_RQM] <= 1'b1;
+    else if((reg_we_rising) && (A0r[3] == 1'b0)) begin
       if(!regs_sr[SR_DRC]) begin
         if(regs_sr[SR_DRS] == 1'b1) begin
           regs_sr[SR_RQM] <= 1'b0;
@@ -223,18 +237,14 @@ always @(posedge CLK) begin
         regs_sr[SR_RQM] <= 1'b0;
       end
     end
-    else if(reg_oe_falling && (A0 == 1'b0)) begin
-//      case(A0)
-//        1'b0: begin
-          if(!regs_sr[SR_DRC]) begin
-            if(regs_sr[SR_DRS] == 1'b1) begin
-              regs_sr[SR_RQM] <= 1'b0;
-            end
-          end else begin
-            regs_sr[SR_RQM] <= 1'b0;
-          end
-//        end
-//      endcase
+    else if(reg_oe_rising && (A0r[3] == 1'b0)) begin
+      if(!regs_sr[SR_DRC]) begin
+        if(regs_sr[SR_DRS] == 1'b1) begin
+          regs_sr[SR_RQM] <= 1'b0;
+        end
+      end else begin
+        regs_sr[SR_RQM] <= 1'b0;
+      end
     end
   end else begin
     regs_sr[SR_RQM] <= 1'b0;
@@ -243,7 +253,7 @@ end
 
 always @(posedge CLK) begin
   if(RST) begin
-    if(reg_we_rising && (A0 == 1'b0)) begin
+    if(reg_we_rising && (A0r[3] == 1'b0)) begin
       if(!regs_sr[SR_DRC]) begin
         if(regs_sr[SR_DRS] == 1'b0) begin
           regs_sr[SR_DRS] <= 1'b1;
@@ -251,8 +261,8 @@ always @(posedge CLK) begin
           regs_sr[SR_DRS] <= 1'b0;
         end
       end 
-    end else if(reg_oe_falling) begin
-      case(A0)
+    end else if(reg_oe_rising) begin
+      case(A0r[3])
         1'b0: begin
           if(!regs_sr[SR_DRC]) begin
             if(regs_sr[SR_DRS] == 1'b0) begin
@@ -271,7 +281,7 @@ end
 
 always @(posedge CLK) begin
   if(RST) begin
-    if(reg_we_rising && (A0 == 1'b0)) begin
+    if(reg_we_rising && (A0r[3] == 1'b0)) begin
       if(!regs_sr[SR_DRC]) begin
         if(regs_sr[SR_DRS] == 1'b0) begin
           regs_dr[7:0] <= DI;
@@ -281,7 +291,7 @@ always @(posedge CLK) begin
       end else begin
         regs_dr[7:0] <= DI;
       end
-    end else if(ld_dst == 4'b0110 && insn_state == 3'b011) begin
+    end else if(ld_dst == 4'b0110 && insn_state == STATE_STORE) begin
       if (op == I_OP || op == I_RT) regs_dr <= idb;
       else if (op == I_LD) regs_dr <= ld_id;
     end
@@ -290,34 +300,13 @@ always @(posedge CLK) begin
   end
 end
 
-always @(posedge CLK) begin
-  if(RST) begin
-    if(reg_oe_falling) begin
-      case(A0)
-        1'b0: begin
-          if(!regs_sr[SR_DRC]) begin
-            if(regs_sr[SR_DRS] == 1'b0) begin
-              DO <= regs_dr[7:0];
-            end else begin
-              DO <= regs_dr[15:8];
-            end
-          end else begin
-            DO <= regs_dr[7:0]; // regs_dr[7:0];
-          end
-        end
-        1'b1: DO <= regs_sr[15:8]; // regs_sr[15:8];
-      endcase
-    end
-  end else begin
-    DO <= 8'h00;
-  end
-end
+assign DO = (A0 ? regs_sr[15:8] : (regs_sr[SR_DRC] ? regs_dr[7:0] : (regs_sr[SR_DRS] ? regs_dr[15:8] : regs_dr[7:0])));
 
 always @(posedge CLK) begin
   if(RST) begin
     case(insn_state)
-      3'b000: begin
-        insn_state <= 3'b001;
+      STATE_FETCH: begin
+        insn_state <= STATE_LOAD;
         opcode <= opcode_w;
         op <= opcode_w[23:22];
         op_pselect <= opcode_w[21:20];
@@ -337,8 +326,8 @@ always @(posedge CLK) begin
         regs_m <= {mul_result[31], mul_result[29:15]};
         regs_n <= {mul_result[14:0], 1'b0};
       end
-      3'b001: begin
-        insn_state <= 3'b010;
+      STATE_LOAD: begin
+        insn_state <= STATE_ALU1;
         case(op)
           I_OP, I_RT: begin
             case(op_src)
@@ -360,8 +349,8 @@ always @(posedge CLK) begin
           end
         endcase
       end
-      3'b010: begin
-        insn_state <= 3'b101;
+      STATE_ALU1: begin
+        insn_state <= STATE_ALU2;
         case(op)
           I_OP, I_RT: begin        
             alu_q <= regs_ab[op_asl];
@@ -382,8 +371,30 @@ always @(posedge CLK) begin
           end
         endcase
       end
-      3'b011: begin
-        insn_state <= 3'b100;
+      STATE_ALU2: begin
+        insn_state <= STATE_STORE;
+        if(op[1] == 1'b0) begin
+          case(op_alu)
+            4'b0001: alu_r <= alu_q | alu_p;
+            4'b0010: alu_r <= alu_q & alu_p;
+            4'b0011: alu_r <= alu_q ^ alu_p;
+            4'b0100: alu_r <= alu_q - alu_p;
+            4'b0101: alu_r <= alu_q + alu_p;
+            4'b0110: alu_r <= alu_q - alu_p - flags_c[~op_asl];
+            4'b0111: alu_r <= alu_q + alu_p + flags_c[~op_asl];
+            4'b1000: alu_r <= alu_q - alu_p;
+            4'b1001: alu_r <= alu_q + alu_p;
+            4'b1010: alu_r <= ~alu_q;
+            4'b1011: alu_r <= {alu_q[15], alu_q[15:1]};
+            4'b1100: alu_r <= {alu_q[14:0], flags_c[~op_asl]};
+            4'b1101: alu_r <= {alu_q[13:0], 2'b11};
+            4'b1110: alu_r <= {alu_q[11:0], 4'b1111};
+            4'b1111: alu_r <= {alu_q[7:0], alu_q[15:8]};
+          endcase
+        end
+      end
+      STATE_STORE: begin
+        insn_state <= STATE_NEXT;
         case(op)
           I_OP, I_RT: begin
             case(op_dst)
@@ -534,8 +545,8 @@ always @(posedge CLK) begin
           end
         endcase
       end
-      3'b100: begin
-        insn_state <= 3'b110;
+      STATE_NEXT: begin
+        insn_state <= STATE_IDLE1;
 
         case(op)
           I_OP, I_RT: begin
@@ -569,34 +580,12 @@ always @(posedge CLK) begin
           end
         endcase
       end
-      3'b110: insn_state <= 3'b111;
-      3'b111: insn_state <= 3'b000;
+      STATE_IDLE1: insn_state <= STATE_IDLE2;
+      STATE_IDLE2: insn_state <= STATE_FETCH;
       
-      3'b101: begin
-        insn_state <= 3'b011;
-        if(op[1] == 1'b0) begin
-          case(op_alu)
-            4'b0001: alu_r <= alu_q | alu_p;
-            4'b0010: alu_r <= alu_q & alu_p;
-            4'b0011: alu_r <= alu_q ^ alu_p;
-            4'b0100: alu_r <= alu_q - alu_p;
-            4'b0101: alu_r <= alu_q + alu_p;
-            4'b0110: alu_r <= alu_q - alu_p - flags_c[~op_asl];
-            4'b0111: alu_r <= alu_q + alu_p + flags_c[~op_asl];
-            4'b1000: alu_r <= alu_q - alu_p;
-            4'b1001: alu_r <= alu_q + alu_p;
-            4'b1010: alu_r <= ~alu_q;
-            4'b1011: alu_r <= {alu_q[15], alu_q[15:1]};
-            4'b1100: alu_r <= {alu_q[14:0], flags_c[~op_asl]};
-            4'b1101: alu_r <= {alu_q[13:0], 2'b11};
-            4'b1110: alu_r <= {alu_q[11:0], 4'b1111};
-            4'b1111: alu_r <= {alu_q[7:0], alu_q[15:8]};
-          endcase
-        end
-      end
     endcase
   end else begin
-    insn_state <= 3'b110;
+    insn_state <= STATE_IDLE1;
     pc <= 11'b0;
     regs_sp <= 4'b0000;
     cond_true <= 0;
@@ -607,7 +596,7 @@ always @(posedge CLK) begin
     regs_sr[9] <= 0;
     regs_sr[8] <= 0;
     regs_sr[7] <= 0;
-    regs_rp <= 16'b0;
+    regs_rp <= 16'h03ff;
     regs_dph <= 4'b0;
     regs_dpl <= 4'b0;
     regs_k <= 16'b0;