testing.c 3.5 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <stdlib.h>
  21. #include <stdint.h>
  22. #include <util/delay.h>
  23. #include "shared_memory.h"
  24. #include "config.h"
  25. #include "sram.h"
  26. #include "debug.h"
  27. #include "crc.h"
  28. #include "info.h"
  29. #include "dump.h"
  30. void test_read_write()
  31. {
  32. uint8_t i;
  33. uint32_t addr;
  34. avr_bus_active();
  35. addr = 0x000000;
  36. i = 1;
  37. while (addr++ <= 0x0000ff) {
  38. sram_write(addr, i++);
  39. }
  40. addr = 0x000000;
  41. while (addr++ <= 0x0000ff) {
  42. info_P(PSTR("read addr=0x%08lx %x\n"), addr, sram_read(addr));
  43. }
  44. }
  45. void test_bulk_read_write()
  46. {
  47. uint8_t i;
  48. uint32_t addr;
  49. avr_bus_active();
  50. addr = 0x000000;
  51. i = 0;
  52. sram_bulk_write_start(addr);
  53. while (addr++ <= 0x8000) {
  54. sram_bulk_write(i++);
  55. sram_bulk_write_next();
  56. }
  57. sram_bulk_write_end();
  58. addr = 0x000000;
  59. sram_bulk_read_start(addr);
  60. while (addr <= 0x8000) {
  61. info_P(PSTR("addr=0x%08lx %x\n"), addr, sram_bulk_read());
  62. sram_bulk_read_next();
  63. addr++;
  64. }
  65. sram_bulk_read_end();
  66. }
  67. void test_non_zero_memory(uint32_t bottom_addr, uint32_t top_addr)
  68. {
  69. uint32_t addr = 0;
  70. uint8_t c;
  71. sram_bulk_read_start(bottom_addr);
  72. for (addr = bottom_addr; addr < top_addr; addr++) {
  73. c = sram_bulk_read();
  74. if (c != 0xff)
  75. info_P(PSTR("addr=0x%08lx c=0x%x\n"), addr, c);
  76. sram_bulk_read_next();
  77. }
  78. sram_bulk_read_end();
  79. }
  80. void test_memory_pattern(uint32_t bottom_addr, uint32_t top_addr,
  81. uint32_t bank_size)
  82. {
  83. uint32_t addr = 0;
  84. uint8_t pattern = 0x55;
  85. info_P(PSTR("test_memory_pattern: bottom_addr=0x%08lx top_addr=0x%08lx\n"),
  86. bottom_addr, top_addr);
  87. sram_bulk_write_start(bottom_addr);
  88. for (addr = bottom_addr; addr < top_addr; addr++) {
  89. if (addr % bank_size == 0) {
  90. pattern++;
  91. info_P(PSTR
  92. ("test_memory_pattern: write addr=0x%08lx pattern=0x%08lx\n"),
  93. addr, pattern);
  94. }
  95. sram_bulk_write(pattern);
  96. }
  97. sram_bulk_write_end();
  98. for (addr = bottom_addr; addr < top_addr; addr += bank_size) {
  99. info_P(PSTR
  100. ("test_memory_pattern: dump bottom_addr=0x%08lx top_addr=0x%08lx\n"),
  101. addr, addr + bank_size);
  102. dump_memory(addr, addr + bank_size);
  103. info_P(PSTR
  104. ("----------------------------------------------------------------\n"));
  105. }
  106. crc_check_bulk_memory((uint32_t) bottom_addr, top_addr, bank_size);
  107. }
  108. void test_crc()
  109. {
  110. info_P(PSTR("test_crc: clear\n"));
  111. avr_bus_active();
  112. sram_bulk_set(0x000000, 0x10000, 0xff);
  113. info_P(PSTR("test_crc: crc\n"));
  114. crc_check_bulk_memory(0x000000, 0x10000, 0x8000);
  115. info_P(PSTR("test_crc: check\n"));
  116. test_non_zero_memory(0x000000, 0x10000);
  117. }