sram.c 7.9 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <stdlib.h>
  21. #include <stdint.h>
  22. #include <avr/io.h>
  23. #include <util/delay.h> /* for _delay_ms() */
  24. #include "config.h"
  25. #include "sram.h"
  26. #include "uart.h"
  27. #include "debug.h"
  28. #include "info.h"
  29. uint32_t addr_current = 0;
  30. uint32_t addr_stash = 0;
  31. void sram_init(void)
  32. {
  33. /*-------------------------------------------------*/
  34. DDRA = 0x00;
  35. PORTA = 0x00;
  36. /*-------------------------------------------------*/
  37. DDRC |= ((1 << AVR_ADDR_LATCH_PIN)
  38. | (1 << AVR_ADDR_SCK_PIN)
  39. | (1 << AVR_ADDR_SER_PIN)
  40. | (1 << AVR_ADDR_LOAD_PIN)
  41. | (1 << AVR_ADDR_UP_PIN));
  42. DDRC &= ~((1 << SNES_WR_PIN)
  43. | (1 << AVR_BTLDR_EN_PIN));
  44. PORTC &= ~((1 << AVR_ADDR_LATCH_PIN)
  45. | (1 << AVR_ADDR_SCK_PIN)
  46. | (1 << SNES_WR_PIN));
  47. PORTC |= ((1 << AVR_ADDR_UP_PIN)
  48. | (1 << AVR_ADDR_LOAD_PIN));
  49. // | (1 << SNES_WR_PIN));
  50. /*-------------------------------------------------*/
  51. DDRB |= ((1 << AVR_RD_PIN)
  52. | (1 << AVR_WR_PIN)
  53. | (1 << AVR_CS_PIN)
  54. | (1 << SNES_IRQ_PIN));
  55. PORTB |= ((1 << AVR_RD_PIN)
  56. | (1 << AVR_WR_PIN)
  57. | (1 << AVR_CS_PIN)
  58. | (1 << SNES_IRQ_PIN));
  59. /*-------------------------------------------------*/
  60. DDRD |= ((1 << AVR_SNES_SW_PIN)
  61. | (1 << HI_LOROM_SW_PIN)
  62. | (1 << SNES_WR_EN_PIN));
  63. PORTD |= (1 << HI_LOROM_SW_PIN);
  64. PORTD &= ~((1 << AVR_SNES_SW_PIN)
  65. | (1 << SNES_WR_EN_PIN));
  66. /*-------------------------------------------------*/
  67. }
  68. void sreg_set(uint32_t addr)
  69. {
  70. uint8_t i = 24;
  71. debug_P(DEBUG_SREG, PSTR("sreg_set: addr=0x%08lx"), addr);
  72. while (i--) {
  73. if ((addr & (1L << i))) {
  74. debug_P(DEBUG_SREG, PSTR("1"));
  75. AVR_ADDR_SER_PORT |= (1 << AVR_ADDR_SER_PIN);
  76. } else {
  77. AVR_ADDR_SER_PORT &= ~(1 << AVR_ADDR_SER_PIN);
  78. debug_P(DEBUG_SREG, PSTR("0"));
  79. }
  80. AVR_ADDR_SCK_PORT |= (1 << AVR_ADDR_SCK_PIN);
  81. AVR_ADDR_SCK_PORT &= ~(1 << AVR_ADDR_SCK_PIN);
  82. }
  83. debug_P(DEBUG_SREG, PSTR("\n"));
  84. AVR_ADDR_LATCH_PORT |= (1 << AVR_ADDR_LATCH_PIN);
  85. AVR_ADDR_LATCH_PORT &= ~(1 << AVR_ADDR_LATCH_PIN);
  86. counter_load();
  87. }
  88. void sram_bulk_addr_save()
  89. {
  90. addr_stash = addr_current;
  91. debug_P(DEBUG_SRAM, PSTR("sram_bulk_addr_save: addr=0x%08lx\n\r"),
  92. addr_stash);
  93. }
  94. inline void sram_bulk_addr_restore()
  95. {
  96. debug_P(DEBUG_SRAM, PSTR("sram_bulk_addr_restore: addr=0x%08lx\n\r"),
  97. addr_stash);
  98. sram_bulk_write_start(addr_stash);
  99. }
  100. void sram_bulk_read_start(uint32_t addr)
  101. {
  102. debug_P(DEBUG_SRAM, PSTR("sram_bulk_read_start: addr=0x%08lx\n\r"), addr);
  103. addr_current = addr;
  104. avr_data_in();
  105. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  106. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  107. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  108. sreg_set(addr);
  109. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  110. asm volatile ("nop");
  111. asm volatile ("nop");
  112. asm volatile ("nop");
  113. asm volatile ("nop");
  114. asm volatile ("nop");
  115. asm volatile ("nop");
  116. }
  117. inline void sram_bulk_read_next(void)
  118. {
  119. addr_current++;
  120. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  121. counter_up();
  122. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  123. asm volatile ("nop");
  124. asm volatile ("nop");
  125. asm volatile ("nop");
  126. asm volatile ("nop");
  127. asm volatile ("nop");
  128. asm volatile ("nop");
  129. }
  130. inline uint8_t sram_bulk_read(void)
  131. {
  132. return AVR_DATA_PIN;
  133. }
  134. void sram_bulk_read_end(void)
  135. {
  136. debug_P(DEBUG_SRAM, PSTR("sram_bulk_read_end:\n"));
  137. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  138. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  139. avr_data_in();
  140. }
  141. uint8_t sram_read(uint32_t addr)
  142. {
  143. uint8_t byte;
  144. debug_P(DEBUG_SRAM_RAW, PSTR("sram_read: addr=0x%08lx\n\r"), addr);
  145. avr_data_in();
  146. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  147. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  148. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  149. sreg_set(addr);
  150. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  151. asm volatile ("nop");
  152. asm volatile ("nop");
  153. asm volatile ("nop");
  154. asm volatile ("nop");
  155. asm volatile ("nop");
  156. asm volatile ("nop");
  157. byte = AVR_DATA_PIN;
  158. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  159. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  160. avr_data_in();
  161. return byte;
  162. }
  163. uint16_t sram_read16_be(uint32_t addr)
  164. {
  165. uint8_t hi = sram_read(addr);
  166. uint8_t lo = sram_read(addr + 1);
  167. return (hi << 8 | lo);
  168. }
  169. void sram_bulk_write_start(uint32_t addr)
  170. {
  171. debug_P(DEBUG_SRAM, PSTR("sram_bulk_write_start: addr=0x%08lx\n\r"), addr);
  172. addr_current = addr;
  173. avr_data_out();
  174. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  175. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  176. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  177. sreg_set(addr);
  178. }
  179. inline void sram_bulk_write_next(void)
  180. {
  181. addr_current++;
  182. counter_up();
  183. }
  184. inline void sram_bulk_write(uint8_t data)
  185. {
  186. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  187. AVR_DATA_PORT = data;
  188. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  189. }
  190. void sram_bulk_write_end(void)
  191. {
  192. debug_P(DEBUG_SRAM, PSTR("sram_bulk_write_end:"));
  193. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  194. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  195. avr_data_in();
  196. }
  197. void sram_write(uint32_t addr, uint8_t data)
  198. {
  199. debug_P(DEBUG_SRAM_RAW, PSTR("sram_write: addr=0x%08lx data=%x\n\r"), addr,
  200. data);
  201. avr_data_out();
  202. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  203. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  204. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  205. sreg_set(addr);
  206. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  207. AVR_DATA_PORT = data;
  208. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  209. asm volatile ("nop");
  210. asm volatile ("nop");
  211. asm volatile ("nop");
  212. asm volatile ("nop");
  213. asm volatile ("nop");
  214. asm volatile ("nop");
  215. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  216. avr_data_in();
  217. }
  218. void sram_bulk_copy_from_buffer(uint32_t addr, uint8_t * src, uint32_t len)
  219. {
  220. uint32_t i;
  221. uint8_t *ptr = src;
  222. debug_P(DEBUG_SRAM,
  223. PSTR
  224. ("sram_bulk_copy_from_buffer: addr=0x%08lx src=0x%p len=%li\n\r"),
  225. addr, src, len);
  226. sram_bulk_write_start(addr);
  227. for (i = addr; i < (addr + len); i++) {
  228. sram_bulk_write(*ptr);
  229. // hack
  230. if ((i + 1) < (addr + len))
  231. sram_bulk_write_next();
  232. ptr++;
  233. }
  234. sram_bulk_write_end();
  235. }
  236. void sram_bulk_copy_into_buffer(uint32_t addr, uint8_t * dst, uint32_t len)
  237. {
  238. uint32_t i;
  239. // uint8_t *ptr = dst;
  240. debug_P(DEBUG_SRAM,
  241. PSTR
  242. ("sram_bulk_copy_into_buffer: addr=0x%08lx dst=0x%p len=%li\n\r"),
  243. addr, dst, len);
  244. sram_bulk_read_start(addr);
  245. for (i = addr; i < (addr + len); i++) {
  246. dst[i] = sram_bulk_read();
  247. sram_bulk_read_next();
  248. }
  249. sram_bulk_read_end();
  250. }
  251. void sram_bulk_set(uint32_t addr, uint32_t len, uint8_t value)
  252. {
  253. uint32_t i;
  254. debug_P(DEBUG_SRAM, PSTR("sram_bulk_set: addr=0x%08lx len=%li\n\r"), addr,
  255. len);
  256. sram_bulk_write_start(addr);
  257. for (i = addr; i < (addr + len); i++) {
  258. if (0 == i % 0xfff)
  259. debug_P(DEBUG_SRAM, PSTR("sram_bulk_set: addr=0x%08lx\n\r"), i);
  260. sram_bulk_write(value);
  261. sram_bulk_write_next();
  262. }
  263. sram_bulk_write_end();
  264. }