usbdrvasm18-crc.inc 30 KB

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  1. /* Name: usbdrvasm18.inc
  2. * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
  3. * Author: Lukas Schrittwieser (based on 20 MHz usbdrvasm20.inc by Jeroen Benschop)
  4. * Creation Date: 2009-01-20
  5. * Tabsize: 4
  6. * Copyright: (c) 2008 by Lukas Schrittwieser and OBJECTIVE DEVELOPMENT Software GmbH
  7. * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
  8. */
  9. /* Do not link this file! Link usbdrvasm.S instead, which includes the
  10. * appropriate implementation!
  11. */
  12. /*
  13. General Description:
  14. This file is the 18 MHz version of the asssembler part of the USB driver. It
  15. requires a 18 MHz crystal (not a ceramic resonator and not a calibrated RC
  16. oscillator).
  17. See usbdrv.h for a description of the entire driver.
  18. Since almost all of this code is timing critical, don't change unless you
  19. really know what you are doing! Many parts require not only a maximum number
  20. of CPU cycles, but even an exact number of cycles!
  21. */
  22. ;max stack usage: [ret(2), YL, SREG, YH, [sofError], bitcnt(x5), shift, x1, x2, x3, x4, cnt, ZL, ZH] = 14 bytes
  23. ;nominal frequency: 18 MHz -> 12 cycles per bit
  24. ; Numbers in brackets are clocks counted from center of last sync bit
  25. ; when instruction starts
  26. ;register use in receive loop to receive the data bytes:
  27. ; shift assembles the byte currently being received
  28. ; x1 holds the D+ and D- line state
  29. ; x2 holds the previous line state
  30. ; cnt holds the number of bytes left in the receive buffer
  31. ; x3 holds the higher crc byte (see algorithm below)
  32. ; x4 is used as temporary register for the crc algorithm
  33. ; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further
  34. ; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted
  35. ; zl lower crc value and crc table index
  36. ; zh used for crc table accesses
  37. ;--------------------------------------------------------------------------------------------------------------
  38. ; CRC mods:
  39. ; table driven crc checker, Z points to table in prog space
  40. ; ZL is the lower crc byte, x3 is the higher crc byte
  41. ; x4 is used as temp register to store different results
  42. ; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the
  43. ; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial
  44. ; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc.
  45. ; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and
  46. ; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF
  47. ; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version
  48. ;--------------------------------------------------------------------------------------------------------------
  49. ; CRC algorithm:
  50. ; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form
  51. ; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order
  52. ; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i
  53. ; propose a research on CRC :-) )
  54. ; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc
  55. ; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3
  56. ; (its destination).
  57. ; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as
  58. ; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored
  59. ; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc
  60. ; calculation is done.
  61. ; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec)
  62. ; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized
  63. ; to a magic number which results in a crc value of 0xFFFF after the first complete byte.
  64. ;
  65. ; This algorithm is split into the extra cycles of the different bits:
  66. ; bit7: XOR the received byte to ZL
  67. ; bit5: load the new high byte to x4
  68. ; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value)
  69. ; move x4 (the new high byte) to x3, the crc value is ready
  70. ;
  71. macro POP_STANDARD ; 18 cycles
  72. pop ZH
  73. pop ZL
  74. pop cnt
  75. pop x5
  76. pop x3
  77. pop x2
  78. pop x1
  79. pop shift
  80. pop x4
  81. endm
  82. macro POP_RETI ; 7 cycles
  83. pop YH
  84. pop YL
  85. out SREG, YL
  86. pop YL
  87. endm
  88. macro CRC_CLEANUP_AND_CHECK
  89. ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor
  90. ; x3 is the higher crc byte, zl the lower one
  91. ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table
  92. lpm x2, Z ;[+2][+3][+4]
  93. ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table
  94. lpm ZL, Z ;[+6][+7][+8]
  95. eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value
  96. cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec)
  97. brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host
  98. cpi x2, 0xb0 ;[+10]
  99. brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host
  100. endm
  101. USB_INTR_VECTOR:
  102. ;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH
  103. push YL ;[-28] push only what is necessary to sync with edge ASAP
  104. in YL, SREG ;[-26]
  105. push YL ;[-25]
  106. push YH ;[-23]
  107. ;----------------------------------------------------------------------------
  108. ; Synchronize with sync pattern:
  109. ;----------------------------------------------------------------------------
  110. ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
  111. ;sync up with J to K edge during sync pattern -- use fastest possible loops
  112. ;The first part waits at most 1 bit long since we must be in sync pattern.
  113. ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
  114. ;waitForJ, ensure that this prerequisite is met.
  115. waitForJ:
  116. inc YL
  117. sbis USBIN, USBMINUS
  118. brne waitForJ ; just make sure we have ANY timeout
  119. waitForK:
  120. ;The following code results in a sampling window of < 1/4 bit which meets the spec.
  121. sbis USBIN, USBMINUS ;[-17]
  122. rjmp foundK ;[-16]
  123. sbis USBIN, USBMINUS
  124. rjmp foundK
  125. sbis USBIN, USBMINUS
  126. rjmp foundK
  127. sbis USBIN, USBMINUS
  128. rjmp foundK
  129. sbis USBIN, USBMINUS
  130. rjmp foundK
  131. sbis USBIN, USBMINUS
  132. rjmp foundK
  133. sbis USBIN, USBMINUS
  134. rjmp foundK
  135. sbis USBIN, USBMINUS
  136. rjmp foundK
  137. sbis USBIN, USBMINUS
  138. rjmp foundK
  139. #if USB_COUNT_SOF
  140. lds YL, usbSofCount
  141. inc YL
  142. sts usbSofCount, YL
  143. #endif /* USB_COUNT_SOF */
  144. #ifdef USB_SOF_HOOK
  145. USB_SOF_HOOK
  146. #endif
  147. rjmp sofError
  148. foundK: ;[-15]
  149. ;{3, 5} after falling D- edge, average delay: 4 cycles
  150. ;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample
  151. ;use 1 bit time for setup purposes, then sample again. Numbers in brackets
  152. ;are cycles from center of first sync (double K) bit after the instruction
  153. push x4 ;[-14]
  154. ; [---] ;[-13]
  155. lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers
  156. ; [---] ;[-11]
  157. clr YH ;[-10]
  158. subi YL, lo8(-(usbRxBuf));[-9] [rx loop init]
  159. sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init]
  160. push shift ;[-7]
  161. ; [---] ;[-6]
  162. ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop
  163. clc ;[-4] the carry has to be clear for receipt of pid bit 0
  164. sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early)
  165. rjmp haveTwoBitsK ;[-2]
  166. pop shift ;[-1] undo the push from before
  167. pop x4 ;[1]
  168. rjmp waitForK ;[3] this was not the end of sync, retry
  169. ; The entire loop from waitForK until rjmp waitForK above must not exceed two
  170. ; bit times (= 24 cycles).
  171. ;----------------------------------------------------------------------------
  172. ; push more registers and initialize values while we sample the first bits:
  173. ;----------------------------------------------------------------------------
  174. haveTwoBitsK:
  175. push x1 ;[0]
  176. push x2 ;[2]
  177. push x3 ;[4] crc high byte
  178. ldi x2, 1<<USBPLUS ;[6] [rx loop init] current line state is K state. D+=="1", D-=="0"
  179. push x5 ;[7]
  180. push cnt ;[9]
  181. ldi cnt, USB_BUFSIZE ;[11]
  182. ;--------------------------------------------------------------------------------------------------------------
  183. ; receives the pid byte
  184. ; there is no real unstuffing algorithm implemented here as a stuffing bit is impossible in the pid byte.
  185. ; That's because the last four bits of the byte are the inverted of the first four bits. If we detect a
  186. ; unstuffing condition something went wrong and abort
  187. ; shift has to be initialized to 0x80
  188. ;--------------------------------------------------------------------------------------------------------------
  189. ; pid bit 0 - used for even more register saving (we need the z pointer)
  190. in x1, USBIN ;[0] sample line state
  191. andi x1, USBMASK ;[1] filter only D+ and D- bits
  192. eor x2, x1 ;[2] generate inverted of actual bit
  193. sbrc x2, USBMINUS ;[3] if the bit is set we received a zero
  194. sec ;[4]
  195. ror shift ;[5] we perform no unstuffing check here as this is the first bit
  196. mov x2, x1 ;[6]
  197. push ZL ;[7]
  198. ;[8]
  199. push ZH ;[9]
  200. ;[10]
  201. ldi x3, 0xFE ;[11] x3 is the high order crc value
  202. bitloopPid:
  203. in x1, USBIN ;[0] sample line state
  204. andi x1, USBMASK ;[1] filter only D+ and D- bits
  205. breq nse0 ;[2] both lines are low so handle se0
  206. eor x2, x1 ;[3] generate inverted of actual bit
  207. sbrc x2, USBMINUS ;[4] set the carry if we received a zero
  208. sec ;[5]
  209. ror shift ;[6]
  210. ldi ZL, 0x54 ;[7] ZL is the low order crc value
  211. ser x4 ;[8] the is no bit stuffing check here as the pid bit can't be stuffed. if so
  212. ; some error occured. In this case the paket is discarded later on anyway.
  213. mov x2, x1 ;[9] prepare for the next cycle
  214. brcc bitloopPid ;[10] while 0s drop out of shift we get the next bit
  215. eor x4, shift ;[11] invert all bits in shift and store result in x4
  216. ;--------------------------------------------------------------------------------------------------------------
  217. ; receives data bytes and calculates the crc
  218. ; the last USBIN state has to be in x2
  219. ; this is only the first half, due to branch distanc limitations the second half of the loop is near the end
  220. ; of this asm file
  221. ;--------------------------------------------------------------------------------------------------------------
  222. rxDataStart:
  223. in x1, USBIN ;[0] sample line state (note: a se0 check is not useful due to bit dribbling)
  224. ser x5 ;[1] prepare the unstuff marker register
  225. eor x2, x1 ;[2] generates the inverted of the actual bit
  226. bst x2, USBMINUS ;[3] copy the bit from x2
  227. bld shift, 0 ;[4] and store it in shift
  228. mov x2, shift ;[5] make a copy of shift for unstuffing check
  229. andi x2, 0xF9 ;[6] mask the last six bits, if we got six zeros (which are six ones in fact)
  230. breq unstuff0 ;[7] then Z is set now and we branch to the unstuffing handler
  231. didunstuff0:
  232. subi cnt, 1 ;[8] cannot use dec because it doesn't affect the carry flag
  233. brcs nOverflow ;[9] Too many bytes received. Ignore packet
  234. st Y+, x4 ;[10] store the last received byte
  235. ;[11] st needs two cycles
  236. ; bit1
  237. in x2, USBIN ;[0] sample line state
  238. andi x1, USBMASK ;[1] check for se0 during bit 0
  239. breq nse0 ;[2]
  240. andi x2, USBMASK ;[3] check se0 during bit 1
  241. breq nse0 ;[4]
  242. eor x1, x2 ;[5]
  243. bst x1, USBMINUS ;[6]
  244. bld shift, 1 ;[7]
  245. mov x1, shift ;[8]
  246. andi x1, 0xF3 ;[9]
  247. breq unstuff1 ;[10]
  248. didunstuff1:
  249. nop ;[11]
  250. ; bit2
  251. in x1, USBIN ;[0] sample line state
  252. andi x1, USBMASK ;[1] check for se0 (as there is nothing else to do here
  253. breq nOverflow ;[2]
  254. eor x2, x1 ;[3] generates the inverted of the actual bit
  255. bst x2, USBMINUS ;[4]
  256. bld shift, 2 ;[5] store the bit
  257. mov x2, shift ;[6]
  258. andi x2, 0xE7 ;[7] if we have six zeros here (which means six 1 in the stream)
  259. breq unstuff2 ;[8] the next bit is a stuffing bit
  260. didunstuff2:
  261. nop2 ;[9]
  262. ;[10]
  263. nop ;[11]
  264. ; bit3
  265. in x2, USBIN ;[0] sample line state
  266. andi x2, USBMASK ;[1] check for se0
  267. breq nOverflow ;[2]
  268. eor x1, x2 ;[3]
  269. bst x1, USBMINUS ;[4]
  270. bld shift, 3 ;[5]
  271. mov x1, shift ;[6]
  272. andi x1, 0xCF ;[7]
  273. breq unstuff3 ;[8]
  274. didunstuff3:
  275. nop ;[9]
  276. rjmp rxDataBit4 ;[10]
  277. ;[11]
  278. ; the avr branch instructions allow an offset of +63 insturction only, so we need this
  279. ; 'local copy' of se0
  280. nse0:
  281. rjmp se0 ;[4]
  282. ;[5]
  283. ; the same same as for se0 is needed for overflow and StuffErr
  284. nOverflow:
  285. stuffErr:
  286. rjmp overflow
  287. unstuff0: ;[8] this is the branch delay of breq unstuffX
  288. andi x1, USBMASK ;[9] do an se0 check here (if the last crc byte ends with 5 one's we might end up here
  289. breq didunstuff0 ;[10] event tough the message is complete -> jump back and store the byte
  290. ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing
  291. in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
  292. andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift)
  293. eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero
  294. andi x1, USBMASK ;[3] mask the interesting bits
  295. breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong
  296. mov x1, x2 ;[5] the next bit expects the last state to be in x1
  297. rjmp didunstuff0 ;[6]
  298. ;[7] jump delay of rjmp didunstuffX
  299. unstuff1: ;[11] this is the jump delay of breq unstuffX
  300. in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
  301. ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing
  302. andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift)
  303. eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero
  304. andi x2, USBMASK ;[4] mask the interesting bits
  305. breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong
  306. mov x2, x1 ;[6] the next bit expects the last state to be in x2
  307. nop2 ;[7]
  308. ;[8]
  309. rjmp didunstuff1 ;[9]
  310. ;[10] jump delay of rjmp didunstuffX
  311. unstuff2: ;[9] this is the jump delay of breq unstuffX
  312. ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing
  313. andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift)
  314. in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
  315. eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
  316. andi x1, USBMASK ;[2] mask the interesting bits
  317. breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong
  318. mov x1, x2 ;[4] the next bit expects the last state to be in x1
  319. nop2 ;[5]
  320. ;[6]
  321. rjmp didunstuff2 ;[7]
  322. ;[8] jump delay of rjmp didunstuffX
  323. unstuff3: ;[9] this is the jump delay of breq unstuffX
  324. ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing
  325. andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift)
  326. in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
  327. eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
  328. andi x2, USBMASK ;[2] mask the interesting bits
  329. breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong
  330. mov x2, x1 ;[4] the next bit expects the last state to be in x2
  331. nop2 ;[5]
  332. ;[6]
  333. rjmp didunstuff3 ;[7]
  334. ;[8] jump delay of rjmp didunstuffX
  335. ; the include has to be here due to branch distance restirctions
  336. #define __USE_CRC__
  337. #include "asmcommon.inc"
  338. ; USB spec says:
  339. ; idle = J
  340. ; J = (D+ = 0), (D- = 1)
  341. ; K = (D+ = 1), (D- = 0)
  342. ; Spec allows 7.5 bit times from EOP to SOP for replies
  343. ; 7.5 bit times is 90 cycles. ...there is plenty of time
  344. sendNakAndReti:
  345. ldi x3, USBPID_NAK ;[-18]
  346. rjmp sendX3AndReti ;[-17]
  347. sendAckAndReti:
  348. ldi cnt, USBPID_ACK ;[-17]
  349. sendCntAndReti:
  350. mov x3, cnt ;[-16]
  351. sendX3AndReti:
  352. ldi YL, 20 ;[-15] x3==r20 address is 20
  353. ldi YH, 0 ;[-14]
  354. ldi cnt, 2 ;[-13]
  355. ; rjmp usbSendAndReti fallthrough
  356. ;usbSend:
  357. ;pointer to data in 'Y'
  358. ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
  359. ;uses: x1...x4, btcnt, shift, cnt, Y
  360. ;Numbers in brackets are time since first bit of sync pattern is sent
  361. usbSendAndReti: ; 12 cycles until SOP
  362. in x2, USBDDR ;[-12]
  363. ori x2, USBMASK ;[-11]
  364. sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
  365. in x1, USBOUT ;[-8] port mirror for tx loop
  366. out USBDDR, x2 ;[-6] <- acquire bus
  367. ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0
  368. ldi x4, USBMASK ;[-5] exor mask
  369. ldi shift, 0x80 ;[-4] sync byte is first byte sent
  370. txByteLoop:
  371. ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000
  372. txBitLoop: ; the loop sends the first 7 bits of the byte
  373. sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state
  374. eor x1, x4 ;[-1]=[11]
  375. out USBOUT, x1 ;[0]
  376. ror shift ;[1]
  377. ror x2 ;[2] transfers the last sent bit to the stuffing history
  378. didStuffN:
  379. nop ;[3]
  380. nop ;[4]
  381. cpi x2, 0xfc ;[5] if we sent six consecutive ones
  382. brcc bitstuffN ;[6]
  383. lsr bitcnt ;[7]
  384. brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount
  385. ; transmit bit 7
  386. sbrs shift, 0 ;[9]
  387. eor x1, x4 ;[10]
  388. didStuff7:
  389. ror shift ;[11]
  390. out USBOUT, x1 ;[0] transfer bit 7 to the pins
  391. ror x2 ;[1] move the bit into the stuffing history
  392. cpi x2, 0xfc ;[2]
  393. brcc bitstuff7 ;[3]
  394. ld shift, y+ ;[4] get next byte to transmit
  395. dec cnt ;[5] decrement byte counter
  396. brne txByteLoop ;[7] if we have more bytes start next one
  397. ;[8] branch delay
  398. ;make SE0:
  399. cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles]
  400. lds x2, usbNewDeviceAddr;[9]
  401. lsl x2 ;[11] we compare with left shifted address
  402. out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle
  403. subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3
  404. sbci YH, 0 ;[2]
  405. ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
  406. ;set address only after data packet was sent, not after handshake
  407. breq skipAddrAssign ;[3]
  408. sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
  409. skipAddrAssign:
  410. ;end of usbDeviceAddress transfer
  411. ldi x2, 1<<USB_INTR_PENDING_BIT;[5] int0 occurred during TX -- clear pending flag
  412. USB_STORE_PENDING(x2) ;[6]
  413. ori x1, USBIDLE ;[7]
  414. in x2, USBDDR ;[8]
  415. cbr x2, USBMASK ;[9] set both pins to input
  416. mov x3, x1 ;[10]
  417. cbr x3, USBMASK ;[11] configure no pullup on both pins
  418. ldi x4, 4 ;[12]
  419. se0Delay:
  420. dec x4 ;[13] [16] [19] [22]
  421. brne se0Delay ;[14] [17] [20] [23]
  422. out USBOUT, x1 ;[24] <-- out J (idle) -- end of SE0 (EOP signal)
  423. out USBDDR, x2 ;[25] <-- release bus now
  424. out USBOUT, x3 ;[26] <-- ensure no pull-up resistors are active
  425. rjmp doReturn
  426. bitstuffN:
  427. eor x1, x4 ;[8] generate a zero
  428. ldi x2, 0 ;[9] reset the bit stuffing history
  429. nop2 ;[10]
  430. out USBOUT, x1 ;[0] <-- send the stuffing bit
  431. rjmp didStuffN ;[1]
  432. bitstuff7:
  433. eor x1, x4 ;[5]
  434. ldi x2, 0 ;[6] reset bit stuffing history
  435. clc ;[7] fill a zero into the shift register
  436. rol shift ;[8] compensate for ror shift at branch destination
  437. rjmp didStuff7 ;[9]
  438. ;[10] jump delay
  439. ;--------------------------------------------------------------------------------------------------------------
  440. ; receives data bytes and calculates the crc
  441. ; second half of the data byte receiver loop
  442. ; most parts of the crc algorithm are here
  443. ;--------------------------------------------------------------------------------------------------------------
  444. nOverflow2:
  445. rjmp overflow
  446. rxDataBit4:
  447. in x1, USBIN ;[0] sample line state
  448. andi x1, USBMASK ;[1] check for se0
  449. breq nOverflow2 ;[2]
  450. eor x2, x1 ;[3]
  451. bst x2, USBMINUS ;[4]
  452. bld shift, 4 ;[5]
  453. mov x2, shift ;[6]
  454. andi x2, 0x9F ;[7]
  455. breq unstuff4 ;[8]
  456. didunstuff4:
  457. nop2 ;[9][10]
  458. nop ;[11]
  459. ; bit5
  460. in x2, USBIN ;[0] sample line state
  461. ldi ZH, hi8(usbCrcTableHigh);[1] use the table for the higher byte
  462. eor x1, x2 ;[2]
  463. bst x1, USBMINUS ;[3]
  464. bld shift, 5 ;[4]
  465. mov x1, shift ;[5]
  466. andi x1, 0x3F ;[6]
  467. breq unstuff5 ;[7]
  468. didunstuff5:
  469. lpm x4, Z ;[8] load the higher crc xor-byte and store it for later use
  470. ;[9] lpm needs 3 cycles
  471. ;[10]
  472. ldi ZH, hi8(usbCrcTableLow);[11] load the lower crc xor byte adress
  473. ; bit6
  474. in x1, USBIN ;[0] sample line state
  475. eor x2, x1 ;[1]
  476. bst x2, USBMINUS ;[2]
  477. bld shift, 6 ;[3]
  478. mov x2, shift ;[4]
  479. andi x2, 0x7E ;[5]
  480. breq unstuff6 ;[6]
  481. didunstuff6:
  482. lpm ZL, Z ;[7] load the lower xor crc byte
  483. ;[8] lpm needs 3 cycles
  484. ;[9]
  485. eor ZL, x3 ;[10] xor the old high crc byte with the low xor-byte
  486. mov x3, x4 ;[11] move the new high order crc value from temp to its destination
  487. ; bit7
  488. in x2, USBIN ;[0] sample line state
  489. eor x1, x2 ;[1]
  490. bst x1, USBMINUS ;[2]
  491. bld shift, 7 ;[3] now shift holds the complete but inverted data byte
  492. mov x1, shift ;[4]
  493. andi x1, 0xFC ;[5]
  494. breq unstuff7 ;[6]
  495. didunstuff7:
  496. eor x5, shift ;[7] x5 marks all bits which have not been inverted by the unstuffing subs
  497. mov x4, x5 ;[8] keep a copy of the data byte it will be stored during next bit0
  498. eor ZL, x4 ;[9] feed the actual byte into the crc algorithm
  499. rjmp rxDataStart ;[10] next byte
  500. ;[11] during the reception of the next byte this one will be fed int the crc algorithm
  501. unstuff4: ;[9] this is the jump delay of rjmp unstuffX
  502. ori shift, 0x10 ;[10] invert the last received bit to prevent furhter unstuffing
  503. andi x5, 0xEF ;[11] mark this bit as inverted (will be corrected before storing shift)
  504. in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
  505. eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
  506. andi x1, USBMASK ;[2] mask the interesting bits
  507. breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong
  508. mov x1, x2 ;[4] the next bit expects the last state to be in x1
  509. nop2 ;[5]
  510. ;[6]
  511. rjmp didunstuff4 ;[7]
  512. ;[8] jump delay of rjmp didunstuffX
  513. unstuff5: ;[8] this is the jump delay of rjmp unstuffX
  514. nop ;[9]
  515. ori shift, 0x20 ;[10] invert the last received bit to prevent furhter unstuffing
  516. andi x5, 0xDF ;[11] mark this bit as inverted (will be corrected before storing shift)
  517. in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
  518. eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
  519. andi x2, USBMASK ;[2] mask the interesting bits
  520. breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong
  521. mov x2, x1 ;[4] the next bit expects the last state to be in x2
  522. nop ;[5]
  523. rjmp didunstuff5 ;[6]
  524. ;[7] jump delay of rjmp didunstuffX
  525. unstuff6: ;[7] this is the jump delay of rjmp unstuffX
  526. nop2 ;[8]
  527. ;[9]
  528. ori shift, 0x40 ;[10] invert the last received bit to prevent furhter unstuffing
  529. andi x5, 0xBF ;[11] mark this bit as inverted (will be corrected before storing shift)
  530. in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
  531. eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
  532. andi x1, USBMASK ;[2] mask the interesting bits
  533. breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong
  534. mov x1, x2 ;[4] the next bit expects the last state to be in x1
  535. rjmp didunstuff6 ;[5]
  536. ;[6] jump delay of rjmp didunstuffX
  537. unstuff7: ;[7] this is the jump delay of rjmp unstuffX
  538. nop ;[8]
  539. nop ;[9]
  540. ori shift, 0x80 ;[10] invert the last received bit to prevent furhter unstuffing
  541. andi x5, 0x7F ;[11] mark this bit as inverted (will be corrected before storing shift)
  542. in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
  543. eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
  544. andi x2, USBMASK ;[2] mask the interesting bits
  545. breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong
  546. mov x2, x1 ;[4] the next bit expects the last state to be in x2
  547. rjmp didunstuff7 ;[5]
  548. ;[6] jump delay of rjmp didunstuff7
  549. ; local copy of the stuffErr desitnation for the second half of the receiver loop
  550. stuffErr2:
  551. rjmp stuffErr
  552. ;--------------------------------------------------------------------------------------------------------------
  553. ; The crc table follows. It has to be aligned to enable a fast loading of the needed bytes.
  554. ; There are two tables of 256 entries each, the low and the high byte table.
  555. ; Table values were generated with the following C code:
  556. /*
  557. #include <stdio.h>
  558. int main (int argc, char **argv)
  559. {
  560. int i, j;
  561. for (i=0; i<512; i++){
  562. unsigned short crc = i & 0xff;
  563. for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0);
  564. if((i & 7) == 0) printf("\n.byte ");
  565. printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff);
  566. if(i == 255) printf("\n");
  567. }
  568. return 0;
  569. }
  570. // Use the following algorithm to compute CRC values:
  571. ushort computeCrc(uchar *msg, uchar msgLen)
  572. {
  573. uchar i;
  574. ushort crc = 0xffff;
  575. for(i = 0; i < msgLen; i++)
  576. crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc);
  577. return crc;
  578. }
  579. */
  580. .balign 256
  581. usbCrcTableLow:
  582. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  583. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  584. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  585. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  586. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  587. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  588. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  589. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  590. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  591. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  592. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  593. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  594. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  595. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  596. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  597. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  598. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  599. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  600. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  601. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  602. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  603. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  604. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  605. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  606. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  607. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  608. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  609. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  610. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  611. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  612. .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
  613. .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
  614. ; .balign 256
  615. usbCrcTableHigh:
  616. .byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2
  617. .byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04
  618. .byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E
  619. .byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8
  620. .byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A
  621. .byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC
  622. .byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6
  623. .byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10
  624. .byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32
  625. .byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4
  626. .byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE
  627. .byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38
  628. .byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA
  629. .byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C
  630. .byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26
  631. .byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0
  632. .byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62
  633. .byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4
  634. .byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE
  635. .byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68
  636. .byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA
  637. .byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C
  638. .byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76
  639. .byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0
  640. .byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92
  641. .byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54
  642. .byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E
  643. .byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98
  644. .byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A
  645. .byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C
  646. .byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86
  647. .byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40