main.c 2.4 KB

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  1. #include <avr/io.h>
  2. #define F_CPU 8000000
  3. #include <util/delay.h>
  4. #include <stdlib.h>
  5. #include "uart.h"
  6. //SREG defines
  7. #define S_MOSI PB3
  8. #define S_SCK PB5
  9. #define S_LATCH PB2
  10. //DEBUG defines
  11. #define D_LED0 PB0
  12. //SRAM defines
  13. #define R_WR PB1
  14. #define R_RD PB7
  15. #define R_DATA PORTD
  16. #define R_DIR DDRD
  17. //Software UART defines
  18. // SUART_RX PB6
  19. void SPI_MasterInit(void)
  20. {
  21. /* Set MOSI and SCK output, all others input */
  22. DDRB |= ((1<<S_MOSI) | (1<<S_SCK) | (1<<S_LATCH) );
  23. /* Enable SPI, Master, set clock rate fck */
  24. SPCR = ((1<<SPE)|(1<<MSTR));
  25. }
  26. void SPI_MasterTransmit(unsigned char cData)
  27. {
  28. /* Start transmission */
  29. SPDR = cData;
  30. /* Wait for transmission complete */
  31. while(!(SPSR & (1<<SPIF)));
  32. }
  33. uint8_t SRAM_Read(uint32_t addr)
  34. {
  35. uint8_t byte;
  36. DDRD=0x00;
  37. PORTD=0x00;
  38. PORTB |= (1<<R_RD);
  39. PORTB |= (1<<R_WR);
  40. SPI_MasterTransmit((uint8_t)(addr>>8));
  41. SPI_MasterTransmit((uint8_t)(addr>>4));
  42. SPI_MasterTransmit((uint8_t)(addr>>0));
  43. PORTB |= (1<<S_LATCH);
  44. PORTB &= ~(1<<S_LATCH);
  45. PORTB &= ~(1<<R_RD);
  46. asm volatile ("nop");
  47. asm volatile ("nop");
  48. byte = PIND;
  49. PORTB |= (1<<R_RD);
  50. return byte;
  51. }
  52. void SRAM_Write(uint32_t addr, uint8_t data)
  53. {
  54. DDRD=0xff;
  55. PORTB |= (1<<R_RD);
  56. PORTB |= (1<<R_WR);
  57. SPI_MasterTransmit((uint8_t)(addr>>8));
  58. SPI_MasterTransmit((uint8_t)(addr>>4));
  59. SPI_MasterTransmit((uint8_t)(addr>>0));
  60. PORTB |= (1<<S_LATCH);
  61. PORTB &= ~(1<<S_LATCH);
  62. PORTB &= ~(1<<R_WR);
  63. PORTD=data;
  64. PORTB |= (1<<R_WR);
  65. }
  66. int main(void)
  67. {
  68. uint8_t read, buf[2], i;
  69. DDRB |= ((1<<D_LED0) | (1<<R_WR) | (1<<R_RD));
  70. PORTB |= (1<<R_RD);
  71. PORTB |= (1<<R_WR);
  72. SPI_MasterInit();
  73. uart_init();
  74. SRAM_Write(0x00000000,0x23);
  75. SRAM_Write(0x00000001, 0x42);
  76. while(1){
  77. i++;
  78. PORTB ^= ((1<<D_LED0));
  79. read = SRAM_Read(0x00000000);
  80. itoa(read,buf,16);
  81. uart_puts("dump: ");
  82. uart_puts(buf);
  83. uart_putc(0x20);
  84. read = SRAM_Read(0x00000001);
  85. itoa(read,buf,16);
  86. uart_puts(buf);
  87. uart_putc(0x20);
  88. read = SRAM_Read(0x00000002);
  89. itoa(read,buf,16);
  90. uart_puts(buf);
  91. uart_putc(0x20);
  92. read = SRAM_Read(0x00000003);
  93. itoa(read,buf,16);
  94. uart_puts(buf);
  95. uart_putc(0x20);
  96. read = SRAM_Read(0x00000004);
  97. itoa(read,buf,16);
  98. uart_puts(buf);
  99. uart_putc(0x20);
  100. if(i==10){
  101. SRAM_Write(0x00000002,0xBE);
  102. SRAM_Write(0x00000003,0xEF);
  103. }
  104. if(i==11)
  105. while(1);
  106. uart_putc(10);
  107. uart_putc(13);
  108. }
  109. return(0);
  110. }