main.c 9.6 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <avr/io.h>
  21. #include <avr/interrupt.h>
  22. #include <util/delay.h>
  23. #include <stdlib.h>
  24. #include <avr/pgmspace.h>
  25. #include <avr/eeprom.h>
  26. #include "usbdrv.h"
  27. #include "oddebug.h"
  28. #include "config.h"
  29. #include "requests.h"
  30. #include "uart.h"
  31. #include "sram.h"
  32. #include "debug.h"
  33. #include "info.h"
  34. #include "dump.h"
  35. #include "crc.h"
  36. #include "usb_bulk.h"
  37. #include "timer.h"
  38. #include "watchdog.h"
  39. #include "rle.h"
  40. #include "loader.h"
  41. #include "command.h"
  42. #include "shared_memory.h"
  43. #include "irq.h"
  44. #include "pwm.h"
  45. #include "testing.h"
  46. #include "shell.h"
  47. extern FILE uart_stdout;
  48. uint8_t debug_level = (DEBUG | DEBUG_USB | DEBUG_CRC | DEBUG_SHM );
  49. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  50. uint32_t req_addr = 0;
  51. uint32_t req_addr_end = 0;
  52. uint32_t req_size;
  53. uint8_t req_bank;
  54. uint32_t req_bank_size;
  55. uint16_t req_bank_cnt;
  56. uint8_t req_percent;
  57. uint8_t req_percent_last;
  58. uint8_t req_state = REQ_STATUS_IDLE;
  59. uint8_t rx_remaining = 0;
  60. uint8_t tx_remaining = 0;
  61. uint16_t sync_errors = 0;
  62. uint8_t tx_buffer[32];
  63. uint8_t data_buffer[4];
  64. uint32_t addr;
  65. uint16_t crc = 0;
  66. usbMsgLen_t usbFunctionSetup(uchar data[8])
  67. {
  68. usbRequest_t *rq = (void *) data;
  69. uint8_t ret_len = 0;
  70. if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  71. req_bank = 0;
  72. rx_remaining = 0;
  73. debug_P(DEBUG_USB, PSTR("USB_BULK_UPLOAD_INIT: %i %i\n"), rq->wValue.word,
  74. rq->wIndex.word);
  75. req_bank_size = (uint32_t) (1L << rq->wValue.word);
  76. req_bank_cnt = rq->wIndex.word;
  77. req_addr_end = (uint32_t) req_bank_size *req_bank_cnt;
  78. req_percent = 0;
  79. req_percent_last = 0;
  80. sync_errors = 0;
  81. debug_P(DEBUG_USB,
  82. PSTR("USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n"),
  83. req_bank_size, req_bank_cnt, req_addr_end);
  84. shared_memory_write(SHARED_MEM_TX_CMD_UPLOAD_START, 0);
  85. shared_memory_write(SHARED_MEM_TX_CMD_BANK_COUNT, req_bank_cnt);
  86. #if DO_TIMER
  87. if (req_addr == 0x000000) {
  88. timer_start();
  89. }
  90. #endif
  91. /*
  92. * -------------------------------------------------------------------------
  93. */
  94. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  95. req_state = REQ_STATUS_BULK_UPLOAD;
  96. req_addr = rq->wValue.word;
  97. req_addr = req_addr << 16;
  98. req_addr = req_addr | rq->wIndex.word;
  99. rx_remaining = rq->wLength.word;
  100. if (req_addr && req_addr % req_bank_size == 0) {
  101. #if DO_TIMER
  102. #ifdef FLT_DEBUG
  103. debug_P(DEBUG_USB,
  104. PSTR("USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n"),
  105. req_bank, req_addr, timer_stop());
  106. #else
  107. debug_P(DEBUG_USB,
  108. PSTR("USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%i\n"),
  109. req_bank, req_addr, timer_stop_int());
  110. #endif
  111. timer_start();
  112. #endif
  113. req_bank++;
  114. } else {
  115. sram_bulk_write_start(req_addr);
  116. }
  117. ret_len = USB_MAX_TRANS;
  118. /*
  119. * -------------------------------------------------------------------------
  120. */
  121. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  122. req_state = REQ_STATUS_BULK_UPLOAD;
  123. req_addr = rq->wValue.word;
  124. req_addr = req_addr << 16;
  125. req_addr = req_addr | rq->wIndex.word;
  126. rx_remaining = rq->wLength.word;
  127. req_percent = (uint32_t)( 100 * req_addr ) / req_addr_end;
  128. if (req_percent!=req_percent_last){
  129. shared_memory_write(SHARED_MEM_TX_CMD_UPLOAD_PROGESS, req_percent);
  130. }
  131. req_percent_last = req_percent;
  132. shared_memory_scratchpad_region_save_helper(req_addr);
  133. if (req_addr && (req_addr % req_bank_size) == 0) {
  134. #if DO_TIMER
  135. #ifdef FLT_DEBUG
  136. debug_P(DEBUG_USB,
  137. PSTR("USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%.4f\n"),
  138. req_bank, req_addr, timer_stop());
  139. #else
  140. debug_P(DEBUG_USB,
  141. PSTR("USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%i\n"),
  142. req_bank, req_addr, timer_stop_int());
  143. #endif
  144. timer_start();
  145. #endif
  146. req_bank++;
  147. shared_memory_write(SHARED_MEM_TX_CMD_BANK_CURRENT, req_bank);
  148. }
  149. ret_len = USB_MAX_TRANS;
  150. /*
  151. * -------------------------------------------------------------------------
  152. */
  153. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  154. if (req_state != REQ_STATUS_BULK_UPLOAD) {
  155. debug_P(DEBUG_USB,
  156. PSTR("USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n"));
  157. return 0;
  158. }
  159. debug_P(DEBUG_USB, PSTR("USB_BULK_UPLOAD_END:\n"));
  160. req_state = REQ_STATUS_IDLE;
  161. sram_bulk_write_end();
  162. shared_memory_write(SHARED_MEM_TX_CMD_UPLOAD_END, 0);
  163. ret_len = 0;
  164. /*
  165. * -------------------------------------------------------------------------
  166. */
  167. } else if (rq->bRequest == USB_CRC) {
  168. req_addr = rq->wValue.word;
  169. req_addr = req_addr << 16;
  170. req_addr = req_addr | rq->wIndex.word;
  171. debug_P(DEBUG_USB, PSTR("USB_CRC: addr=0x%08lx \n"), req_addr);
  172. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  173. ret_len = 0;
  174. /*
  175. * -------------------------------------------------------------------------
  176. */
  177. } else if (rq->bRequest == USB_MODE_SNES) {
  178. req_state = REQ_STATUS_SNES;
  179. debug_P(DEBUG_USB, PSTR("USB_MODE_SNES:\n"));
  180. ret_len = 0;
  181. pwm_stop();
  182. /*
  183. * -------------------------------------------------------------------------
  184. */
  185. } else if (rq->bRequest == USB_MODE_AVR) {
  186. req_state = REQ_STATUS_AVR;
  187. debug_P(DEBUG_USB, PSTR("USB_MODE_AVR:\n"));
  188. ret_len = 0;
  189. /*
  190. * -------------------------------------------------------------------------
  191. */
  192. } else if (rq->bRequest == USB_AVR_RESET) {
  193. debug_P(DEBUG_USB, PSTR("USB_AVR_RESET:\n"));
  194. soft_reset();
  195. ret_len = 0;
  196. /*
  197. * -------------------------------------------------------------------------
  198. */
  199. } else if (rq->bRequest == USB_CRC_ADDR) {
  200. req_state = REQ_STATUS_CRC;
  201. req_addr = rq->wValue.word;
  202. req_addr = req_addr << 16;
  203. req_addr = req_addr | rq->wIndex.word;
  204. debug_P(DEBUG_USB, PSTR("USB_CRC_ADDR: addr=0x%lx size=%i\n"), req_addr,
  205. rq->wLength.word);
  206. req_size = rq->wLength.word;
  207. req_size = req_size << 2;
  208. tx_remaining = 2;
  209. debug_P(DEBUG_USB, PSTR("USB_CRC_ADDR: addr=0x%lx size=%li\n"), req_addr,
  210. req_size);
  211. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  212. tx_buffer[0] = crc & 0xff;
  213. tx_buffer[1] = (crc >> 8) & 0xff;
  214. ret_len = 2;
  215. req_state = REQ_STATUS_IDLE;
  216. }
  217. usbMsgPtr = data_buffer;
  218. return ret_len; /* default for not implemented requests: return no data back to host */
  219. }
  220. /*
  221. * -------------------------------------------------------------------------
  222. */
  223. void globals_init(){
  224. req_addr = 0;
  225. req_addr_end = 0;
  226. req_state = REQ_STATUS_IDLE;
  227. rx_remaining = 0;
  228. tx_remaining = 0;
  229. sync_errors = 0;
  230. }
  231. int main(void)
  232. {
  233. uart_init();
  234. stdout = &uart_stdout;
  235. banner();
  236. system_init();
  237. pwm_init();
  238. shared_memory_init();
  239. snes_reset_hi();
  240. snes_reset_off();
  241. irq_init();
  242. boot_startup_rom(50);
  243. globals_init();
  244. pwm_stop();
  245. usbInit();
  246. usb_connect();
  247. while (1) {
  248. avr_bus_active();
  249. info_P(PSTR("Activate AVR bus\n"));
  250. snes_lorom();
  251. info_P(PSTR("Disable SNES WR\n"));
  252. snes_wr_disable();
  253. sei();
  254. info_P(PSTR("USB poll\n"));
  255. while (req_state != REQ_STATUS_SNES) {
  256. usbPoll();
  257. shell_run();
  258. }
  259. shared_memory_write(SHARED_MEM_TX_CMD_TERMINATE, 0);
  260. #if DO_SHM_SCRATCHPAD
  261. shared_memory_scratchpad_region_tx_restore();
  262. shared_memory_scratchpad_region_rx_restore();
  263. #endif
  264. #if DO_CRC_CHECK
  265. info_P(PSTR("-->CRC Check\n"));
  266. crc_check_bulk_memory(0x000000, req_bank_size * req_bank_cnt, req_bank_size);
  267. #endif
  268. info_P(PSTR("-->Switch TO SNES\n"));
  269. set_rom_mode();
  270. snes_wr_disable();
  271. info_P(PSTR("Disable SNES WR\n"));
  272. snes_bus_active();
  273. info_P(PSTR("Activate SNES bus\n"));
  274. irq_stop();
  275. send_reset();
  276. info_P(PSTR("Poll USB\n"));
  277. while ((req_state != REQ_STATUS_AVR)) {
  278. usbPoll();
  279. shell_run();
  280. }
  281. info_P(PSTR("-->Switch TO AVR\n"));
  282. shared_memory_init();
  283. irq_init();
  284. boot_startup_rom(500);
  285. }
  286. return 0;
  287. }