dmafifo.asm 22 KB

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  1. /*
  2. todo:
  3. add a special case for uploading 2 vertical rows of the tilemap.
  4. doing this with 32 dma transfers of 4 bytes each is incredibly slow.
  5. better make a tight loop using vram acces 32byte increment that uploads the tilemap rows manually.
  6. guesstimate is that the dma fifo routine can transfer 130 bytes per scanline on average.
  7. normal transfers shouldnt be smaller than 128 bytes or so, otherwise the time needed to set up a dma transfer throws
  8. our timing off way too much.
  9. scanlines 200-261 can be used for uploads.
  10. maximum transfer length should be 2048 bytes.
  11. nmi eats about 8 scanlines.
  12. current guesstimate is 6784/$1a80 bytes per frame.
  13. this routine is used to dma transfer data to vram in bulk.
  14. other routines can queue writes into a fifo buffer and these then get transferred to vram during nmi or forced blank.
  15. ;this only works for transfers from a-bus to vram to keep things simple
  16. ;a transfer length of 0 marks the end of the buffer
  17. ;WARNING!
  18. ;this routine MUST have finished till nmi starts or it will produce glitched transfers! no longer true. was caused by some status stuff not being pushed to stack during irq entry.
  19. ;overscan is enabled to lengthen the time available for dma'ing stuff from the dma fifo to vram
  20. ;glitched transfer risk can be minimized by writing the dma count value last!!
  21. number of scanlines: irq trigger: nmi trigger normal: irq trigger overscan:
  22. ntsc: 261 200 225 240
  23. pal: 311 200 225 240
  24. maximum number of entries: 128
  25. dma queue format:
  26. offset: length: function:
  27. 00 2 transfer length
  28. 02 2 vram target
  29. 04 2 a-bus source offset
  30. 06 1 a-bus source bank
  31. areas needed:
  32. DmaFifoBuffer ds $1c0
  33. variables needed:
  34. DmaFifoPointer dw ;relative pointer to current free entry in buffer
  35. DmaFifoSourcePointerLo dw
  36. DmaFifoSourcePointerBa db
  37. fixed variable needed:
  38. .define DmaFifoEntryLength 7
  39. routine features:
  40. InitDmaFifo:
  41. -clear dma fifo buffer
  42. ProcessDmaFifo:
  43. -setup initial dma regs
  44. -process the list until a length of 0 is encountered
  45. -reset DmaFifoPointer to 0
  46. transfer types:
  47. 00=void, no transfer
  48. 01=normal dma from a-bus adress to vram
  49. 02=special manual transfer mode to upload vertical tilemap rows
  50. 03=special transfer,16x16 sprite
  51. 04=special transfer, 32x32 sprite
  52. 05=special transfer, 64x64 sprite
  53. 06=special vwf transfer, converts 2bpp tiles to 4bpp. transfer length is number of tiles, not bytelength
  54. how to write entries into table, m/x=16bit, new:
  55. ;transfer type 1, normal a-bus to vram dma:
  56. ldx.b DmaFifoPointer
  57. lda #1 ;transfer type
  58. sta.l DmaFifoEntryType,x
  59. sta.l DmaFifoEntryCount,x ;length 4305
  60. sta.l DmaFifoEntryTarget,x ;vram target 2116
  61. sta.l DmaFifoEntrySrcLo,x ;source 4302
  62. sta.l DmaFifoEntrySrcHi,x ;source 4303
  63. sta.l DmaFifoEntrySrcBank,x ;source 4304
  64. txa ;update fifo entry pointer
  65. clc
  66. adc.w #DmaFifoEntryLength
  67. sta.b DmaFifoPointer
  68. ;transfer type 2, upload vertical tilemap row from wram bank 7e to vram
  69. ldx.b DmaFifoPointer
  70. lda #2 ;transfer type
  71. sta.l DmaFifoEntryType,x
  72. sta.l DmaFifoEntryTarget,x ;vram target 2116
  73. sta.l DmaFifoEntryCount,x ;number of lines to upload (one line has 32 entries), maximum 32 lines
  74. sta.l DmaFifoEntrySrcLo,x ;source 4302
  75. sta.l DmaFifoEntrySrcHi,x ;source 4303
  76. ;sta.l DmaFifoEntrySrcBank,x ;source 4304
  77. */
  78. ;waits for all dma transfers to be done and then one frame
  79. WaitDmaTransfersDone:
  80. php
  81. rep #$31
  82. WaitDmaTransfersDoneLoop:
  83. lda.b DmaFifoPointer
  84. bne WaitDmaTransfersDoneLoop
  85. plp
  86. rts
  87. ;waits 2 frames to be sure all settings have been written to the video regs
  88. WaitFrame:
  89. ; rts
  90. php
  91. rep #$31
  92. WaitFrameIncDone:
  93. lda.b FrameCounterLo
  94. cmp.b FrameCounterLo
  95. beq WaitFrameIncDone
  96. /*
  97. WaitFrameIncDone1:
  98. lda.b FrameCounterLo
  99. cmp.b FrameCounterLo
  100. beq WaitFrameIncDone1
  101. */
  102. plp
  103. rts
  104. InitDmaFifo:
  105. php
  106. rep #$31
  107. lda.w #0 ;clear word: $0000
  108. sta.l (DmaFifoPointer+$7e0000) ;reset fifo pointer
  109. sta.l (DmaFifoPointerIrq+$7e0000) ;reset fifo pointer
  110. ldy.w #DmaFifoEntryLength*256
  111. ldx.w #DmaFifoBuffer&$ffff
  112. jsr ClearWRAM
  113. ; sta.l (DmaFifoOverhang+$7e0000)
  114. ; sta.l (DmaFifoTotalBytesTransferred+$7e0000)
  115. plp
  116. rts
  117. ProcessDmaFifoTypeLUT:
  118. .dw ProcessDmaFifoTypeVoid
  119. .dw ProcessDmaFifoTypeNormalDma
  120. .dw ProcessDmaFifoTypeVTilemapRow
  121. .dw ProcessDmaFifoType16x16Sprite
  122. .dw ProcessDmaFifoType32x32Sprite
  123. .dw ProcessDmaFifoType64x64Sprite
  124. .dw ProcessDmaFifoTypeVwf2bppTo4bpp
  125. .dw UploadBg1Tilemap
  126. .dw UploadBg2Tilemap
  127. .dw UploadBg3Tilemap
  128. .dw NMIUploadPal
  129. .dw NMIUploadOAM
  130. .dw ProcessDmaFifoTypeVoid
  131. .dw ProcessDmaFifoTypeVoid
  132. .dw ProcessDmaFifoTypeVoid
  133. .dw ProcessDmaFifoTypeVoid
  134. .dw ProcessDmaFifoTypeVoid
  135. ProcessDmaFifoTypeVoid:
  136. ; sec
  137. rts
  138. ProcessDmaFifoTypeVwf2bppTo4bpp:
  139. ;setup some dma regs that always stay the same on all transfers:
  140. lda.w #$1801 ;Set the DMA mode (word, normal increment)
  141. sta.w $4300
  142. lda.b [DmaFifoSourcePointerLo],y
  143. and.w #$7f ;128 tiles max(vram vwf buffer size)
  144. beq ProcessDmaFifoTypeVwf2bppTo4bppAbort
  145. sta.b TempBufferIrq ;number of tiles to transfer, counter
  146. /*
  147. asl a ;multiply by 16(length of one 2bpp tile)
  148. asl a
  149. asl a
  150. asl a
  151. clc
  152. adc.b DmaFifoTotalBytesTransferred
  153. sta.b DmaFifoTotalBytesTransferred
  154. */
  155. lda.w #16 ;transfer length, one tile
  156. sta.w $4305
  157. iny
  158. iny
  159. lda.b [DmaFifoSourcePointerLo],y
  160. sta.b TempBufferIrq+2 ;vram target
  161. sta.w $2116
  162. iny
  163. iny
  164. lda.b [DmaFifoSourcePointerLo],y
  165. sta.b TempBufferIrq+4 ;dma source
  166. sta.w $4302
  167. iny
  168. lda.b [DmaFifoSourcePointerLo],y ;dma source, high byte and bank
  169. iny
  170. iny
  171. ; iny
  172. sta.w $4303
  173. ProcessDmaFifoTypeVwf2bppTo4bppLoop:
  174. sep #$20
  175. lda #$80
  176. sta.w $2115 ;set VRAM transfer mode to word-access, increment by 1
  177. lda.b #$01
  178. sta.w $420b
  179. dec.b TempBufferIrq ;counter
  180. beq ProcessDmaFifoTypeVwf2bppTo4bppAbort ;all tiles uploaded?
  181. rep #$31
  182. lda.b TempBufferIrq+2
  183. ; clc
  184. adc.w #32/2 ;add one 4bpp tile to vram target
  185. sta.b TempBufferIrq+2
  186. sta.w $2116
  187. lda.b TempBufferIrq+4
  188. clc
  189. adc.w #16 ;add one 2bpp tile to wram source
  190. sta.b TempBufferIrq+4
  191. sta.w $4302
  192. lda.w #16 ;transfer length, one line
  193. sta.w $4305
  194. bra ProcessDmaFifoTypeVwf2bppTo4bppLoop
  195. ProcessDmaFifoTypeVwf2bppTo4bppAbort:
  196. rts
  197. ProcessDmaFifoType16x16Sprite:
  198. lda.w #$1801 ;Set the DMA mode (word, normal increment)
  199. sta.w $4300
  200. lda.w #64 ;transfer length, one line
  201. sta.w $4305
  202. /*
  203. lda.w #64*8
  204. clc
  205. adc.b DmaFifoTotalBytesTransferred
  206. sta.b DmaFifoTotalBytesTransferred
  207. */
  208. iny
  209. iny
  210. lda.b [DmaFifoSourcePointerLo],y
  211. sta.b TempBufferIrq ;vram target
  212. sta.w $2116
  213. iny
  214. iny
  215. lda.b [DmaFifoSourcePointerLo],y
  216. sta.b TempBufferIrq+2 ;dma source
  217. sta.w $4302
  218. iny
  219. lda.b [DmaFifoSourcePointerLo],y ;dma source, high byte and bank
  220. iny
  221. iny
  222. ; iny
  223. sta.w $4303
  224. sep #$20
  225. lda #$80
  226. sta.w $2115 ;set VRAM transfer mode to word-access, increment by 1
  227. lda.b #$01
  228. sta.w $420b
  229. rep #$31
  230. lda.b TempBufferIrq
  231. ; clc
  232. adc.w #32*16/2 ;add one 16tile-line to vram target
  233. sta.b TempBufferIrq
  234. sta.w $2116
  235. lda.b TempBufferIrq+2
  236. clc
  237. adc.w #64 ;add one tileline in source
  238. sta.b TempBufferIrq+2
  239. sta.w $4302
  240. lda.w #64 ;transfer length, one line
  241. sta.w $4305
  242. sep #$20
  243. lda.b #$01
  244. sta.w $420b
  245. rts
  246. ProcessDmaFifoType32x32Sprite:
  247. lda.w #$1801 ;Set the DMA mode (word, normal increment)
  248. sta.w $4300
  249. lda.w #128 ;transfer length, one line
  250. sta.w $4305
  251. /*
  252. lda.w #128*8
  253. clc
  254. adc.b DmaFifoTotalBytesTransferred
  255. sta.b DmaFifoTotalBytesTransferred
  256. */
  257. iny
  258. iny
  259. lda.b [DmaFifoSourcePointerLo],y
  260. sta.b TempBufferIrq ;vram target
  261. sta.w $2116
  262. iny
  263. iny
  264. lda.b [DmaFifoSourcePointerLo],y
  265. sta.b TempBufferIrq+2 ;dma source
  266. sta.w $4302
  267. iny
  268. lda.b [DmaFifoSourcePointerLo],y ;dma source, high byte and bank
  269. iny
  270. iny
  271. ; iny
  272. sta.w $4303
  273. sep #$20
  274. lda #$80
  275. sta.w $2115 ;set VRAM transfer mode to word-access, increment by 1
  276. lda.b #$01
  277. sta.w $420b
  278. rep #$31
  279. lda.b TempBufferIrq
  280. ; clc
  281. adc.w #32*16/2 ;add one 16tile-line to vram target
  282. sta.b TempBufferIrq
  283. sta.w $2116
  284. lda.b TempBufferIrq+2
  285. clc
  286. adc.w #128 ;add one tileline in source
  287. sta.b TempBufferIrq+2
  288. sta.w $4302
  289. lda.w #128 ;transfer length, one line
  290. sta.w $4305
  291. sep #$20
  292. lda.b #$01
  293. sta.w $420b
  294. rep #$31
  295. lda.b TempBufferIrq
  296. ; clc
  297. adc.w #32*16/2 ;add one 16tile-line to vram target
  298. sta.b TempBufferIrq
  299. sta.w $2116
  300. lda.b TempBufferIrq+2
  301. clc
  302. adc.w #128 ;add one tileline in source
  303. sta.b TempBufferIrq+2
  304. sta.w $4302
  305. lda.w #128 ;transfer length, one line
  306. sta.w $4305
  307. sep #$20
  308. lda.b #$01
  309. sta.w $420b
  310. rep #$31
  311. lda.b TempBufferIrq
  312. ; clc
  313. adc.w #32*16/2 ;add one 16tile-line to vram target
  314. sta.b TempBufferIrq
  315. sta.w $2116
  316. lda.b TempBufferIrq+2
  317. clc
  318. adc.w #128 ;add one tileline in source
  319. sta.b TempBufferIrq+2
  320. sta.w $4302
  321. lda.w #128 ;transfer length, one line
  322. sta.w $4305
  323. sep #$20
  324. lda.b #$01
  325. sta.w $420b
  326. rts
  327. ;takes 19 lines for 2048 bytes. a single 2048 byte transfer takes 12 lines, so this could be sped up a bit still
  328. ProcessDmaFifoType64x64Sprite:
  329. lda.w #$1801 ;Set the DMA mode (word, normal increment)
  330. sta.w $4300
  331. ; lda.b [DmaFifoSourcePointerLo],y
  332. ; beq ProcessDmaFifoTypeNormalDmaAbort
  333. lda.w #256 ;transfer length, one line
  334. sta.w $4305
  335. /*
  336. lda.w #256*8
  337. clc
  338. adc.b DmaFifoTotalBytesTransferred
  339. sta.b DmaFifoTotalBytesTransferred
  340. */
  341. iny
  342. iny
  343. lda.b [DmaFifoSourcePointerLo],y
  344. sta.b TempBufferIrq ;vram target
  345. sta.w $2116
  346. iny
  347. iny
  348. lda.b [DmaFifoSourcePointerLo],y
  349. sta.b TempBufferIrq+2 ;dma source
  350. sta.w $4302
  351. iny
  352. lda.b [DmaFifoSourcePointerLo],y ;dma source, high byte and bank
  353. iny
  354. iny
  355. ; iny
  356. sta.w $4303
  357. sep #$20
  358. lda #$80
  359. sta.w $2115 ;set VRAM transfer mode to word-access, increment by 1
  360. lda.b #$01
  361. sta.w $420b
  362. rep #$31
  363. lda.b TempBufferIrq
  364. ; clc
  365. adc.w #32*16/2 ;add one 16tile-line to vram target
  366. sta.b TempBufferIrq
  367. sta.w $2116
  368. lda.b TempBufferIrq+2
  369. clc
  370. adc.w #256 ;add one tileline in source
  371. sta.b TempBufferIrq+2
  372. sta.w $4302
  373. lda.w #256 ;transfer length, one line
  374. sta.w $4305
  375. sep #$20
  376. lda.b #$01
  377. sta.w $420b
  378. rep #$31
  379. lda.b TempBufferIrq
  380. ; clc
  381. adc.w #32*16/2 ;add one 16tile-line to vram target
  382. sta.b TempBufferIrq
  383. sta.w $2116
  384. lda.b TempBufferIrq+2
  385. clc
  386. adc.w #256 ;add one tileline in source
  387. sta.b TempBufferIrq+2
  388. sta.w $4302
  389. lda.w #256 ;transfer length, one line
  390. sta.w $4305
  391. sep #$20
  392. lda.b #$01
  393. sta.w $420b
  394. rep #$31
  395. lda.b TempBufferIrq
  396. ; clc
  397. adc.w #32*16/2 ;add one 16tile-line to vram target
  398. sta.b TempBufferIrq
  399. sta.w $2116
  400. lda.b TempBufferIrq+2
  401. clc
  402. adc.w #256 ;add one tileline in source
  403. sta.b TempBufferIrq+2
  404. sta.w $4302
  405. lda.w #256 ;transfer length, one line
  406. sta.w $4305
  407. sep #$20
  408. lda.b #$01
  409. sta.w $420b
  410. rep #$31
  411. lda.b TempBufferIrq
  412. ; clc
  413. adc.w #32*16/2 ;add one 16tile-line to vram target
  414. sta.b TempBufferIrq
  415. sta.w $2116
  416. lda.b TempBufferIrq+2
  417. clc
  418. adc.w #256 ;add one tileline in source
  419. sta.b TempBufferIrq+2
  420. sta.w $4302
  421. lda.w #256 ;transfer length, one line
  422. sta.w $4305
  423. sep #$20
  424. lda.b #$01
  425. sta.w $420b
  426. rep #$31
  427. lda.b TempBufferIrq
  428. ; clc
  429. adc.w #32*16/2 ;add one 16tile-line to vram target
  430. sta.b TempBufferIrq
  431. sta.w $2116
  432. lda.b TempBufferIrq+2
  433. clc
  434. adc.w #256 ;add one tileline in source
  435. sta.b TempBufferIrq+2
  436. sta.w $4302
  437. lda.w #256 ;transfer length, one line
  438. sta.w $4305
  439. sep #$20
  440. lda.b #$01
  441. sta.w $420b
  442. rep #$31
  443. lda.b TempBufferIrq
  444. ; clc
  445. adc.w #32*16/2 ;add one 16tile-line to vram target
  446. sta.b TempBufferIrq
  447. sta.w $2116
  448. lda.b TempBufferIrq+2
  449. clc
  450. adc.w #256 ;add one tileline in source
  451. sta.b TempBufferIrq+2
  452. sta.w $4302
  453. lda.w #256 ;transfer length, one line
  454. sta.w $4305
  455. sep #$20
  456. lda.b #$01
  457. sta.w $420b
  458. rep #$31
  459. lda.b TempBufferIrq
  460. ; clc
  461. adc.w #32*16/2 ;add one 16tile-line to vram target
  462. sta.b TempBufferIrq
  463. sta.w $2116
  464. lda.b TempBufferIrq+2
  465. clc
  466. adc.w #256 ;add one tileline in source
  467. sta.b TempBufferIrq+2
  468. sta.w $4302
  469. lda.w #256 ;transfer length, one line
  470. sta.w $4305
  471. sep #$20
  472. lda.b #$01
  473. sta.w $420b
  474. rep #$31 ;clear carry, dont abort processing fifo list
  475. rts
  476. ProcessDmaFifoTypeNormalDma:
  477. lda.w #$1801 ;Set the DMA mode (word, normal increment)
  478. sta.w $4300
  479. lda.b [DmaFifoSourcePointerLo],y
  480. beq ProcessDmaFifoTypeNormalDmaAbort
  481. sta.w $4305
  482. /*
  483. cmp.w #DmaFifoMinTransferSize ;check if transfer is lower than 64 and load 64 for counter if it is. otherwise, these transfers screw up our calculation
  484. bcs ProcessDmaFifoTypeNormalDmaBigEnough
  485. lda.w #DmaFifoMinTransferSize ;load minimum length
  486. ProcessDmaFifoTypeNormalDmaBigEnough:
  487. clc
  488. adc.b DmaFifoTotalBytesTransferred
  489. sta.b DmaFifoTotalBytesTransferred
  490. */
  491. iny
  492. iny
  493. lda.b [DmaFifoSourcePointerLo],y
  494. sta.w $2116
  495. iny
  496. iny
  497. lda.b [DmaFifoSourcePointerLo],y
  498. sta.w $4302
  499. iny
  500. lda.b [DmaFifoSourcePointerLo],y
  501. iny
  502. iny
  503. ; iny
  504. sta.w $4303
  505. ; lda #$18 ;Set the destination register (VRAM gate)
  506. ; sta $4301
  507. sep #$20
  508. lda #$80
  509. sta.w $2115 ;set VRAM transfer mode to word-access, increment by 1
  510. lda.b #$01
  511. sta.w $420b
  512. rep #$31 ;clear carry, dont abort processing fifo list
  513. rts
  514. ProcessDmaFifoTypeNormalDmaAbort: ;abort and go to next entry if a transfer length of 0 is encountered
  515. iny
  516. iny
  517. iny
  518. iny
  519. iny
  520. iny
  521. iny
  522. rts
  523. ProcessDmaFifoTypeVTilemapRow:
  524. lda.w #$1801 ;Set the DMA mode (word, normal increment)
  525. sta.w $4300
  526. sep #$20
  527. lda #%10000001
  528. sta $2115 ;set VRAM transfer mode to word-access, increment by 64
  529. rep #$31
  530. ; lda.b [DmaFifoSourcePointerLo],y ;get number of lines to transfer
  531. ; and #31 ;maximum number of lines:32
  532. ; tax
  533. iny
  534. iny
  535. lda.b [DmaFifoSourcePointerLo],y
  536. sta.w $2116 ;store vram target
  537. iny
  538. iny
  539. lda.b [DmaFifoSourcePointerLo],y
  540. tax ;source offset in bank $7e
  541. iny
  542. iny
  543. iny
  544. lda.l $7e0000,x
  545. sta $2118 ;write data to vram
  546. lda.l $7e0000+$40,x
  547. sta $2118 ;write data to vram
  548. lda.l $7e0000+$80,x
  549. sta $2118 ;write data to vram
  550. lda.l $7e0000+$c0,x
  551. sta $2118 ;write data to vram
  552. lda.l $7e0000+$100,x
  553. sta $2118 ;write data to vram
  554. lda.l $7e0000+$140,x
  555. sta $2118 ;write data to vram
  556. lda.l $7e0000+$180,x
  557. sta $2118 ;write data to vram
  558. lda.l $7e0000+$1c0,x
  559. sta $2118 ;write data to vram
  560. lda.l $7e0000+$200,x
  561. sta $2118 ;write data to vram
  562. lda.l $7e0000+$240,x
  563. sta $2118 ;write data to vram
  564. lda.l $7e0000+$280,x
  565. sta $2118 ;write data to vram
  566. lda.l $7e0000+$2c0,x
  567. sta $2118 ;write data to vram
  568. lda.l $7e0000+$300,x
  569. sta $2118 ;write data to vram
  570. lda.l $7e0000+$340,x
  571. sta $2118 ;write data to vram
  572. lda.l $7e0000+$380,x
  573. sta $2118 ;write data to vram
  574. lda.l $7e0000+$3c0,x
  575. sta $2118 ;write data to vram
  576. lda.l $7e0000+$400,x
  577. sta $2118 ;write data to vram
  578. lda.l $7e0000+$440,x
  579. sta $2118 ;write data to vram
  580. lda.l $7e0000+$480,x
  581. sta $2118 ;write data to vram
  582. lda.l $7e0000+$4c0,x
  583. sta $2118 ;write data to vram
  584. lda.l $7e0000+$500,x
  585. sta $2118 ;write data to vram
  586. lda.l $7e0000+$540,x
  587. sta $2118 ;write data to vram
  588. lda.l $7e0000+$580,x
  589. sta $2118 ;write data to vram
  590. lda.l $7e0000+$5c0,x
  591. sta $2118 ;write data to vram
  592. lda.l $7e0000+$600,x
  593. sta $2118 ;write data to vram
  594. lda.l $7e0000+$640,x
  595. sta $2118 ;write data to vram
  596. lda.l $7e0000+$680,x
  597. sta $2118 ;write data to vram
  598. lda.l $7e0000+$6c0,x
  599. sta $2118 ;write data to vram
  600. lda.l $7e0000+$700,x
  601. sta $2118 ;write data to vram
  602. lda.l $7e0000+$740,x
  603. sta $2118 ;write data to vram
  604. lda.l $7e0000+$780,x
  605. sta $2118 ;write data to vram
  606. lda.l $7e0000+$7c0,x
  607. sta $2118 ;write data to vram
  608. rts
  609. /*
  610. pointer
  611. pointerirq
  612. -if pointer=0, exit immediately
  613. -get pointerirq and do transfer its pointing to, then increase pointerirq by one entry
  614. -if pointerirq is equal or bigger than pointer, clear pointer and pointerirq
  615. */
  616. ProcessDmaFifo:
  617. php
  618. sep #$20
  619. ;setup pointer to fifo buffer
  620. lda.b #$7e
  621. sta.b DmaFifoSourcePointerBa
  622. rep #$31
  623. lda.w #DmaFifoBuffer&$ffff
  624. sta.b DmaFifoSourcePointerLo
  625. ; ldy.b DmaFifoOverhang ;normally 0. if the list wasnt finished last frame, we finish it now
  626. ldy.b DmaFifoPointer
  627. beq ProcessDmaFifoExit
  628. ProcessDmaFifoLoop:
  629. ldy.b DmaFifoPointerIrq
  630. lda.b [DmaFifoSourcePointerLo],y ;get transfer type
  631. phy ;save for later
  632. and.w #$000f ;16 different transfer types only
  633. asl a
  634. tax
  635. iny ;prepare pointer for dma upload routine
  636. php
  637. jsr (ProcessDmaFifoTypeLUT,x)
  638. plp
  639. ply
  640. lda.w #0
  641. sta.b [DmaFifoSourcePointerLo],y ;clear this transfer type to be on the safe side
  642. iny
  643. iny
  644. sta.b [DmaFifoSourcePointerLo],y
  645. iny
  646. iny
  647. sta.b [DmaFifoSourcePointerLo],y
  648. iny
  649. iny
  650. sta.b [DmaFifoSourcePointerLo],y
  651. iny
  652. iny
  653. tya
  654. sta.b DmaFifoPointerIrq ;update process pointer
  655. cmp.b DmaFifoPointer
  656. bcc ProcessDmaFifoNotDone ;done when process pointer is bigger than queue pointer
  657. stz.b DmaFifoPointerIrq ;clear both pointers
  658. stz.b DmaFifoPointer
  659. bra ProcessDmaFifoExit
  660. ProcessDmaFifoNotDone:
  661. ; cpy.w #DmaFifoEntryLength*128 ;check if whole list was processed
  662. ;check if scanline 238 has been passed:
  663. sep #$20
  664. lda.b #$80
  665. sta.w $4201 ;reset latch
  666. nop
  667. nop
  668. nop
  669. nop
  670. lda.w $2137 ;latch current scanline
  671. lda.w $213f ;reset $213d lo/hi byte counter
  672. lda.w $213d ;get low byte
  673. xba
  674. lda.w $213d ;get high byte
  675. xba
  676. rep #$31
  677. and.w #$1ff
  678. cmp.w #199
  679. bcc ProcessDmaFifoExit ;exit if lower than scanline 200 (wrapped around)
  680. cmp.w #239
  681. bcc ProcessDmaFifoLoop ;exit if bigger than scanline 237 (nearly at end of irq timeframe)
  682. ProcessDmaFifoExit:
  683. ; jsr InitDmaFifo
  684. ; sty.b DmaFifoPointer ;should always be zero
  685. plp
  686. rts
  687. /*
  688. UploadBg1TilemapFifo:
  689. php
  690. rep #$31
  691. ldx.b DmaFifoPointer
  692. lda #1 ;transfer type normal dma
  693. sta.l DmaFifoEntryType,x
  694. lda.b VramBg1Tilemap
  695. sta.l DmaFifoEntryTarget,x ;vram target 2116
  696. lda.w #Bg1MapBuffer & $ffff
  697. sta.l DmaFifoEntrySrcLo,x ;source 4302
  698. lda.w #$800
  699. sta.l DmaFifoEntryCount,x ;length 4305
  700. sep #$20
  701. lda.b #(Bg1MapBuffer >> 16)
  702. sta.l DmaFifoEntrySrcBank,x ;source 4304
  703. rep #$31
  704. txa ;update fifo entry pointer
  705. adc.w #DmaFifoEntryLength
  706. sta.b DmaFifoPointer
  707. plp
  708. rts
  709. */
  710. NMIUploadPal:
  711. ;transfer palette buffer to cgram
  712. sep #$20
  713. stz.w $2121 ;upload colour-palette buffer at $7e:0e00 to cg-ram every frame
  714. ldx #PaletteBuffer&$ffff ;start at color 0
  715. stx.w $4302 ;Store the data offset into DMA source offset
  716. ldx #$0200
  717. stx.w $4305 ;Store the size of the data block
  718. lda.b #$7e
  719. sta.w $4304 ;Store the data bank holding the tile data
  720. lda.b #$00 ;Set the DMA mode (byte, normal increment)
  721. sta.w $4300
  722. lda.b #$22 ;Set the destination register ( $2122: CG-RAM Write )
  723. sta.w $4301
  724. lda.b #$01 ;Initiate the DMA transfer
  725. sta.w $420B
  726. ; stz.b NMIPaletteUploadFlag
  727. rts
  728. NMIUploadOAM:
  729. ;transfer sprite buffer to oamram
  730. sep #$20
  731. stz.w $2102 ;upload to oam adress 0
  732. stz.w $2103
  733. ldx.w #OamBuffer&$ffff ;start at color 0
  734. stx.w $4302 ;Store the data offset into DMA source offset
  735. ldx.w #$0220
  736. stx.w $4305 ;Store the size of the data block
  737. lda.b #$7e
  738. sta.w $4304 ;Store the data bank holding the tile data
  739. lda.b #$00 ;Set the DMA mode (byte, normal increment)
  740. sta.w $4300
  741. lda.b #$04 ;Set the destination register ( $2122: CG-RAM Write )
  742. sta.w $4301
  743. lda.b #$01 ;Initiate the DMA transfer
  744. sta.w $420B
  745. ; stz.b NMIOamUploadFlag ;clear upload flag
  746. rts
  747. BgTilemapSizeLUT:
  748. .dw $800
  749. .dw $1000
  750. .dw $1000
  751. .dw $2000
  752. ;NMIUploadBg1:
  753. UploadBg1Tilemap:
  754. rep #$31
  755. lda.b BG1TilemapVram
  756. and.w #%11 ;get tilemap size
  757. asl a
  758. tax
  759. lda.l (BgTilemapSizeLUT+BaseAdress),x
  760. sta.w $4305 ;Store the size of the data block
  761. ;transfer bg1 tilemap to vram if needed:
  762. sep #$20
  763. ldx.b VramBg1Tilemap
  764. stx.w $2116 ;vram adress $0000
  765. ldx.w #Bg1MapBuffer & $ffff
  766. stx.w $4302 ;Store the data offset into DMA source offset
  767. lda.b #(Bg1MapBuffer >> 16)
  768. sta.w $4304 ;Store the data bank of the source data
  769. lda.b #$80
  770. sta.w $2115 ;set VRAM transfer mode to word-access, increment by 1
  771. lda.b #$01 ;Set the DMA mode (word, normal increment)
  772. sta.w $4300
  773. lda.b #$18 ;Set the destination register (VRAM gate)
  774. sta.w $4301
  775. lda.b #$01 ;Initiate the DMA transfer
  776. sta.w $420B
  777. ; stz.b NMIBg1UploadFlag
  778. rts
  779. ;NMIUploadBg2:
  780. UploadBg2Tilemap:
  781. ;transfer bg2 tilemap to vram if needed:
  782. rep #$31
  783. lda.b BG2TilemapVram
  784. and.w #%11 ;get tilemap size
  785. asl a
  786. tax
  787. lda.l (BgTilemapSizeLUT+BaseAdress),x
  788. sta.w $4305 ;Store the size of the data block
  789. sep #$20
  790. ldx.b VramBg2Tilemap
  791. stx.w $2116 ;vram adress $0000
  792. ldx.w #Bg2MapBuffer & $ffff
  793. stx.w $4302 ;Store the data offset into DMA source offset
  794. ; ldx.w #$800
  795. ; stx.w $4305 ;Store the size of the data block
  796. lda.b #(Bg2MapBuffer >> 16)
  797. sta.w $4304 ;Store the data bank of the source data
  798. lda.b #$80
  799. sta.w $2115 ;set VRAM transfer mode to word-access, increment by 1
  800. lda.b #$01 ;Set the DMA mode (word, normal increment)
  801. sta.w $4300
  802. lda.b #$18 ;Set the destination register (VRAM gate)
  803. sta.w $4301
  804. lda.b #$01 ;Initiate the DMA transfer
  805. sta.w $420B
  806. ; stz.b NMIBg2UploadFlag
  807. rts
  808. UploadBg3Tilemap:
  809. ;transfer bg3 tilemap to vram if needed:
  810. rep #$31
  811. lda.b BG3TilemapVram
  812. and.w #%11 ;get tilemap size
  813. asl a
  814. tax
  815. lda.l (BgTilemapSizeLUT+BaseAdress),x
  816. sta.w $4305 ;Store the size of the data block
  817. sep #$20
  818. ldx.b VramBg3Tilemap
  819. stx.w $2116 ;vram adress $0000
  820. ldx.w #Bg3MapBuffer & $ffff
  821. stx.w $4302 ;Store the data offset into DMA source offset
  822. ; ldx.w #$800
  823. ; stx.w $4305 ;Store the size of the data block
  824. lda.b #(Bg3MapBuffer >> 16)
  825. sta.w $4304 ;Store the data bank of the source data
  826. lda.b #$80
  827. sta.w $2115 ;set VRAM transfer mode to word-access, increment by 1
  828. lda.b #$01 ;Set the DMA mode (word, normal increment)
  829. sta.w $4300
  830. lda.b #$18 ;Set the destination register (VRAM gate)
  831. sta.w $4301
  832. lda.b #$01 ;Initiate the DMA transfer
  833. sta.w $420B
  834. ; stz.b NMIBg3UploadFlag
  835. rts