main.c 16 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <avr/io.h>
  21. #include <avr/interrupt.h> /* for sei() */
  22. #include <util/delay.h> /* for _delay_ms() */
  23. #include <stdlib.h>
  24. #include <avr/pgmspace.h> /* required by usbdrv.h */
  25. #include <avr/eeprom.h>
  26. #include "usbdrv.h"
  27. #include "oddebug.h" /* This is also an example for using debug
  28. * macros */
  29. #include "config.h"
  30. #include "requests.h" /* The custom request numbers we use */
  31. #include "uart.h"
  32. #include "sram.h"
  33. #include "debug.h"
  34. #include "info.h"
  35. #include "dump.h"
  36. #include "crc.h"
  37. #include "usb_bulk.h"
  38. #include "timer.h"
  39. #include "watchdog.h"
  40. #include "huffman-decode.h"
  41. #include "rle.h"
  42. #include "loader.h"
  43. #include "shared_memory.h"
  44. extern const char _rom[] PROGMEM;
  45. extern FILE uart_stdout;
  46. uint8_t debug_level = ( DEBUG | DEBUG_USB | DEBUG_CRC );
  47. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  48. uint32_t req_addr = 0;
  49. uint32_t req_addr_end = 0;
  50. uint32_t req_size;
  51. uint8_t req_bank;
  52. uint32_t req_bank_size;
  53. uint16_t req_bank_cnt;
  54. uint8_t req_state = REQ_STATUS_IDLE;
  55. uint8_t rx_remaining = 0;
  56. uint8_t tx_remaining = 0;
  57. uint16_t sync_errors = 0;
  58. uint8_t tx_buffer[32];
  59. uint8_t data_buffer[4];
  60. uint32_t addr;
  61. uint16_t crc = 0;
  62. usbMsgLen_t usbFunctionSetup(uchar data[8])
  63. {
  64. usbRequest_t *rq = (void *) data;
  65. uint8_t ret_len = 0;
  66. /*
  67. * -------------------------------------------------------------------------
  68. */
  69. if (rq->bRequest == USB_UPLOAD_INIT) {
  70. if (req_state != REQ_STATUS_IDLE){
  71. debug(DEBUG_USB,"USB_UPLOAD_INIT: ERROR state is not REQ_STATUS_IDLE\n");
  72. return 0;
  73. }
  74. req_bank = 0;
  75. rx_remaining = 0;
  76. req_bank_size = (uint32_t)1 << rq->wValue.word;
  77. sync_errors = 0;
  78. crc = 0;
  79. shared_memory_put(SHARED_MEM_CMD_UPLOAD_START,0);
  80. debug(DEBUG_USB,"USB_UPLOAD_INIT: bank_size=0x%08lx\n", req_bank_size);
  81. /*
  82. * -------------------------------------------------------------------------
  83. */
  84. } else if (rq->bRequest == USB_UPLOAD_ADDR) {
  85. req_state = REQ_STATUS_UPLOAD;
  86. req_addr = rq->wValue.word;
  87. req_addr = req_addr << 16;
  88. req_addr = req_addr | rq->wIndex.word;
  89. if (rx_remaining) {
  90. sync_errors++;
  91. debug
  92. (DEBUG_USB,"USB_UPLOAD_ADDR: Out of sync addr=0x%lx remain=%i packet=%i sync_error=%i\n",
  93. req_addr, rx_remaining, rq->wLength.word, sync_errors);
  94. ret_len = 0;
  95. }
  96. rx_remaining = rq->wLength.word;
  97. ret_len = USB_MAX_TRANS;
  98. if (req_addr && (req_addr % 0x1000) == 0) {
  99. debug(DEBUG_USB,"USB_UPLOAD_ADDR: bank=0x%02x addr=0x%08lx crc=%04x\n",
  100. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  101. }
  102. if (req_addr && req_addr % req_bank_size == 0) {
  103. debug(DEBUG_USB,"USB_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx\n",
  104. req_bank, req_addr);
  105. req_bank++;
  106. //shared_memory_put(SHARED_MEM_CMD_UPLOAD_PROGESS,req_bank);
  107. }
  108. ret_len = USB_MAX_TRANS;
  109. /*
  110. * -------------------------------------------------------------------------
  111. */
  112. } else if (rq->bRequest == USB_DOWNLOAD_INIT) {
  113. debug(DEBUG_USB,"USB_DOWNLOAD_INIT\n");
  114. /*
  115. * -------------------------------------------------------------------------
  116. */
  117. } else if (rq->bRequest == USB_DOWNLOAD_ADDR) {
  118. debug(DEBUG_USB,"USB_DOWNLOAD_ADDR\n");
  119. /*
  120. * -------------------------------------------------------------------------
  121. */
  122. } else if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  123. req_bank = 0;
  124. rx_remaining = 0;
  125. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: %i %i\n",rq->wValue.word, rq->wIndex.word);
  126. req_bank_size = (uint32_t)(1L << rq->wValue.word);
  127. req_bank_cnt = rq->wIndex.word;
  128. req_addr_end = (uint32_t)req_bank_size * req_bank_cnt;
  129. sync_errors = 0;
  130. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n",
  131. req_bank_size, req_bank_cnt, req_addr_end);
  132. shared_memory_put(SHARED_MEM_CMD_UPLOAD_START,0);
  133. if (req_addr == 0x000000){
  134. timer_start();
  135. }
  136. /*
  137. * -------------------------------------------------------------------------
  138. */
  139. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  140. req_state = REQ_STATUS_BULK_UPLOAD;
  141. req_addr = rq->wValue.word;
  142. req_addr = req_addr << 16;
  143. req_addr = req_addr | rq->wIndex.word;
  144. rx_remaining = rq->wLength.word;
  145. if (req_addr && req_addr % req_bank_size == 0) {
  146. #ifdef FLT_DEBUG
  147. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  148. req_bank, req_addr,timer_stop());
  149. #else
  150. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%i\n",
  151. req_bank, req_addr,timer_stop_int());
  152. #endif
  153. req_bank++;
  154. shared_memory_put(SHARED_MEM_CMD_UPLOAD_PROGESS,req_bank);
  155. sram_bulk_write_start(req_addr);
  156. timer_start();
  157. } else {
  158. sram_bulk_write_start(req_addr);
  159. }
  160. ret_len = USB_MAX_TRANS;
  161. /*
  162. * -------------------------------------------------------------------------
  163. */
  164. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  165. req_state = REQ_STATUS_BULK_UPLOAD;
  166. req_addr = rq->wValue.word;
  167. req_addr = req_addr << 16;
  168. req_addr = req_addr | rq->wIndex.word;
  169. rx_remaining = rq->wLength.word;
  170. #if 0
  171. if (req_addr && (req_addr % 0x1000) == 0) {
  172. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: bank=0x%02x addr=0x%08lx crc=%04x\n",
  173. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  174. }
  175. sram_bulk_write_start(req_addr);
  176. #endif
  177. if (req_addr && ( req_addr % req_bank_size) == 0) {
  178. #ifdef FLT_DEBUG
  179. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  180. req_bank, req_addr,timer_stop());
  181. #else
  182. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%i\n",
  183. req_bank, req_addr,timer_stop_int());
  184. #endif
  185. req_bank++;
  186. timer_start();
  187. shared_memory_put(SHARED_MEM_CMD_UPLOAD_PROGESS,req_bank);
  188. sram_bulk_write_start(req_addr);
  189. }
  190. ret_len = USB_MAX_TRANS;
  191. /*
  192. * -------------------------------------------------------------------------
  193. */
  194. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  195. if (req_state != REQ_STATUS_BULK_UPLOAD){
  196. debug(DEBUG_USB,"USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n");
  197. return 0;
  198. }
  199. debug(DEBUG_USB,"USB_BULK_UPLOAD_END:\n");
  200. req_state = REQ_STATUS_IDLE;
  201. sram_bulk_write_end();
  202. shared_memory_put(SHARED_MEM_CMD_UPLOAD_END,0);
  203. ret_len = 0;
  204. /*
  205. * -------------------------------------------------------------------------
  206. */
  207. } else if (rq->bRequest == USB_CRC) {
  208. req_addr = rq->wValue.word;
  209. req_addr = req_addr << 16;
  210. req_addr = req_addr | rq->wIndex.word;
  211. debug(DEBUG_USB,"USB_CRC: addr=0x%08lx \n", req_addr);
  212. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  213. ret_len = 0;
  214. /*
  215. * -------------------------------------------------------------------------
  216. */
  217. } else if (rq->bRequest == USB_MODE_SNES) {
  218. req_state = REQ_STATUS_SNES;
  219. debug(DEBUG_USB,"USB_MODE_SNES:\n");
  220. ret_len = 0;
  221. /*
  222. * -------------------------------------------------------------------------
  223. */
  224. } else if (rq->bRequest == USB_MODE_AVR) {
  225. req_state = REQ_STATUS_AVR;
  226. debug(DEBUG_USB,"USB_MODE_AVR:\n");
  227. ret_len = 0;
  228. /*
  229. * -------------------------------------------------------------------------
  230. */
  231. } else if (rq->bRequest == USB_AVR_RESET) {
  232. debug(DEBUG_USB,"USB_AVR_RESET:\n");
  233. soft_reset();
  234. ret_len = 0;
  235. /*
  236. * -------------------------------------------------------------------------
  237. */
  238. } else if (rq->bRequest == USB_CRC_ADDR) {
  239. req_state = REQ_STATUS_CRC;
  240. req_addr = rq->wValue.word;
  241. req_addr = req_addr << 16;
  242. req_addr = req_addr | rq->wIndex.word;
  243. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%i\n", req_addr,
  244. rq->wLength.word);
  245. req_size = rq->wLength.word;
  246. req_size = req_size << 2;
  247. tx_remaining = 2;
  248. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%li\n", req_addr, req_size);
  249. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  250. tx_buffer[0] = crc & 0xff;
  251. tx_buffer[1] = (crc >> 8) & 0xff;
  252. ret_len = 2;
  253. req_state = REQ_STATUS_IDLE;
  254. }
  255. usbMsgPtr = data_buffer;
  256. return ret_len; /* default for not implemented requests: return
  257. * no data back to host */
  258. }
  259. /*
  260. * -------------------------------------------------------------------------
  261. */
  262. void test_read_write(){
  263. uint8_t i;
  264. uint32_t addr;
  265. avr_bus_active();
  266. addr = 0x000000;
  267. i = 1;
  268. while (addr++ <= 0x0000ff){
  269. sram_write(addr,i++);
  270. }
  271. addr = 0x000000;
  272. while (addr++ <= 0x0000ff){
  273. info("read addr=0x%08lx %x\n",addr,sram_read(addr));
  274. }
  275. }
  276. void test_bulk_read_write(){
  277. uint8_t i;
  278. uint32_t addr;
  279. avr_bus_active();
  280. addr = 0x000000;
  281. i = 0;
  282. sram_bulk_write_start(addr);
  283. while (addr++ <= 0x8000){
  284. sram_bulk_write(i++);
  285. sram_bulk_write_next();
  286. }
  287. sram_bulk_write_end();
  288. addr = 0x000000;
  289. sram_bulk_read_start(addr);
  290. while (addr <= 0x8000){
  291. info("addr=0x%08lx %x\n",addr,sram_bulk_read());
  292. sram_bulk_read_next();
  293. addr++;
  294. }
  295. sram_bulk_read_end();
  296. }
  297. void test_non_zero_memory(uint32_t bottom_addr,uint32_t top_addr)
  298. {
  299. uint32_t addr = 0;
  300. uint8_t c;
  301. sram_bulk_read_start(bottom_addr);
  302. for (addr = bottom_addr; addr < top_addr; addr++) {
  303. c = sram_bulk_read();
  304. if (c!=0xff)
  305. info("addr=0x%08lx c=0x%x\n",addr,c);
  306. sram_bulk_read_next();
  307. }
  308. sram_bulk_read_end();
  309. }
  310. void test_crc(){
  311. info("test_crc: clear\n");
  312. avr_bus_active();
  313. sram_bulk_set(0x000000,0x10000,0xff);
  314. info("test_crc: crc\n");
  315. crc_check_bulk_memory(0x000000,0x10000,0x8000);
  316. info("test_crc: check\n");
  317. test_non_zero_memory(0x000000,0x10000);
  318. }
  319. uint16_t read_byte_pgm(uint16_t addr){
  320. return pgm_read_byte((PGM_VOID_P)addr);
  321. }
  322. uint16_t read_byte_ee(uint16_t addr){
  323. return eeprom_read_byte((uint8_t*)addr);
  324. }
  325. void decompress(PGM_VOID_P addr, uint16_t(*fp)(uint16_t)){
  326. uint16_t c;
  327. uint32_t i = 0;
  328. huffman_dec_ctx_t ctx;
  329. huffman_dec_init(&ctx, fp);
  330. huffman_dec_set_addr(&ctx, (uint16_t)addr);
  331. while(1){
  332. i++;
  333. c=huffman_dec_byte(&ctx);
  334. if (i%1024==0)
  335. info(".");
  336. if(c>0xff){
  337. return;
  338. }
  339. c&=0xff;
  340. sram_bulk_write(c);
  341. }
  342. }
  343. void decompress_huffman(void){
  344. info("Decompress Rom %p to 0x000000\n",(void*)_rom);
  345. sram_bulk_write_start(0x000000);
  346. decompress(&_rom,read_byte_pgm);
  347. sram_bulk_write_end();
  348. info("Done\n");
  349. }
  350. void send_reset(){
  351. info("Reset Snes\n");
  352. snes_reset_on();
  353. snes_reset_lo();
  354. _delay_ms(2);
  355. snes_reset_hi();
  356. snes_reset_off();
  357. }
  358. void send_irq(){
  359. snes_irq_on();
  360. snes_irq_lo();
  361. _delay_us(20);
  362. snes_irq_hi();
  363. snes_irq_off();
  364. }
  365. void set_rom_mode(){
  366. if (req_bank_size == 0x8000){
  367. snes_lorom();
  368. info("Set Snes lowrom \n");
  369. } else {
  370. snes_hirom();
  371. info("Set Snes hirom \n");
  372. }
  373. }
  374. void usb_connect(){
  375. uint8_t i = 0;
  376. info("USB init\n");
  377. usbDeviceDisconnect(); /* enforce re-enumeration, do this while */
  378. cli();
  379. info("USB disconnect\n");
  380. i = 10;
  381. while (--i) { /* fake USB disconnect for > 250 ms */
  382. led_on();
  383. _delay_ms(35);
  384. led_off();
  385. _delay_ms(65);
  386. }
  387. led_on();
  388. usbDeviceConnect();
  389. info("USB connect\n");
  390. }
  391. void boot_startup_rom(){
  392. uint8_t i = 0;
  393. info("Activate AVR bus\n");
  394. avr_bus_active();
  395. info("IRQ off\n");
  396. snes_irq_lo();
  397. snes_irq_off();
  398. snes_lorom();
  399. info("Set Snes lowrom \n");
  400. /*
  401. info("Set Snes hirom\n");
  402. snes_hirom();
  403. info("Disable snes WR\n");
  404. snes_wr_disable();
  405. info("IRQ off\n");
  406. snes_irq_lo();
  407. snes_irq_off();
  408. */
  409. rle_decode(&_rom, ROM_SIZE, 0x000000);
  410. dump_memory(0x10000 - 0x100, 0x10000);
  411. snes_reset_hi();
  412. snes_reset_off();
  413. snes_irq_lo();
  414. snes_irq_off();
  415. info("IRQ off\n");
  416. snes_hirom();
  417. snes_wr_disable();
  418. info("Disable snes WR\n");
  419. snes_bus_active();
  420. info("Activate Snes bus\n");
  421. _delay_ms(100);
  422. info("Reset Snes\n");
  423. send_reset();
  424. _delay_ms(100);
  425. #if 0
  426. i = 20;
  427. info("Wait");
  428. while (--i){
  429. _delay_ms(500);
  430. info(".");
  431. }
  432. info("\n");
  433. #endif
  434. }
  435. int main(void)
  436. {
  437. uint8_t i;
  438. uint16_t irq_count = 0;
  439. uart_init();
  440. stdout = &uart_stdout;
  441. info("Sytem start\n");
  442. system_init();
  443. #if 0
  444. test_read_write();
  445. test_bulk_read_write();
  446. test_crc();
  447. while(1);
  448. #endif
  449. info("Boot startup rom\n");
  450. boot_startup_rom();
  451. usbInit();
  452. usb_connect();
  453. while (1){
  454. avr_bus_active();
  455. info("Activate AVR bus\n");
  456. info("IRQ off\n");
  457. snes_irq_lo();
  458. snes_irq_off();
  459. info("Set Snes lowrom\n");
  460. snes_lorom();
  461. info("Disable snes WR\n");
  462. snes_wr_disable();
  463. sei();
  464. info("USB poll\n");
  465. while (req_state != REQ_STATUS_SNES){
  466. usbPoll();
  467. }
  468. shared_memory_put(SHARED_MEM_CMD_TERMINATE,0);
  469. info("USB poll done\n");
  470. snes_reset_hi();
  471. snes_reset_off();
  472. snes_irq_lo();
  473. snes_irq_off();
  474. info("IRQ off\n");
  475. set_rom_mode();
  476. snes_wr_disable();
  477. info("Disable snes WR\n");
  478. snes_bus_active();
  479. info("Activate Snes bus\n");
  480. _delay_ms(100);
  481. info("Reset Snes\n");
  482. send_reset();
  483. info("Poll\n");
  484. while (req_state != REQ_STATUS_AVR){
  485. usbPoll();
  486. #ifdef DO_IRQ
  487. i = 10;
  488. while (--i) {
  489. _delay_ms(100);
  490. }
  491. info("Send IRQ %i\n",++irq_count);
  492. send_irq();
  493. #endif
  494. #ifdef DO_BUS_STEALING
  495. avr_bus_active();
  496. sram_bulk_read_start(0x003000);
  497. c = sram_bulk_read();
  498. i = 5;
  499. while (--i) {
  500. _delay_ms(500);
  501. info("Wait to switch to snes mode %i\n", i);
  502. }
  503. if (req_bank_size == 0x8000){
  504. snes_lorom();
  505. info("Set Snes lowrom \n");
  506. } else {
  507. snes_hirom();
  508. info("Set Snes hirom \n");
  509. }
  510. snes_wr_disable();
  511. info("Disable snes WR\n");
  512. snes_bus_active();
  513. info("Activate Snes bus\n");
  514. info("Read 0x3000=%c\n",c);
  515. #endif
  516. }
  517. }
  518. return 0;
  519. }