main.c 7.2 KB

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  1. #include <avr/io.h>
  2. #include <util/delay.h>
  3. #include <stdlib.h>
  4. #include "uart.h"
  5. #include "mmc.h"
  6. #include "fat.h"
  7. // Debug
  8. #define debug(x, fmt) printf("%s:%u: %s=" fmt, __FILE__, __LINE__, #x, x)
  9. extern FILE uart_stdout;
  10. //SREG defines
  11. #define S_MOSI PB5
  12. #define S_MISO PB6
  13. #define S_SCK PB7
  14. #define S_LATCH PB4
  15. //DEBUG defines
  16. #define D_LED0 PD6
  17. //SRAM defines
  18. #define R_WR PB1
  19. #define R_RD PB0
  20. #define RAM_PORT PORTA
  21. #define RAM_DIR DDRA
  22. #define RAM_REG PINA
  23. #define CTRL_PORT PORTB
  24. #define CTR_DIR DDRB
  25. #define LATCH_PORT PORTB
  26. #define LATCH_DIR DDRB
  27. #define SPI_PORT PORTB
  28. #define SPI_DIR DDRB
  29. #define LED_PORT PORTD
  30. #define LED_DIR DDRD
  31. //#define FILENAME "sprite.raw" //ok
  32. //#define FILENAME "ascii.smc" //ok
  33. //#define FILENAME "rom.smc" //ok
  34. //#define FILENAME "supert.smc"
  35. //#define FILENAME "vortex.smc"
  36. //#define FILENAME "mrdo.smc"
  37. //#define FILENAME "spacei.smc"
  38. //#define FILENAME "bank01.smc" //ok
  39. //#define FILENAME "bank02.smc" //ok
  40. //#define FILENAME "bank03.smc" //ok
  41. //#define FILENAME "bank04.smc" //ok
  42. //#define FILENAME "bank05.smc" //ok
  43. //#define FILENAME "bank06.smc" //ok
  44. //#define FILENAME "bank07.smc" //ok
  45. //#define FILENAME "banklo.smc" //ok
  46. //#define FILENAME "bankhi.smc" //ok
  47. #define FILENAME "vram2.smc" //ok
  48. #define DUMPNAME "dump256.smc"
  49. #define BUFFER_SIZE 512
  50. #define BLOCKS 512
  51. #define MEMSIZE 0x80000
  52. uint8_t read_buffer[BUFFER_SIZE];
  53. void dump_packet(uint32_t addr,uint32_t len,uint8_t *packet){
  54. uint16_t i,j;
  55. uint16_t sum = 0;
  56. uint8_t clear=0;
  57. for (i=0;i<len;i+=16) {
  58. sum = 0;
  59. for (j=0;j<16;j++) {
  60. sum +=packet[i+j];
  61. }
  62. if (!sum){
  63. clear=1;
  64. continue;
  65. }
  66. if (clear){
  67. printf("*\n");
  68. clear = 0;
  69. }
  70. printf("%08lx:", addr + i);
  71. for (j=0;j<16;j++) {
  72. printf(" %02x", packet[i+j]);
  73. }
  74. printf(" |");
  75. for (j=0;j<16;j++) {
  76. if (packet[i+j]>=33 && packet[i+j]<=126 )
  77. printf("%c", packet[i+j]);
  78. else
  79. printf(".");
  80. }
  81. printf("|\n");
  82. }
  83. }
  84. void spi_init(void)
  85. {
  86. /* Set MOSI and SCK output, all others input */
  87. SPI_DIR |= ((1<<S_MOSI) | (1<<S_SCK) | (1<<S_LATCH));
  88. SPI_DIR &= ~(1<<S_MISO);
  89. SPI_PORT |= (1<<S_MISO);
  90. /* Enable SPI, Master*/
  91. SPCR = ((1<<SPE) | (1<<MSTR));
  92. }
  93. void spi_master_transmit(unsigned char cData)
  94. {
  95. /* Start transmission */
  96. SPDR = cData;
  97. /* Wait for transmission complete */
  98. while(!(SPSR & (1<<SPIF)));
  99. }
  100. void sram_set_addr(uint32_t addr)
  101. {
  102. spi_master_transmit((uint8_t)(addr>>16));
  103. spi_master_transmit((uint8_t)(addr>>8));
  104. spi_master_transmit((uint8_t)(addr>>0));
  105. LATCH_PORT |= (1<<S_LATCH);
  106. LATCH_PORT &= ~(1<<S_LATCH);
  107. }
  108. uint8_t sram_read(uint32_t addr)
  109. {
  110. uint8_t byte;
  111. RAM_DIR = 0x00;
  112. RAM_PORT = 0xff;
  113. CTRL_PORT |= (1<<R_RD);
  114. CTRL_PORT |= (1<<R_WR);
  115. spi_master_transmit((uint8_t)(addr>>16));
  116. spi_master_transmit((uint8_t)(addr>>8));
  117. spi_master_transmit((uint8_t)(addr>>0));
  118. LATCH_PORT |= (1<<S_LATCH);
  119. LATCH_PORT &= ~(1<<S_LATCH);
  120. CTRL_PORT &= ~(1<<R_RD);
  121. asm volatile ("nop");
  122. asm volatile ("nop");
  123. asm volatile ("nop");
  124. asm volatile ("nop");
  125. asm volatile ("nop");
  126. asm volatile ("nop");
  127. asm volatile ("nop");
  128. asm volatile ("nop");
  129. byte = RAM_REG;
  130. CTRL_PORT |= (1<<R_RD);
  131. RAM_DIR =0x00;
  132. RAM_PORT =0x00;
  133. return byte;
  134. }
  135. void sram_write(uint32_t addr, uint8_t data)
  136. {
  137. RAM_DIR = 0xff;
  138. CTRL_PORT |= (1<<R_RD);
  139. CTRL_PORT |= (1<<R_WR);
  140. spi_master_transmit((uint8_t)(addr>>16));
  141. spi_master_transmit((uint8_t)(addr>>8));
  142. spi_master_transmit((uint8_t)(addr>>0));
  143. LATCH_PORT |= (1<<S_LATCH);
  144. LATCH_PORT &= ~(1<<S_LATCH);
  145. CTRL_PORT &= ~(1<<R_WR);
  146. RAM_PORT = data;
  147. CTRL_PORT |= (1<<R_WR);
  148. RAM_DIR = 0x00;
  149. RAM_PORT = 0x00;
  150. }
  151. void sram_init(void){
  152. RAM_DIR = 0x00;
  153. RAM_PORT = 0x00;
  154. CTR_DIR |= ((1<<R_WR) | (1<<R_RD));
  155. CTRL_PORT |= (1<<R_RD);
  156. CTRL_PORT |= (1<<R_WR);
  157. LED_PORT |= (1<<D_LED0);
  158. }
  159. void sram_snes_mode(void){
  160. CTRL_PORT |= (1<<R_WR);
  161. CTRL_PORT &= ~(1<<R_RD);
  162. }
  163. void sram_clear(uint32_t addr, uint32_t len){
  164. uint32_t i;
  165. for (i=addr; i<(addr + len);i++ ){
  166. if (0==i%0xfff)
  167. printf("sram_clear %lx\n\r",i);
  168. sram_write(i, 0x00);
  169. }
  170. }
  171. void sram_copy(uint32_t addr,uint8_t *src, uint32_t len){
  172. uint32_t i;
  173. uint8_t *ptr = src;
  174. for (i=addr; i<(addr + len);i++ )
  175. sram_write(i, *ptr++);
  176. }
  177. void sram_read_buffer(uint32_t addr,uint8_t *dst, uint32_t len){
  178. uint32_t i;
  179. uint8_t *ptr = dst;
  180. for (i=addr; i<(addr + len);i++ ){
  181. *ptr = sram_read(i);
  182. ptr++;
  183. }
  184. }
  185. uint8_t sram_check(uint8_t *buffer, uint32_t len){
  186. for (uint16_t cnt=0; cnt<len; cnt++)
  187. if (buffer[cnt])
  188. return 1;
  189. return 0;
  190. }
  191. int main(void)
  192. {
  193. uint16_t fat_cluster = 0;
  194. uint8_t fat_attrib = 0;
  195. uint32_t fat_size = 0;
  196. uint32_t rom_addr = 0;
  197. uint32_t skip_block = 0;
  198. uint8_t bank_cnt = 0;
  199. uart_init();
  200. stdout = &uart_stdout;
  201. sram_init();
  202. printf("SRAM Init\n");
  203. spi_init();
  204. printf("SPI Init\n");
  205. #if 0
  206. sram_clear(0x000000, 0x80000);
  207. printf("sram_clear\n");
  208. #endif
  209. //printf("read 0x0f0f\n");
  210. //sram_read(0x0f0f);
  211. //printf("write 0x0f0f\n");
  212. //sram_write(0x0f0f,0xaa);
  213. #if 0
  214. rom_addr = 0x4aaaa;
  215. printf("write %lx\n",rom_addr);
  216. sram_set_addr(rom_addr);
  217. while(1);
  218. #endif
  219. while ( mmc_init() !=0) {
  220. printf("No sdcard...\n");
  221. }
  222. printf("MMC Init done\n");
  223. fat_init(read_buffer);
  224. printf("FAT Init done.\n");
  225. rom_addr = 0x000000;
  226. printf("Look for %s\n",FILENAME);
  227. if (fat_search_file((uint8_t*)FILENAME,
  228. &fat_cluster,
  229. &fat_size,
  230. &fat_attrib,
  231. read_buffer) == 1) {
  232. for (uint16_t block_cnt=0; block_cnt<BLOCKS; block_cnt++) {
  233. fat_read_file (fat_cluster,read_buffer,block_cnt);
  234. if (block_cnt && block_cnt % 64 == 0){
  235. printf("Write Ram Bank: 0x%x Addr: 0x%lx Skipped: %li\n",bank_cnt,rom_addr,skip_block);
  236. bank_cnt++;
  237. skip_block=0;
  238. }
  239. //if (sram_check(read_buffer,512))
  240. sram_copy(rom_addr,read_buffer,512);
  241. //else
  242. // skip_block +=1;
  243. rom_addr += 512;
  244. }
  245. printf("Write Ram Bank: 0x%x Addr: 0x%lx Skipped: %li\n",bank_cnt,rom_addr,skip_block);
  246. printf("Done\n");
  247. }
  248. printf("Dump Headern\r");
  249. rom_addr = 0x8000-512;
  250. sram_read_buffer(rom_addr,read_buffer,512);
  251. dump_packet(rom_addr,512,read_buffer);
  252. #if 0
  253. printf("Dump Memory\n\r");
  254. rom_addr = 0x000000;
  255. for (uint16_t block_cnt=0; block_cnt < 64; block_cnt++) {
  256. sram_read_buffer(rom_addr,read_buffer,512);
  257. dump_packet(rom_addr,512,read_buffer);
  258. rom_addr += 512;
  259. }
  260. printf("\nDone 0x%lx\n",rom_addr);
  261. #endif
  262. #if 0
  263. printf("Look for %s\n",DUMPNAME);
  264. fat_cluster = 0;
  265. fat_attrib = 0;
  266. fat_size = 0;
  267. if (fat_search_file((uint8_t*)DUMPNAME,
  268. &fat_cluster,
  269. &fat_size,
  270. &fat_attrib,
  271. read_buffer) == 1) {
  272. printf("Found %s\n",DUMPNAME);
  273. rom_addr = 0x000000;
  274. bank_cnt =0;
  275. for (uint16_t block_cnt=0; block_cnt<BLOCKS; block_cnt++) {
  276. printf("Write 1");
  277. sram_read_buffer(rom_addr,read_buffer,512);
  278. printf("Write 2");
  279. fat_write_file (fat_cluster,read_buffer,block_cnt);
  280. if (block_cnt % 64 == 0){
  281. bank_cnt++;
  282. }
  283. printf("Write File Bank: 0x%x Addr: 0x%lx Skipped: %li\n",bank_cnt,rom_addr,skip_block);
  284. rom_addr += 512;
  285. }
  286. printf("Done 0x%lx Skipped %li\n",rom_addr,skip_block);
  287. }
  288. #endif
  289. sram_snes_mode();
  290. printf("\nEnter Snes mode\n");
  291. while(1);
  292. return 0 ;
  293. }