main.c 16 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <avr/io.h>
  21. #include <avr/interrupt.h> /* for sei() */
  22. #include <util/delay.h> /* for _delay_ms() */
  23. #include <stdlib.h>
  24. #include <avr/pgmspace.h> /* required by usbdrv.h */
  25. #include <avr/eeprom.h>
  26. #include "usbdrv.h"
  27. #include "oddebug.h" /* This is also an example for using debug macros */
  28. #include "config.h"
  29. #include "requests.h" /* The custom request numbers we use */
  30. #include "uart.h"
  31. #include "sram.h"
  32. #include "debug.h"
  33. #include "info.h"
  34. #include "dump.h"
  35. #include "crc.h"
  36. #include "usb_bulk.h"
  37. #include "timer.h"
  38. #include "watchdog.h"
  39. #include "rle.h"
  40. #include "loader.h"
  41. #include "shared_memory.h"
  42. extern const char _rom[] PROGMEM;
  43. extern FILE uart_stdout;
  44. uint8_t debug_level = (DEBUG | DEBUG_USB | DEBUG_CRC);
  45. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  46. uint32_t req_addr = 0;
  47. uint32_t req_addr_end = 0;
  48. uint32_t req_size;
  49. uint8_t req_bank;
  50. uint32_t req_bank_size;
  51. uint16_t req_bank_cnt;
  52. uint8_t req_state = REQ_STATUS_IDLE;
  53. uint8_t rx_remaining = 0;
  54. uint8_t tx_remaining = 0;
  55. uint16_t sync_errors = 0;
  56. uint8_t tx_buffer[32];
  57. uint8_t data_buffer[4];
  58. uint32_t addr;
  59. uint16_t crc = 0;
  60. usbMsgLen_t usbFunctionSetup(uchar data[8])
  61. {
  62. usbRequest_t *rq = (void *) data;
  63. uint8_t ret_len = 0;
  64. /*
  65. * -------------------------------------------------------------------------
  66. */
  67. if (rq->bRequest == USB_UPLOAD_INIT) {
  68. if (req_state != REQ_STATUS_IDLE) {
  69. debug(DEBUG_USB,
  70. "USB_UPLOAD_INIT: ERROR state is not REQ_STATUS_IDLE\n");
  71. return 0;
  72. }
  73. req_bank = 0;
  74. rx_remaining = 0;
  75. req_bank_size = (uint32_t) 1 << rq->wValue.word;
  76. sync_errors = 0;
  77. crc = 0;
  78. debug(DEBUG_USB, "USB_UPLOAD_INIT: bank_size=0x%08lx\n", req_bank_size);
  79. /*
  80. * -------------------------------------------------------------------------
  81. */
  82. } else if (rq->bRequest == USB_UPLOAD_ADDR) {
  83. req_state = REQ_STATUS_UPLOAD;
  84. req_addr = rq->wValue.word;
  85. req_addr = req_addr << 16;
  86. req_addr = req_addr | rq->wIndex.word;
  87. if (rx_remaining) {
  88. sync_errors++;
  89. debug
  90. (DEBUG_USB,
  91. "USB_UPLOAD_ADDR: Out of sync addr=0x%lx remain=%i packet=%i sync_error=%i\n",
  92. req_addr, rx_remaining, rq->wLength.word, sync_errors);
  93. ret_len = 0;
  94. }
  95. rx_remaining = rq->wLength.word;
  96. ret_len = USB_MAX_TRANS;
  97. if (req_addr && (req_addr % 0x1000) == 0) {
  98. debug(DEBUG_USB,
  99. "USB_UPLOAD_ADDR: bank=0x%02x addr=0x%08lx crc=%04x\n",
  100. req_bank, req_addr, crc_check_bulk_memory(req_addr - 0x1000,
  101. req_addr,
  102. req_bank_size));
  103. }
  104. if (req_addr && req_addr % req_bank_size == 0) {
  105. debug(DEBUG_USB, "USB_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx\n",
  106. req_bank, req_addr);
  107. req_bank++;
  108. // shared_memory_put(SHARED_MEM_CMD_UPLOAD_PROGESS,req_bank);
  109. }
  110. ret_len = USB_MAX_TRANS;
  111. /*
  112. * -------------------------------------------------------------------------
  113. */
  114. } else if (rq->bRequest == USB_DOWNLOAD_INIT) {
  115. debug(DEBUG_USB, "USB_DOWNLOAD_INIT\n");
  116. /*
  117. * -------------------------------------------------------------------------
  118. */
  119. } else if (rq->bRequest == USB_DOWNLOAD_ADDR) {
  120. debug(DEBUG_USB, "USB_DOWNLOAD_ADDR\n");
  121. /*
  122. * -------------------------------------------------------------------------
  123. */
  124. } else if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  125. req_bank = 0;
  126. rx_remaining = 0;
  127. debug(DEBUG_USB, "USB_BULK_UPLOAD_INIT: %i %i\n", rq->wValue.word,
  128. rq->wIndex.word);
  129. req_bank_size = (uint32_t) (1L << rq->wValue.word);
  130. req_bank_cnt = rq->wIndex.word;
  131. req_addr_end = (uint32_t) req_bank_size *req_bank_cnt;
  132. sync_errors = 0;
  133. debug(DEBUG_USB,
  134. "USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n",
  135. req_bank_size, req_bank_cnt, req_addr_end);
  136. shared_memory_put(SHARED_MEM_CMD_BANK_COUNT, req_bank_cnt);
  137. if (req_addr == 0x000000) {
  138. timer_start();
  139. }
  140. /*
  141. * -------------------------------------------------------------------------
  142. */
  143. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  144. req_state = REQ_STATUS_BULK_UPLOAD;
  145. req_addr = rq->wValue.word;
  146. req_addr = req_addr << 16;
  147. req_addr = req_addr | rq->wIndex.word;
  148. rx_remaining = rq->wLength.word;
  149. if (req_addr && req_addr % req_bank_size == 0) {
  150. #ifdef FLT_DEBUG
  151. debug(DEBUG_USB,
  152. "USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  153. req_bank, req_addr, timer_stop());
  154. #else
  155. debug(DEBUG_USB,
  156. "USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%i\n",
  157. req_bank, req_addr, timer_stop_int());
  158. #endif
  159. req_bank++;
  160. shared_memory_put(SHARED_MEM_CMD_UPLOAD_PROGESS, req_bank);
  161. sram_bulk_write_start(req_addr);
  162. timer_start();
  163. } else {
  164. sram_bulk_write_start(req_addr);
  165. }
  166. ret_len = USB_MAX_TRANS;
  167. /*
  168. * -------------------------------------------------------------------------
  169. */
  170. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  171. req_state = REQ_STATUS_BULK_UPLOAD;
  172. req_addr = rq->wValue.word;
  173. req_addr = req_addr << 16;
  174. req_addr = req_addr | rq->wIndex.word;
  175. rx_remaining = rq->wLength.word;
  176. #if 0
  177. if (req_addr && (req_addr % 0x1000) == 0) {
  178. debug(DEBUG_USB,
  179. "USB_BULK_UPLOAD_NEXT: bank=0x%02x addr=0x%08lx crc=%04x\n",
  180. req_bank, req_addr, crc_check_bulk_memory(req_addr - 0x1000,
  181. req_addr,
  182. req_bank_size));
  183. }
  184. sram_bulk_write_start(req_addr);
  185. #endif
  186. if (req_addr && (req_addr % req_bank_size) == 0) {
  187. #ifdef FLT_DEBUG
  188. debug(DEBUG_USB,
  189. "USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  190. req_bank, req_addr, timer_stop());
  191. #else
  192. debug(DEBUG_USB,
  193. "USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%i\n",
  194. req_bank, req_addr, timer_stop_int());
  195. #endif
  196. req_bank++;
  197. timer_start();
  198. shared_memory_put(SHARED_MEM_CMD_BANK_CURRENT, req_bank);
  199. sram_bulk_write_start(req_addr);
  200. }
  201. ret_len = USB_MAX_TRANS;
  202. /*
  203. * -------------------------------------------------------------------------
  204. */
  205. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  206. if (req_state != REQ_STATUS_BULK_UPLOAD) {
  207. debug(DEBUG_USB,
  208. "USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n");
  209. return 0;
  210. }
  211. debug(DEBUG_USB, "USB_BULK_UPLOAD_END:\n");
  212. req_state = REQ_STATUS_IDLE;
  213. sram_bulk_write_end();
  214. shared_memory_put(SHARED_MEM_CMD_UPLOAD_END, 0);
  215. ret_len = 0;
  216. /*
  217. * -------------------------------------------------------------------------
  218. */
  219. } else if (rq->bRequest == USB_CRC) {
  220. req_addr = rq->wValue.word;
  221. req_addr = req_addr << 16;
  222. req_addr = req_addr | rq->wIndex.word;
  223. debug(DEBUG_USB, "USB_CRC: addr=0x%08lx \n", req_addr);
  224. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  225. ret_len = 0;
  226. /*
  227. * -------------------------------------------------------------------------
  228. */
  229. } else if (rq->bRequest == USB_MODE_SNES) {
  230. req_state = REQ_STATUS_SNES;
  231. debug(DEBUG_USB, "USB_MODE_SNES:\n");
  232. ret_len = 0;
  233. /*
  234. * -------------------------------------------------------------------------
  235. */
  236. } else if (rq->bRequest == USB_MODE_AVR) {
  237. req_state = REQ_STATUS_AVR;
  238. debug(DEBUG_USB, "USB_MODE_AVR:\n");
  239. ret_len = 0;
  240. /*
  241. * -------------------------------------------------------------------------
  242. */
  243. } else if (rq->bRequest == USB_AVR_RESET) {
  244. debug(DEBUG_USB, "USB_AVR_RESET:\n");
  245. soft_reset();
  246. ret_len = 0;
  247. /*
  248. * -------------------------------------------------------------------------
  249. */
  250. } else if (rq->bRequest == USB_CRC_ADDR) {
  251. req_state = REQ_STATUS_CRC;
  252. req_addr = rq->wValue.word;
  253. req_addr = req_addr << 16;
  254. req_addr = req_addr | rq->wIndex.word;
  255. debug(DEBUG_USB, "USB_CRC_ADDR: addr=0x%lx size=%i\n", req_addr,
  256. rq->wLength.word);
  257. req_size = rq->wLength.word;
  258. req_size = req_size << 2;
  259. tx_remaining = 2;
  260. debug(DEBUG_USB, "USB_CRC_ADDR: addr=0x%lx size=%li\n", req_addr,
  261. req_size);
  262. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  263. tx_buffer[0] = crc & 0xff;
  264. tx_buffer[1] = (crc >> 8) & 0xff;
  265. ret_len = 2;
  266. req_state = REQ_STATUS_IDLE;
  267. }
  268. usbMsgPtr = data_buffer;
  269. return ret_len; /* default for not implemented requests: return no data back to host */
  270. }
  271. /*
  272. * -------------------------------------------------------------------------
  273. */
  274. void test_read_write()
  275. {
  276. uint8_t i;
  277. uint32_t addr;
  278. avr_bus_active();
  279. addr = 0x000000;
  280. i = 1;
  281. while (addr++ <= 0x0000ff) {
  282. sram_write(addr, i++);
  283. }
  284. addr = 0x000000;
  285. while (addr++ <= 0x0000ff) {
  286. info("read addr=0x%08lx %x\n", addr, sram_read(addr));
  287. }
  288. }
  289. void test_bulk_read_write()
  290. {
  291. uint8_t i;
  292. uint32_t addr;
  293. avr_bus_active();
  294. addr = 0x000000;
  295. i = 0;
  296. sram_bulk_write_start(addr);
  297. while (addr++ <= 0x8000) {
  298. sram_bulk_write(i++);
  299. sram_bulk_write_next();
  300. }
  301. sram_bulk_write_end();
  302. addr = 0x000000;
  303. sram_bulk_read_start(addr);
  304. while (addr <= 0x8000) {
  305. info("addr=0x%08lx %x\n", addr, sram_bulk_read());
  306. sram_bulk_read_next();
  307. addr++;
  308. }
  309. sram_bulk_read_end();
  310. }
  311. void test_non_zero_memory(uint32_t bottom_addr, uint32_t top_addr)
  312. {
  313. uint32_t addr = 0;
  314. uint8_t c;
  315. sram_bulk_read_start(bottom_addr);
  316. for (addr = bottom_addr; addr < top_addr; addr++) {
  317. c = sram_bulk_read();
  318. if (c != 0xff)
  319. info("addr=0x%08lx c=0x%x\n", addr, c);
  320. sram_bulk_read_next();
  321. }
  322. sram_bulk_read_end();
  323. }
  324. void test_crc()
  325. {
  326. info("test_crc: clear\n");
  327. avr_bus_active();
  328. sram_bulk_set(0x000000, 0x10000, 0xff);
  329. info("test_crc: crc\n");
  330. crc_check_bulk_memory(0x000000, 0x10000, 0x8000);
  331. info("test_crc: check\n");
  332. test_non_zero_memory(0x000000, 0x10000);
  333. }
  334. uint16_t read_byte_pgm(uint16_t addr)
  335. {
  336. return pgm_read_byte((PGM_VOID_P) addr);
  337. }
  338. uint16_t read_byte_ee(uint16_t addr)
  339. {
  340. return eeprom_read_byte((uint8_t *) addr);
  341. }
  342. void send_reset()
  343. {
  344. info("Reset Snes\n");
  345. snes_reset_on();
  346. snes_reset_lo();
  347. _delay_ms(2);
  348. snes_reset_hi();
  349. snes_reset_off();
  350. }
  351. void send_irq()
  352. {
  353. snes_irq_on();
  354. snes_irq_lo();
  355. _delay_us(20);
  356. snes_irq_hi();
  357. snes_irq_off();
  358. }
  359. void set_rom_mode()
  360. {
  361. if (req_bank_size == 0x8000) {
  362. snes_lorom();
  363. info("Set Snes lowrom \n");
  364. } else {
  365. snes_hirom();
  366. info("Set Snes hirom \n");
  367. }
  368. }
  369. void usb_connect()
  370. {
  371. uint8_t i = 0;
  372. info("USB init\n");
  373. usbDeviceDisconnect(); /* enforce re-enumeration, do this while */
  374. cli();
  375. info("USB disconnect\n");
  376. i = 10;
  377. while (--i) { /* fake USB disconnect for > 250 ms */
  378. led_on();
  379. _delay_ms(35);
  380. led_off();
  381. _delay_ms(65);
  382. }
  383. led_on();
  384. usbDeviceConnect();
  385. info("USB connect\n");
  386. }
  387. void boot_startup_rom()
  388. {
  389. info("Activate AVR bus\n");
  390. avr_bus_active();
  391. info("IRQ off\n");
  392. snes_irq_lo();
  393. snes_irq_off();
  394. snes_lorom();
  395. info("Set Snes lowrom \n");
  396. rle_decode(&_rom, ROM_BUFFER_SIZE, 0x000000);
  397. dump_memory(0x10000 - 0x100, 0x10000);
  398. snes_reset_hi();
  399. snes_reset_off();
  400. snes_irq_lo();
  401. snes_irq_off();
  402. info("IRQ off\n");
  403. snes_hirom();
  404. snes_wr_disable();
  405. info("Disable snes WR\n");
  406. snes_bus_active();
  407. info("Activate Snes bus\n");
  408. _delay_ms(100);
  409. info("Reset Snes\n");
  410. send_reset();
  411. _delay_ms(100);
  412. #if 0
  413. uint8_t i = 0;
  414. i = 20;
  415. info("Wait");
  416. while (--i) {
  417. _delay_ms(500);
  418. info(".");
  419. }
  420. info("\n");
  421. #endif
  422. }
  423. int main(void)
  424. {
  425. uart_init();
  426. stdout = &uart_stdout;
  427. info("Sytem start\n");
  428. system_init();
  429. #if 0
  430. test_read_write();
  431. test_bulk_read_write();
  432. test_crc();
  433. while (1);
  434. #endif
  435. info("Boot startup rom\n");
  436. boot_startup_rom();
  437. usbInit();
  438. usb_connect();
  439. while (1) {
  440. avr_bus_active();
  441. info("Activate AVR bus\n");
  442. info("IRQ off\n");
  443. snes_irq_lo();
  444. snes_irq_off();
  445. info("Set Snes lowrom\n");
  446. snes_lorom();
  447. info("Disable snes WR\n");
  448. snes_wr_disable();
  449. sei();
  450. info("USB poll\n");
  451. while (req_state != REQ_STATUS_SNES) {
  452. usbPoll();
  453. }
  454. shared_memory_put(SHARED_MEM_CMD_TERMINATE, 0);
  455. info("USB poll done\n");
  456. snes_reset_hi();
  457. snes_reset_off();
  458. snes_irq_lo();
  459. snes_irq_off();
  460. info("IRQ off\n");
  461. set_rom_mode();
  462. snes_wr_disable();
  463. info("Disable snes WR\n");
  464. snes_bus_active();
  465. info("Activate Snes bus\n");
  466. _delay_ms(100);
  467. info("Reset Snes\n");
  468. send_reset();
  469. info("Poll\n");
  470. while (req_state != REQ_STATUS_AVR) {
  471. usbPoll();
  472. #ifdef DO_IRQ
  473. uint8_t i;
  474. uint16_t irq_count = 0;
  475. i = 10;
  476. while (--i) {
  477. _delay_ms(100);
  478. }
  479. info("Send IRQ %i\n", ++irq_count);
  480. send_irq();
  481. #endif
  482. #ifdef DO_BUS_STEALING
  483. avr_bus_active();
  484. sram_bulk_read_start(0x003000);
  485. c = sram_bulk_read();
  486. i = 5;
  487. while (--i) {
  488. _delay_ms(500);
  489. info("Wait to switch to snes mode %i\n", i);
  490. }
  491. if (req_bank_size == 0x8000) {
  492. snes_lorom();
  493. info("Set Snes lowrom \n");
  494. } else {
  495. snes_hirom();
  496. info("Set Snes hirom \n");
  497. }
  498. snes_wr_disable();
  499. info("Disable snes WR\n");
  500. snes_bus_active();
  501. info("Activate Snes bus\n");
  502. info("Read 0x3000=%c\n", c);
  503. #endif
  504. }
  505. }
  506. return 0;
  507. }