usbdrvasm20.inc 15 KB

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  1. /* Name: usbdrvasm20.inc
  2. * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
  3. * Author: Jeroen Benschop
  4. * Based on usbdrvasm16.inc from Christian Starkjohann
  5. * Creation Date: 2008-03-05
  6. * Tabsize: 4
  7. * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH
  8. * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
  9. */
  10. /* Do not link this file! Link usbdrvasm.S instead, which includes the
  11. * appropriate implementation!
  12. */
  13. /*
  14. General Description:
  15. This file is the 20 MHz version of the asssembler part of the USB driver. It
  16. requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC
  17. oscillator).
  18. See usbdrv.h for a description of the entire driver.
  19. Since almost all of this code is timing critical, don't change unless you
  20. really know what you are doing! Many parts require not only a maximum number
  21. of CPU cycles, but even an exact number of cycles!
  22. */
  23. #define leap2 x3
  24. #ifdef __IAR_SYSTEMS_ASM__
  25. #define nextInst $+2
  26. #else
  27. #define nextInst .+0
  28. #endif
  29. ;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
  30. ;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte
  31. ; Numbers in brackets are clocks counted from center of last sync bit
  32. ; when instruction starts
  33. ;register use in receive loop:
  34. ; shift assembles the byte currently being received
  35. ; x1 holds the D+ and D- line state
  36. ; x2 holds the previous line state
  37. ; x4 (leap) is used to add a leap cycle once every three bytes received
  38. ; X3 (leap2) is used to add a leap cycle once every three stuff bits received
  39. ; bitcnt is used to determine when a stuff bit is due
  40. ; cnt holds the number of bytes left in the receive buffer
  41. USB_INTR_VECTOR:
  42. ;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
  43. push YL ;[-28] push only what is necessary to sync with edge ASAP
  44. in YL, SREG ;[-26]
  45. push YL ;[-25]
  46. push YH ;[-23]
  47. ;----------------------------------------------------------------------------
  48. ; Synchronize with sync pattern:
  49. ;----------------------------------------------------------------------------
  50. ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
  51. ;sync up with J to K edge during sync pattern -- use fastest possible loops
  52. ;The first part waits at most 1 bit long since we must be in sync pattern.
  53. ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
  54. ;waitForJ, ensure that this prerequisite is met.
  55. waitForJ:
  56. inc YL
  57. sbis USBIN, USBMINUS
  58. brne waitForJ ; just make sure we have ANY timeout
  59. waitForK:
  60. ;The following code results in a sampling window of < 1/4 bit which meets the spec.
  61. sbis USBIN, USBMINUS ;[-19]
  62. rjmp foundK ;[-18]
  63. sbis USBIN, USBMINUS
  64. rjmp foundK
  65. sbis USBIN, USBMINUS
  66. rjmp foundK
  67. sbis USBIN, USBMINUS
  68. rjmp foundK
  69. sbis USBIN, USBMINUS
  70. rjmp foundK
  71. sbis USBIN, USBMINUS
  72. rjmp foundK
  73. sbis USBIN, USBMINUS
  74. rjmp foundK
  75. sbis USBIN, USBMINUS
  76. rjmp foundK
  77. sbis USBIN, USBMINUS
  78. rjmp foundK
  79. #if USB_COUNT_SOF
  80. lds YL, usbSofCount
  81. inc YL
  82. sts usbSofCount, YL
  83. #endif /* USB_COUNT_SOF */
  84. #ifdef USB_SOF_HOOK
  85. USB_SOF_HOOK
  86. #endif
  87. rjmp sofError
  88. foundK: ;[-16]
  89. ;{3, 5} after falling D- edge, average delay: 4 cycles
  90. ;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample
  91. ;use 1 bit time for setup purposes, then sample again. Numbers in brackets
  92. ;are cycles from center of first sync (double K) bit after the instruction
  93. push bitcnt ;[-16]
  94. ; [---] ;[-15]
  95. lds YL, usbInputBufOffset;[-14]
  96. ; [---] ;[-13]
  97. clr YH ;[-12]
  98. subi YL, lo8(-(usbRxBuf));[-11] [rx loop init]
  99. sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init]
  100. push shift ;[-9]
  101. ; [---] ;[-8]
  102. ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected
  103. nop2 ;[-6]
  104. ; [---] ;[-5]
  105. ldi bitcnt, 5 ;[-4] [rx loop init]
  106. sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early)
  107. rjmp haveTwoBitsK ;[-2]
  108. pop shift ;[-1] undo the push from before
  109. pop bitcnt ;[1]
  110. rjmp waitForK ;[3] this was not the end of sync, retry
  111. ; The entire loop from waitForK until rjmp waitForK above must not exceed two
  112. ; bit times (= 27 cycles).
  113. ;----------------------------------------------------------------------------
  114. ; push more registers and initialize values while we sample the first bits:
  115. ;----------------------------------------------------------------------------
  116. haveTwoBitsK:
  117. push x1 ;[0]
  118. push x2 ;[2]
  119. push x3 ;[4] (leap2)
  120. ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit
  121. push x4 ;[7] == leap
  122. ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received
  123. push cnt ;[10]
  124. ldi cnt, USB_BUFSIZE ;[12] [rx loop init]
  125. ldi x2, 1<<USBPLUS ;[13] current line state is K state. D+=="1", D-=="0"
  126. bit0:
  127. in x1, USBIN ;[0] sample line state
  128. andi x1, USBMASK ;[1] filter only D+ and D- bits
  129. rjmp handleBit ;[2] make bit0 14 cycles long
  130. ;----------------------------------------------------------------------------
  131. ; Process bit7. However, bit 6 still may need unstuffing.
  132. ;----------------------------------------------------------------------------
  133. b6checkUnstuff:
  134. dec bitcnt ;[9]
  135. breq unstuff6 ;[10]
  136. bit7:
  137. subi cnt, 1 ;[11] cannot use dec becaus it does not affect the carry flag
  138. brcs overflow ;[12] Too many bytes received. Ignore packet
  139. in x1, USBIN ;[0] sample line state
  140. andi x1, USBMASK ;[1] filter only D+ and D- bits
  141. cpse x1, x2 ;[2] when previous line state equals current line state, handle "1"
  142. rjmp b7handle0 ;[3] when line state differs, handle "0"
  143. sec ;[4]
  144. ror shift ;[5] shift "1" into the data
  145. st y+, shift ;[6] store the data into the buffer
  146. ldi shift, 0x40 ;[7] reset data for receiving the next byte
  147. subi leap, 0x55 ;[9] trick to introduce a leap cycle every 3 bytes
  148. brcc nextInst ;[10 or 11] it will fail after 85 bytes. However low speed can only receive 11
  149. dec bitcnt ;[11 or 12]
  150. brne bit0 ;[12 or 13]
  151. ldi x1, 1 ;[13 or 14] unstuffing bit 7
  152. in bitcnt, USBIN ;[0] sample stuff bit
  153. rjmp unstuff ;[1]
  154. b7handle0:
  155. mov x2,x1 ;[5] Set x2 to current line state
  156. ldi bitcnt, 6 ;[6]
  157. lsr shift ;[7] shift "0" into the data
  158. st y+, shift ;[8] store data into the buffer
  159. ldi shift, 0x40 ;[10] reset data for receiving the next byte
  160. subi leap, 0x55 ;[11] trick to introduce a leap cycle every 3 bytes
  161. brcs bit0 ;[12] it will fail after 85 bytes. However low speed can only receive 11
  162. rjmp bit0 ;[13]
  163. ;----------------------------------------------------------------------------
  164. ; Handle unstuff
  165. ; x1==0xFF indicate unstuffing bit6
  166. ;----------------------------------------------------------------------------
  167. unstuff6:
  168. ldi x1,0xFF ;[12] indicate unstuffing bit 6
  169. in bitcnt, USBIN ;[0] sample stuff bit
  170. nop ;[1] fix timing
  171. unstuff: ;b0-5 b6 b7
  172. mov x2,bitcnt ;[3] [2] [3] Set x2 to match line state
  173. subi leap2, 0x55 ;[4] [3] [4] delay loop
  174. brcs nextInst ;[5] [4] [5] add one cycle every three stuff bits
  175. sbci leap2,0 ;[6] [5] [6]
  176. ldi bitcnt,6 ;[7] [6] [7] reset bit stuff counter
  177. andi x2, USBMASK ;[8] [7] [8] only keep D+ and D-
  178. cpi x1,0 ;[9] [8] [9]
  179. brmi bit7 ;[10] [9] [10] finished unstuffing bit6 When x1<0
  180. breq bitloop ;[11] --- [11] finished unstuffing bit0-5 when x1=0
  181. nop ;--- --- [12]
  182. in x1, USBIN ;--- --- [0] sample line state for bit0
  183. andi x1, USBMASK ;--- --- [1] filter only D+ and D- bits
  184. rjmp handleBit ;--- --- [2] make bit0 14 cycles long
  185. ;----------------------------------------------------------------------------
  186. ; Receiver loop (numbers in brackets are cycles within byte after instr)
  187. ;----------------------------------------------------------------------------
  188. bitloop:
  189. in x1, USBIN ;[0] sample line state
  190. andi x1, USBMASK ;[1] filter only D+ and D- bits
  191. breq se0 ;[2] both lines are low so handle se0
  192. handleBit:
  193. cpse x1, x2 ;[3] when previous line state equals current line state, handle "1"
  194. rjmp handle0 ;[4] when line state differs, handle "0"
  195. sec ;[5]
  196. ror shift ;[6] shift "1" into the data
  197. brcs b6checkUnstuff ;[7] When after shift C is set, next bit is bit7
  198. nop2 ;[8]
  199. dec bitcnt ;[10]
  200. brne bitloop ;[11]
  201. ldi x1,0 ;[12] indicate unstuff for bit other than bit6 or bit7
  202. in bitcnt, USBIN ;[0] sample stuff bit
  203. rjmp unstuff ;[1]
  204. handle0:
  205. mov x2, x1 ;[6] Set x2 to current line state
  206. ldi bitcnt, 6 ;[7] reset unstuff counter.
  207. lsr shift ;[8] shift "0" into the data
  208. brcs bit7 ;[9] When after shift C is set, next bit is bit7
  209. nop ;[10]
  210. rjmp bitloop ;[11]
  211. ;----------------------------------------------------------------------------
  212. ; End of receive loop. Now start handling EOP
  213. ;----------------------------------------------------------------------------
  214. macro POP_STANDARD ; 14 cycles
  215. pop cnt
  216. pop x4
  217. pop x3
  218. pop x2
  219. pop x1
  220. pop shift
  221. pop bitcnt
  222. endm
  223. macro POP_RETI ; 7 cycles
  224. pop YH
  225. pop YL
  226. out SREG, YL
  227. pop YL
  228. endm
  229. #include "asmcommon.inc"
  230. ; USB spec says:
  231. ; idle = J
  232. ; J = (D+ = 0), (D- = 1)
  233. ; K = (D+ = 1), (D- = 0)
  234. ; Spec allows 7.5 bit times from EOP to SOP for replies
  235. ; 7.5 bit times is 100 cycles. This implementation arrives a bit later at se0
  236. ; then specified in the include file but there is plenty of time
  237. bitstuffN:
  238. eor x1, x4 ;[8]
  239. ldi x2, 0 ;[9]
  240. nop2 ;[10]
  241. out USBOUT, x1 ;[12] <-- out
  242. rjmp didStuffN ;[0]
  243. bitstuff7:
  244. eor x1, x4 ;[6]
  245. ldi x2, 0 ;[7] Carry is zero due to brcc
  246. rol shift ;[8] compensate for ror shift at branch destination
  247. nop2 ;[9]
  248. rjmp didStuff7 ;[11]
  249. sendNakAndReti:
  250. ldi x3, USBPID_NAK ;[-18]
  251. rjmp sendX3AndReti ;[-17]
  252. sendAckAndReti:
  253. ldi cnt, USBPID_ACK ;[-17]
  254. sendCntAndReti:
  255. mov x3, cnt ;[-16]
  256. sendX3AndReti:
  257. ldi YL, 20 ;[-15] x3==r20 address is 20
  258. ldi YH, 0 ;[-14]
  259. ldi cnt, 2 ;[-13]
  260. ; rjmp usbSendAndReti fallthrough
  261. ;usbSend:
  262. ;pointer to data in 'Y'
  263. ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
  264. ;uses: x1...x4, btcnt, shift, cnt, Y
  265. ;Numbers in brackets are time since first bit of sync pattern is sent
  266. ;We don't match the transfer rate exactly (don't insert leap cycles every third
  267. ;byte) because the spec demands only 1.5% precision anyway.
  268. usbSendAndReti: ; 12 cycles until SOP
  269. in x2, USBDDR ;[-12]
  270. ori x2, USBMASK ;[-11]
  271. sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
  272. in x1, USBOUT ;[-8] port mirror for tx loop
  273. out USBDDR, x2 ;[-7] <- acquire bus
  274. ; need not init x2 (bitstuff history) because sync starts with 0
  275. ldi x4, USBMASK ;[-6] exor mask
  276. ldi shift, 0x80 ;[-5] sync byte is first byte sent
  277. txByteLoop:
  278. ldi bitcnt, 0x49 ;[-4] [10] binary 01001001
  279. txBitLoop:
  280. sbrs shift, 0 ;[-3] [10] [11]
  281. eor x1, x4 ;[-2] [11] [12]
  282. out USBOUT, x1 ;[-1] [12] [13] <-- out N
  283. ror shift ;[0] [13] [14]
  284. ror x2 ;[1]
  285. didStuffN:
  286. nop2 ;[2]
  287. nop ;[4]
  288. cpi x2, 0xfc ;[5]
  289. brcc bitstuffN ;[6]
  290. lsr bitcnt ;[7]
  291. brcc txBitLoop ;[8]
  292. brne txBitLoop ;[9]
  293. sbrs shift, 0 ;[10]
  294. eor x1, x4 ;[11]
  295. didStuff7:
  296. out USBOUT, x1 ;[-1] [13] <-- out 7
  297. ror shift ;[0] [14]
  298. ror x2 ;[1]
  299. nop ;[2]
  300. cpi x2, 0xfc ;[3]
  301. brcc bitstuff7 ;[4]
  302. ld shift, y+ ;[5]
  303. dec cnt ;[7]
  304. brne txByteLoop ;[8]
  305. ;make SE0:
  306. cbr x1, USBMASK ;[9] prepare SE0 [spec says EOP may be 25 to 30 cycles]
  307. lds x2, usbNewDeviceAddr;[10]
  308. lsl x2 ;[12] we compare with left shifted address
  309. out USBOUT, x1 ;[13] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
  310. subi YL, 20 + 2 ;[0] Only assign address on data packets, not ACK/NAK in x3
  311. sbci YH, 0 ;[1]
  312. ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
  313. ;set address only after data packet was sent, not after handshake
  314. breq skipAddrAssign ;[2]
  315. sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
  316. skipAddrAssign:
  317. ;end of usbDeviceAddress transfer
  318. ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
  319. USB_STORE_PENDING(x2) ;[5]
  320. ori x1, USBIDLE ;[6]
  321. in x2, USBDDR ;[7]
  322. cbr x2, USBMASK ;[8] set both pins to input
  323. mov x3, x1 ;[9]
  324. cbr x3, USBMASK ;[10] configure no pullup on both pins
  325. ldi x4, 5 ;[11]
  326. se0Delay:
  327. dec x4 ;[12] [15] [18] [21] [24]
  328. brne se0Delay ;[13] [16] [19] [22] [25]
  329. out USBOUT, x1 ;[26] <-- out J (idle) -- end of SE0 (EOP signal)
  330. out USBDDR, x2 ;[27] <-- release bus now
  331. out USBOUT, x3 ;[28] <-- ensure no pull-up resistors are active
  332. rjmp doReturn